Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claim(s) 1 is/are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Won (US 2006/0097813).
Regarding claim 1, Won discloses a relaxation oscillator (FIG 1) comprising:
first (MP3) and second (MP1) current sources;
a comparator (14) having a first input (+) connected to the first current source, a second input (-) connected to the second current source and an output (Vout1), wherein one of the first and second inputs is an inverting (-) input and other one of the first and second inputs is a non-inverting (+) input;
a resistive circuit (R4) connected between the first input of the comparator and the ground, wherein the resistive circuit comprises at least a first resistor (VSS); and
a capacitor charging circuit (C1, R1, MN1) connected between the second input of the comparator and the ground, wherein the capacitor charging circuit comprises a capacitor (C1), a second resistor (R1) connected in series with the capacitor and a switch (MN1) connected in parallel with the capacitor, the switch being configured to be controlled based on the output (Vout1) of the comparator (via Q).
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 2-15 is/are rejected under 35 U.S.C. 103 as being unpatentable over Won (US 20060097813) in view of Urs Deniew “Analysis and Design of an Ultralow-Power CMOS Relaxation Oscillator” (cite by the applicant).
Regarding claim 9, Won discloses a differential relaxation oscillator (FIG 1) comprising:
First (MP3), second (MP1) and third (MP2) current sources;
a first comparator (15) having a first input (+) connected to the first current source, a second input (-) connected to the third current source (MP2) and an output (Vout2), wherein one of the first and second inputs of the first comparator is an inverting (-) input and other one of the first and second inputs of the first comparator is a non-inverting (+) input;
a second comparator (14) having a first input (+) connected to the first current source, a second input (-) connected to the second current source (MP1) and an output (Vout1), wherein one of the first and second inputs of the second comparator is an inverting input and other one of the first and second inputs of the second comparator is a non-inverting input, the first input of the second comparator being of the same type as the first input of the first comparator;
a resistive circuit (R4) connected between the first input of the first comparator (15) and the ground (VSS), wherein the resistive circuit comprises at least a first resistor (R4);
a first capacitor charging circuit (C2, MN2, R2) connected between the second input of the first comparator and the ground, wherein the first capacitor charging circuit comprises a first capacitor (C2), a second resistor (R2) connected in series with the first capacitor and a first switch (MN2) connected in parallel with the first capacitor;
a second capacitor charging circuit (C1, MN1, R1) connected between the second input of the second comparator and the ground, wherein the second capacitor charging circuit comprises a second capacitor (C1), a third resistor (R1) connected in series with the second capacitor and a second switch (MN1) connected in parallel with the second capacitor;
Won does not disclose a third, fourth switches and a resetting circuit. However, such circuits are well known in the art (as shown in FIG 1 of Urs Denier as an example for a resetting circuit and a clock divider) that one of ordinary skill in the art would recognize as an obvious variance of switch configuration and therefore, it would have been obvious to one of ordinary skill in the art to modify the circuit of Won to include such switch configuration because such modification would have been an art recognized equivalent switch configuration.
Regarding claim 2|1, Won discloses the relaxation oscillator except further comprising: a falling edge delay circuit connected between the output of the comparator and the switch for delaying switching of the switch so as to enable more complete resetting of a charge of the capacitor when the switch is closed. As is known in the art, such circuit is used to complete discharging capacitors and therefore, it would have been obvious to one of ordinary skill in the art to use such circuit because such a modification would have been a mere inclusion of a routine practice in a switch configuration circuit.
Regarding claim 3|1, Won discloses the relaxation oscillator except further comprising: a clock divider circuit connected to the output of the comparator. As is known in the art, such circuit is used to provide clock signals of interest and therefore, it would have been obvious to one of ordinary skill in the art to use such circuit because such a modification would have been a mere inclusion of a routine practice in an oscillator circuit.
Regarding claim 4|1, Won discloses the relaxation oscillator except wherein the first and second current sources are configured to output substantially equal currents. Such function in the circuit is implied because the circuit of Won is substantially the same as shown in this application.
Regarding claim 5|1, Won discloses the relaxation oscillator except wherein the first and second resistors have, respectively, first and second resistances and, respectively, first and second temperature coefficients selected so as to implement a substantially flat temperature response for the relaxation oscillator as a whole. Such function in the circuit is implied because the circuit of Won is substantially the same as shown in this application.
Regarding claim 6|5|1, Won discloses the relaxation oscillator except wherein the first and second temperature coefficients are both either positive or negative and/or the first resistance is larger than the second resistance and the second temperature coefficient is larger than the first temperature coefficient. Such function in the circuit is implied because the circuit of Won is substantially the same as shown in this application.
Regarding claim 7|5|1, Won discloses the relaxation oscillator except wherein the first resistance, the second resistance, the first temperature coefficient and the second temperature coefficient have values substantially satisfying
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159
539
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where R, Ro, a and ao are, respectively, the first resistance, the second resistance, the first temperature coefficient and the second temperature coefficient and dT is a differential of temperature. Such function in the circuit is implied because the circuit of Won is substantially the same as shown in this application.
Regarding claim 8|1, Won discloses the relaxation oscillator except wherein the falling edge delay circuit comprises
an input,
an output,
a delay element having an input connected to the input of the falling edge delay circuit and an output and
an OR gate having a first input connected to an output of the delay element, a second input connected to the input of the falling edge delay circuit and an output connected to the output of the falling edge delay circuit. As is known in the art, such circuit is used to complete discharging capacitors and therefore, it would have been obvious to one of ordinary skill in the art to use such circuit because such a modification would have been a mere inclusion of a routine practice in a switch configuration circuit.
Regarding claim 10|9, Won discloses the differential relaxation oscillator except wherein the resetting circuit is configured to control the first, second, third and fourth switches so that, at any given time, a state of the third switch matches a state of the second switch and a state of the fourth switch matches a state of the first switch. Such functional features are obvious consequences of the modification to include the third and fourth switches and the resetting circuit.
Regarding claim 11|9, Won discloses the differential relaxation oscillator wherein the resistive circuit consists of the first resistor, the first capacitor charging circuit consists of the first capacitor, the second resistor and the first switch and/or the second capacitor charging circuit consists of the second capacitor, the third resistor and the second switch.
Regarding claim 12|9, Won discloses the differential relaxation oscillator except wherein the first, second and third current sources are configured to output substantially equal currents. Such function in the circuit is implied because the circuit of Won is substantially the same as shown in this application.
Regarding claim 13|9, Won discloses the differential relaxation oscillator except wherein the first, second and third resistors have, respectively, first, second and third resistances and, respectively, first, second and third temperature coefficients selected so as to implement a substantially flat temperature response for the differential relaxation oscillator as a whole. Such function in the circuit is implied because the circuit of Won is substantially the same as shown in this application.
Regarding claim 14|13|9, Won discloses the differential relaxation oscillator except wherein the first, second and third temperature coefficients are all either positive or negative and/or the first resistance is larger than the second resistance and larger than the third resistance and the second and third temperature coefficients are larger than the first temperature coefficient. Such function in the circuit is implied because the circuit of Won is substantially the same as shown in this application.
Regarding claim 15|9, Won discloses the differential relaxation oscillator except wherein the resetting circuit is configured to: receive the outputs of the first and second comparators; cause closing the first and third switches in response to the output of the first comparator corresponding to a first logical value, wherein the first logical value is equal to a logical one or a logical zero; cause opening the first and third switches or keeping the first and third switches open in response to the output of the first comparator corresponding to a second logical value, wherein the second logical value is an opposite logical value to the first logical value; cause closing the second and fourth switches or keeping the first and third switches closed in response to the output of the second comparator corresponding to the first logical value; and cause opening the second and fourth switches or keeping the second and fourth switches open in response to the output of the second comparator corresponding to the second logical value. Such functional features are obvious consequences of the modification to include the third and fourth switches and the resetting circuit.
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure.
Sivakumar (US 2017/0255220) discloses a relaxation oscillator with temperature independent circuit.
Thomsen (US 2014/0176250) discloses a differential relaxation oscillator showing two switch capacitors.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to Joseph Chang whose telephone number is (571)272-1759. The examiner can normally be reached M-F 7:00- 17:00.
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If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Menatoallah M Youssef can be reached at 571-270-3684. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/JOSEPH CHANG/Primary Examiner, Art Unit 2836
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