Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1-20 are rejected under 35 U.S.C. 103 as being unpatentable over Huang, US PGPUB 20200387282 in view of Hung et al., US Patent 11079877 hereinafter referenced as Hung.
As to claim 1, Huang discloses a shift register, comprising: an input circuit, connected to an input terminal, a first clock signal terminal, and a first input node, and configured to transmit an input signal provided by the input terminal to the first input node in response to a first clock signal provided by the first clock signal terminal (e.g., input circuit 110, fig. 1);
a first control circuit, connected to a second voltage terminal, a second clock signal terminal, a third voltage terminal, a second output node, and the first input node, and configured to transmit a second control signal to the second output node under the control of a second clock signal provided by the second clock signal terminal and the voltage at the first input node ([0038] e.g., first control circuit 120, fig. 1, wherein the first control circuit 120 is configured to: bring the first voltage terminal CN into conduction with a second node N2 in response to the third clock signal, received at the third clock signal terminal CK3, being active, thereby supplying the first voltage to the second node N2);
a second control circuit, connected to the third voltage terminal, the first input node, the first output node, and the second output node, and configured to control the first control signal and the second control signal under the control of the voltage at the first input node and the second control signal ([0039] e.g., second control circuit 130, fig. 1, wherein The second control circuit 130 is configured to: bring the fourth voltage terminal VGL into conduction with the first node N1); and
an output circuit, connected to the first output node, the second output node, the second voltage terminal, the third voltage terminal, and an output terminal, and configured to output a signal at the second voltage terminal or the third voltage terminal from the output terminal under the control of the first control signal and the second control signal, wherein the voltage at the first voltage terminal is capable of enabling conduction between the second voltage terminal and the output terminal ([0044] e.g., first output circuit 180, fig. 1, wherein the first output circuit 180 is configured to: bring the first output terminal OUT1 into conduction with the touch signal terminal TX in response to the fifth node N5 being at an active potential).
Huang does not specifically disclose a voltage stabilization circuit, connected to a first voltage terminal, a first output node, and the first input node, and configured to transmit a first control signal to the first output node under the control of a voltage at the first input node.
However, in the same endeavor Hung discloses a voltage stabilization circuit, connected to a first voltage terminal, a first output node, and the first input node, and configured to transmit a first control signal to the first output node under the control of a voltage at the first input node (For example, the display pixel 140 may include a switch transistor whose control terminal is coupled to the first gate line GLa, and include a liquid crystal capacitor and a voltage stablization capacitor, in which the liquid crystal capacitor and the voltage stablization capacitor are coupled between the switch transistor and the common electrodes Com; col. 4, lines 25-28).
Therefore, it would have been obvious to one of ordinary skill in the art to modify the disclosure of Huang to further include Hung’s voltage stabilizer circuit, in order to reduce the power consumption of the device.
As to claim 11, Huang discloses a driving circuit, comprising a plurality of cascaded shift registers, wherein an input circuit, connected to an input terminal, a first clock signal terminal, and a first input node, and configured to transmit an input signal provided by the input terminal to the first input node in response to a first clock signal provided by the first clock signal terminal (e.g., input circuit 110, fig. 1);
a first control circuit, connected to a second voltage terminal, a second clock signal terminal, a third voltage terminal, a second output node, and the first input node, and configured to transmit a second control signal to the second output node under the control of a second clock signal provided by the second clock signal terminal and the voltage at the first input node ([0038] e.g., first control circuit 120, fig. 1, wherein the first control circuit 120 is configured to: bring the first voltage terminal CN into conduction with a second node N2 in response to the third clock signal, received at the third clock signal terminal CK3, being active, thereby supplying the first voltage to the second node N2);
a second control circuit, connected to the third voltage terminal, the first input node, the first output node, and the second output node, and configured to control the first control signal and the second control signal under the control of the voltage at the first input node and the second control signal ([0039] e.g., second control circuit 130, fig. 1, wherein The second control circuit 130 is configured to: bring the fourth voltage terminal VGL into conduction with the first node N1); and
an output circuit, connected to the first output node, the second output node, the second voltage terminal, the third voltage terminal, and an output terminal, and configured to output a signal at the second voltage terminal or the third voltage terminal from the output terminal under the control of the first control signal and the second control signal, wherein the voltage at the first voltage terminal is capable of enabling conduction between the second voltage terminal and the output terminal ([0044] e.g., first output circuit 180, fig. 1, wherein the first output circuit 180 is configured to: bring the first output terminal OUT1 into conduction with the touch signal terminal TX in response to the fifth node N5 being at an active potential).
Huang does not specifically disclose a voltage stabilization circuit, connected to a first voltage terminal, a first output node, and the first input node, and configured to transmit a first control signal to the first output node under the control of a voltage at the first input node.
However, in the same endeavor Hung discloses a voltage stabilization circuit, connected to a first voltage terminal, a first output node, and the first input node, and configured to transmit a first control signal to the first output node under the control of a voltage at the first input node (For example, the display pixel 140 may include a switch transistor whose control terminal is coupled to the first gate line GLa, and include a liquid crystal capacitor and a voltage stablization capacitor, in which the liquid crystal capacitor and the voltage stablization capacitor are coupled between the switch transistor and the common electrodes Com; col. 4, lines 25-28).
Therefore, it would have been obvious to one of ordinary skill in the art to modify the disclosure of Huang to further include Hung’s voltage stabilizer circuit, in order to reduce the power consumption of the device.
As to claim 12, Huang discloses a display panel, comprising: a driving backplane, comprising a plurality of pixel circuits and first driving circuits, wherein the plurality of pixel circuits are arranged in an array along a row direction and a column direction, and an output terminal of one of the first driving circuits is connected to at least one row of the pixel circuits ([0079], a display panel of the touch display panel 310 comprises a plurality of pixels arranged in a matrix (not shown). Each of the pixels can be electrically connected to a corresponding one of the gate lines GL and a corresponding one of the data lines DL); and
light-emitting devices, arranged in an array on a side of the driving backplane ([0079] The display panel of the touch display panel 310 can be a liquid crystal display panel, an organic light emitting diode (OLED) display panel or a display panel of any other suitable type),
wherein the first driving circuit comprises a plurality of cascaded shift registers, and the shift register comprises: an input circuit, connected to an input terminal, a first clock signal terminal, and a first input node, and configured to transmit an input signal provided by the input terminal to the first input node in response to a first clock signal provided by the first clock signal terminal (e.g., input circuit 110, fig. 1);
a first control circuit, connected to a second voltage terminal, a second clock signal terminal, a third voltage terminal, a second output node, and the first input node, and configured to transmit a second control signal to the second output node under the control of a second clock signal provided by the second clock signal terminal and the voltage at the first input node ([0038] e.g., first control circuit 120, fig. 1, wherein the first control circuit 120 is configured to: bring the first voltage terminal CN into conduction with a second node N2 in response to the third clock signal, received at the third clock signal terminal CK3, being active, thereby supplying the first voltage to the second node N2);
a second control circuit, connected to the third voltage terminal, the first input node, the first output node, and the second output node, and configured to control the first control signal and the second control signal under the control of the voltage at the first input node and the second control signal ([0039] e.g., second control circuit 130, fig. 1, wherein The second control circuit 130 is configured to: bring the fourth voltage terminal VGL into conduction with the first node N1); and
an output circuit, connected to the first output node, the second output node, the second voltage terminal, the third voltage terminal, and an output terminal, and configured to output a signal at the second voltage terminal or the third voltage terminal from the output terminal under the control of the first control signal and the second control signal, wherein the voltage at the first voltage terminal is capable of enabling conduction between the second voltage terminal and the output terminal ([0044] e.g., first output circuit 180, fig. 1, wherein the first output circuit 180 is configured to: bring the first output terminal OUT1 into conduction with the touch signal terminal TX in response to the fifth node N5 being at an active potential).
Huang does not specifically disclose a voltage stabilization circuit, connected to a first voltage terminal, a first output node, and the first input node, and configured to transmit a first control signal to the first output node under the control of a voltage at the first input node.
However, in the same endeavor Hung discloses a voltage stabilization circuit, connected to a first voltage terminal, a first output node, and the first input node, and configured to transmit a first control signal to the first output node under the control of a voltage at the first input node (For example, the display pixel 140 may include a switch transistor whose control terminal is coupled to the first gate line GLa, and include a liquid crystal capacitor and a voltage stablization capacitor, in which the liquid crystal capacitor and the voltage stablization capacitor are coupled between the switch transistor and the common electrodes Com; col. 4, lines 25-28).
Therefore, it would have been obvious to one of ordinary skill in the art to modify the disclosure of Huang to further include Hung’s voltage stabilizer circuit, in order to reduce the power consumption of the device.
As to claim 2, the combination of Huang and Hung discloses the shift register according to claim 1. The combination further discloses the first control circuit comprises: a first control subcircuit, connected to a second input node, the second voltage terminal, and the second clock signal terminal, and configured to be turned on or off under the control of the second clock signal; a second control subcircuit, connected to a connection node, the first input node, and the third voltage terminal, and configured to be turned on or off under the control of the voltage at the first input node; and a third control subcircuit, connected to the second input node and the connection node, and configured to be turned on or off under the control of a voltage at the third voltage terminal (Huang, [0005] a first control circuit, configured to: bring the first voltage terminal into conduction with a second node in response to the third clock signal received at the third clock signal terminal being active; and bring the second voltage terminal into conduction with the second node in response to the fourth clock signal received at the fourth clock signal terminal being active).
As to claim 3, the combination of Huang and Hung discloses the shift register according to claim 2. The combination further discloses the first control subcircuit comprises a first control transistor, the second control subcircuit comprises a second control transistor, and the third control subcircuit comprises a third control transistor and a first capacitor; the first control transistor has a gate connected to the second clock signal terminal, a first terminal connected to the second voltage terminal, and a second terminal connected to the second input node; the second control transistor has a gate connected to the first input node, a first terminal connected to the third voltage terminal, and a second terminal connected to the connection node; and the third control transistor has a gate connected to the connection node through the first capacitor, a first terminal connected to the connection node, and a second terminal connected to the second input node (Huang, [0049] The first transistor T1 has a gate connected to the input terminal IN, a first electrode connected to the first voltage terminal CN, and a second electrode connected to the first node N1. A gate of the second transistor T2 is connected to the reset terminal RST, a first electrode thereof is connected to the first node N1, and a second electrode thereof is connected to the second voltage terminal CNB).
As to claim 4, the combination of Huang and Hung discloses the shift register according to claim 1. The combination further discloses the voltage stabilization circuit comprises a voltage stabilization transistor and a second capacitor; and the voltage stabilization transistor has a gate connected to the first input node and the second capacitor, a first terminal connected to the first voltage terminal, and a second terminal connected to the second capacitor and the first output node (Hung, for example, the display pixel 140 may include a switch transistor whose control terminal is coupled to the first gate line GLa, and include a liquid crystal capacitor and a voltage stablization capacitor, in which the liquid crystal capacitor and the voltage stablization capacitor are coupled between the switch transistor and the common electrodes Com; col. 4, lines 25-28).
As to claim 5, the combination of Huang and Hung discloses the shift register according to claim 1. The combination further discloses the second control circuit comprises a fourth control subcircuit and a fifth control subcircuit; the fourth control subcircuit is connected to the third voltage terminal, the first input node, and the second output node, and is configured to control the second control signal under the control of the voltage at the first input node; and the fifth control subcircuit is connected to the third voltage terminal, the first output node, and the second output node, and is configured to control the first control signal under the control of a voltage at the second output node (Huang, [0014] According to an exemplary embodiment, the fifth control circuit comprises: a fifteenth transistor, a gate thereof being connected to the third node, a first electrode thereof being connected to the touch control signal terminal, and a second electrode thereof being connected to the fifth node).
As to claim 6, the combination of Huang and Hung discloses the shift register according to claim 5. The combination further discloses the fourth control subcircuit comprises a fourth control transistor, and the fifth control subcircuit comprises a fifth control transistor; the fourth control transistor has a gate connected to the first input node, a first terminal connected to the third voltage terminal, and a second terminal connected to the second output node; and the fifth control transistor has a gate connected to the second output node, a first terminal connected to the third voltage terminal, and a second terminal connected to the first output node (Huang, [0012] According to an exemplary embodiment, the fourth control circuit comprises: an eighth transistor, a gate thereof being connected to the third voltage terminal, a second electrode thereof being connected to the first node).
As to claim 7, the combination of Huang and Hung discloses the shift register according to claim 1. The combination further discloses the input circuit comprises an input transistor, and the input transistor has a gate connected to the first clock signal terminal, a first terminal connected to the input terminal, and a second terminal connected to the first input node; the output circuit comprises a first output transistor, a third capacitor, a second output transistor, and a fourth capacitor; the first output transistor has a gate connected to the first output node, a first terminal connected to the second voltage terminal, and a second terminal connected to the output terminal, and the third capacitor connects the first output node and the second voltage terminal; and the second output transistor has a gate connected to the second output node, a first terminal connected to the third voltage terminal, and a second terminal connected to the output terminal, and the fourth capacitor connects the second output node and the third voltage terminal (Huang, [0038] The first control circuit 120 is configured to: bring the first voltage terminal CN into conduction with a second node N2 in response to the third clock signal, received at the third clock signal terminal CK3, being active, thereby supplying the first voltage to the second node N2; and bring the second voltage terminal CNB into conduction with the second node N2 in response to the fourth clock signal, received at the fourth clock signal terminal CK4, being active, thereby supplying the second voltage to the second node N2).
As to claim 8, the combination of Huang and Hung discloses the shift register according to claim 2. The combination further discloses the shift register further comprises: a first isolation circuit connecting the first input node and the voltage stabilization circuit (Hung, 1n the present embodiment, since the sensing line SL1 and the data line DL2 are separated by a longer distance, the noise on the sensing line SL1 is caused by almost the data line DL1. Similarly, the noise on the sensing line SL2 is caused by almost the data line DL2; col. 7, lines 60-64).
As to claim 9, the combination of Huang and Hung discloses the shift register according to claim 8. The combination further discloses the shift register further comprises: a second isolation circuit connecting the connection node and the second output node (Hung, 1n the present embodiment, since the sensing line SL1 and the data line DL2 are separated by a longer distance, the noise on the sensing line SL1 is caused by almost the data line DL1. Similarly, the noise on the sensing line SL2 is caused by almost the data line DL2; col. 7, lines 60-64).
As to claim 10, the combination of Huang and Hung discloses the shift register according to claim 9. The combination further discloses the first isolation circuit comprises a first isolation transistor, and the second isolation circuit comprises a second isolation transistor; the first isolation transistor has a gate connected to the second voltage terminal, a first terminal connected to the first input node, and a second terminal connected to the voltage stabilization circuit; and the second isolation transistor has a gate connected to the second voltage terminal, a first terminal connected to the connection node, and a second terminal connected to the second output node (Hung, As shown in FIG. 7, by alternately superimposing the first coupling signal Pe1 and the second coupling signal Pe2 on the sensing signals SS2 and SS1, respectively, the sensing signals SS1 and SS2 will have noises that have the same waveform and are completely cancelled out in the differential amplifier Op).
As to claim 13, the combination of Huang and Hung discloses the display panel according to claim 12. The combination further discloses the pixel circuit comprises a plurality of transistors, the number of the first driving circuits is two, and the display panel further comprises a second driving circuit; in the same pixel circuit, gates of some transistors are connected to the output terminal of the first driving circuit, and gates of some other transistors are connected to an output terminal of the second driving circuit; and the two first driving circuits are connected to gates of different transistors in the pixel circuit (Huang, [0057] Besides, the fourth node N4 is further connected with the third output terminal OUT3 such that the signal at the fourth node N4 can be outputted as a third output signal. The third output signal can be used as an input signal of the next stage touch electrode driving circuit, and/or as a reset signal of the previous stage touch electrode driving circuit).
As to claim 14, the combination of Huang and Hung discloses the display panel according to claim 13. The combination further discloses the pixel circuit comprises a driving transistor, a writing transistor, a compensation transistor, a first reset transistor, a second reset transistor, a first light-emitting control transistor, a second light-emitting control transistor, and a storage capacitor; the first reset transistor and the compensation transistor are N-type metal oxide transistors, and the driving transistor, the writing transistor, the second reset transistor, the first light-emitting control transistor, and the second light-emitting control transistor are P-type polysilicon transistors; the first light-emitting control transistor has a first terminal used to receive a first power signal and a second terminal connected to a first terminal of the driving transistor, a second terminal of the driving transistor is connected to a first terminal of the second light-emitting control transistor, and a second terminal of the second light-emitting control transistor is connected to the light-emitting device; the compensation transistor has a first terminal connected to the second terminal of the driving transistor and a second terminal connected to a gate of the driving transistor; the first reset transistor has a first terminal used to receive a first reset signal and a second terminal connected to a second terminal of the compensation transistor; the second reset transistor has a first terminal used to receive a second reset signal and a second terminal connected to the second terminal of the driving transistor; the writing transistor has a first terminal used to receive a data signal and a second terminal connected to the first terminal of the driving transistor; the storage capacitor has a first plate connected to the gate of the driving transistor and a second plate used to receive the first power signal; a gate of the first reset transistor and a gate of the compensation transistor are connected to the output terminal of one of the first driving circuits; a gate of the first light-emitting control transistor and a gate of the second light-emitting control transistor are connected to the output terminal of the other of the first driving circuits; and a gate of the writing transistor and a gate of the second reset transistor are connected to the output terminal of the second driving circuit (Hung, when the light irradiates the transistors M2 and M3 through the light filters 210 and 220, the transistors M2-M3 charge the storage capacitor Cs. The transistors M4-M5 can be configured to prevent the transistors M2-M3 from erroneously charging the storage capacitor Cs due to the ambient light; col. 3, lines 65-67).
As to claim 15, the combination of Huang and Hung discloses the shift register according to claim 1. The combination further discloses the driving method comprises: in a first stage, turning on the input circuit and turning off the first control circuit by the first clock signal and the second clock signal, turning on the voltage stabilization circuit, and enabling conduction between the second voltage terminal and the output terminal and disabling conduction between the third voltage terminal and the output terminal under the control of the first control signal; in a second stage, turning off the input circuit and turning on the first control circuit by the first clock signal and the second clock signal, turning on the voltage stabilization circuit, and enabling conduction between the second voltage terminal and the output terminal and disabling conduction between the third voltage terminal and the output terminal under the control of the voltage at the first voltage terminal, the first control signal, and the second control signal; in a third stage, turning on the input circuit by the first clock signal and the second clock signal, turning off the voltage stabilization circuit, and enabling conduction between the second voltage terminal and the output terminal and disabling conduction between the third voltage terminal and the output terminal under the control of the voltage at the first voltage terminal, the first control signal, and the second control signal; and in a fourth stage, turning off the input circuit by the first clock signal and the second clock signal, turning off the voltage stabilization circuit, and disabling conduction between the second voltage terminal and the output terminal and enabling conduction between the third voltage terminal and the output terminal under the control of the voltage at the third voltage terminal, the first control signal, and the second control signal (Huang, [0036] FIG. 1 is an exemplary block diagram of a touch electrode driving circuit according to an exemplary embodiment. Referring to FIG. 1, touch electrode driving circuit 100 comprises: an input terminal IN operable to receive an input pulse; a reset terminal RST operable to receive a reset pulse; a first voltage terminal CN operable to be applied with a first voltage; a second voltage terminal CNB operable to be applied with a second voltage; a third voltage terminal VGH operable to be applied with a third voltage; a fourth voltage terminal VGL operable to be applied with a fourth voltage; a common voltage signal terminal VCOM operable to be applied with a common voltage signal; a first common voltage signal control terminal VCOM_EN1 operable to be applied with a first common voltage control signal; a second common voltage signal control terminal VCOM_EN2 operable to be applied with a second common voltage control signal; a first clock signal terminal CK1 operable to receive a first clock signal; a second clock signal terminal CK2 operable to receive a second clock signal; a third clock signal terminal CK3 operable to receive a third clock signal; a fourth clock signal terminal CK4 operable to receive a fourth clock signal).
As to claim 16, the combination of Huang and Hung discloses the shift register according to claim 15. The combination further discloses an absolute value of the voltage at the first voltage terminal is greater than an absolute value of a voltage at the second voltage terminal (Hung, for example, the capacitance value of the variable capacitor of the first coupling circuit 322a is positively correlated to the capacitance value of the load capacitor Co on the sensing line SL1, and the capacitance value of the variable capacitor of the second coupling circuit 322b is positively correlated to the capacitance value of the load capacitor Co on the sensing line SL2, and so on; col. 6, lines 33-40).
As to claim 17, the combination of Huang and Hung discloses the shift register according to claim 16. The combination further discloses an absolute value of a difference between the absolute value of the voltage at the first voltage terminal and the absolute value of the voltage at the second voltage terminal is 3V (Hung, for example, the capacitance value of the variable capacitor of the first coupling circuit 322a is positively correlated to the capacitance value of the load capacitor Co on the sensing line SL1, and the capacitance value of the variable capacitor of the second coupling circuit 322b is positively correlated to the capacitance value of the load capacitor Co on the sensing line SL2, and so on; col. 6, lines 33-40).
As to claim 18, the combination of Huang and Hung discloses the shift register according to claim 15. The combination further discloses a pulse width of the input signal is n times a pulse width of the first clock signal and the second clock signal, where n is a positive integer (Huang, [0064] Signals of the touch control signal terminal TX_EN are square wave pulse signals for sampling signals of the touch signal terminal TX, and the signals of the touch signal terminal TX are a group of high frequency pulse signals for detecting and scanning touch signals).
As to claim 19, the combination of Huang and Hung discloses the driving circuit according to claim 11. The combination further discloses the first control circuit comprises: a first control subcircuit, connected to a second input node, the second voltage terminal, and the second clock signal terminal, and configured to be turned on or off under the control of the second clock signal; a second control subcircuit, connected to a connection node, the first input node, and the third voltage terminal, and configured to be turned on or off under the control of the voltage at the first input node; and a third control subcircuit, connected to the second input node and the connection node, and configured to be turned on or off under the control of a voltage at the third voltage terminal (Huang, [0066] The first clock signal terminal CK1 and the third node N3 are in conduction by the switching-on of the ninth transistor T9, and the second clock signal terminal CK2 and the fourth node N4 are in conduction by the switching-on of the twelfth transistor T12).
As to claim 20, the combination of Huang and Hung discloses the driving circuit according to claim 19. The combination further discloses the first control subcircuit comprises a first control transistor, the second control subcircuit comprises a second control transistor, and the third control subcircuit comprises a third control transistor and a first capacitor; the first control transistor has a gate connected to the second clock signal terminal, a first terminal connected to the second voltage terminal, and a second terminal connected to the second input node; the second control transistor has a gate connected to the first input node, a first terminal connected to the third voltage terminal, and a second terminal connected to the connection node; and the third control transistor has a gate connected to the connection node through the first capacitor, a first terminal connected to the connection node, and a second terminal connected to the second input node (Huang, A gate of the fifth transistor T5 is connected to the third voltage terminal VGH, and a first electrode thereof is connected to the second node N2. A second electrode of the third transistor T3, a first electrode of the fourth transistor T4 and a second electrode of the fifth transistor T5 are connected together. The voltage at the third voltage terminal VGH keeps the voltage signal at the gate of the fifth transistor T5 at an active potential, so the fifth transistor T5 is in a normally-on state such that the first electrode and the second electrode thereof are always in conduction).
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure.
Zheng, US PGPUB 20210358367 discloses a shift register and a driving method thereof, a gate drive circuit, and a display device are provided. The shift register includes: an input circuit, configured to input an input voltage provided by the input voltage terminal to an intermediate circuit under control of a first clock signal provided by the first clock signal terminal; the intermediate circuit, configured to write a second clock signal output by the second clock signal terminal or a first power signal output by the first power terminal to the intermediate output terminal as an intermediate output signal under control of the input voltage and the control circuit; and an output circuit, configured to output an output signal, a phase of which is opposite to a phase of the intermediate output signal.
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/SAHLU OKEBATO/Primary Examiner, Art Unit 2625 7/10/2026
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