DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Specification
The title of the invention is not descriptive. A new title is required that is clearly indicative of the invention to which the claims are directed.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 1, 4, 6-9, and 13-15 is/are rejected under 35 U.S.C. 103 as being unpatentable over Sakakibara et al. (U.S. Pub. No. 20180152650) in view of Mao et al. (U.S. Pub No. 20170347047).
Regarding claim 1, Sakakibara discloses:
A light detection element (each pixel 21 within the pixel array unit 12, where each pixel 21 within the pixel array unit 12 is configured of the pixel circuit 41 and the ADC 42, par. 72, 83, and Figs. 1-4 and 13) comprising:
a photoelectric conversion section that is provided in a semiconductor substrate and generates a charge corresponding to incident light (photodiode (PD) 321 of pixel circuit 41 is a photoelectric conversion element, and on the first semiconductor substrate 351A, the pixel circuit 41 and circuits of the transistors 81, 82, and 85 in the differential input circuit 61 of the ADC 42 are formed, par. 299 and Figs. 4, 13, and 36);
a first accumulation section that accumulates the charge generated by the photoelectric conversion section (FD (floating diffusion layer) 323, where first transfer transistor 322 transfers a charge generated by the photodiode 321 to the FD 323, par. 179-180);
an amplification transistor that generates an input signal corresponding to an amount of the charges accumulated in the first accumulation section (transistor 82, where processing permits the transistor 82 in the differential input circuit 61 (of ADC 42) to function as an amplifier transistor of the pixel circuit 41, where pixel circuit 41 outputs charge signals as the analog pixel signal SIG to the ADC 42 on the basis of the amount of received light, par. 84 and 181);
a second accumulation section to which a saturated charge is transferred from the photoelectric conversion section via the first accumulation section (lateral over flow integration capacitor 325 (LOFIC 325), where first transfer transistor 322 transfers a charge generated by the photodiode 321 to the FD 323, and the second transfer transistor 324 transfers a charge exceeding the saturated amount of charges of the photodiode 321, in other words, a charge overflowed from the photodiode 321 to the LOFIC 325 via the FD323 and the LOFIC 325 accumulates the charge overflowed from the photodiode 321, par. 180 and Fig. 13);
a conversion efficiency switching transistor that transfers the saturated charge to the second accumulation section to switch a conversion efficiency (second transfer transistor 324, where second transfer transistor 324 transfers a charge exceeding the saturated amount of charges of the photodiode 321, in other words, a charge overflowed from the photodiode 321 to the LOFIC 325 via the FD323, where in the case of the high-light intensity, a charge accumulated in the photodiode 321 is held in both of the FD 323 and the LOFIC 325, and on the other hand, in the case of the low-light intensity, the charge accumulated in the photodiode 321 is held only in the FD 323, and through this processing, a conversion efficiency can be switched in accordance with the amount of received light and the pixel signal can be obtained with a high gain at the time of the low-light intensity, par. 179-180 and 353);
a reset transistor that resets the charge accumulated in the first accumulation section and the saturated charge accumulated in the second accumulation section (reset transistor 326 resets a charge held in the FD 323 and the LOFIC 325, par. 181); and
a differential input circuit that compares the input signal generated by the amplification transistor with a reference signal and outputs a comparison result (differential input circuit 61 compares the pixel signal SIG output from the pixel circuit 41 and the reference signal REF output from the slope generator 14 and, when the pixel signal SIG is higher than the reference signal REF, and outputs a predetermined signal (current), where transistor 82 in the differential input circuit 61 (of ADC 42) functions as an amplifier transistor of the pixel circuit 41 using analog pixel signal SIG output from pixel circuit 41, par. 84, 100, 181),
wherein the second accumulation section includes
a capacitor (lateral over flow integration capacitor 325 (LOFIC 325), par. 179-180).
Sakakibara is silent with regards to the capacitor being a metal insulator metal (MIM) capacitor having a three-dimensional structure or a metal oxide semiconductor (MOS) capacitor. Mao discloses the capacitor being a metal insulator metal (MIM) capacitor having a three-dimensional structure or a metal oxide semiconductor (MOS) capacitor (capacitor C is a lateral overflow integrating capacitor (LOFIC) and any excess charge in the pixels/subpixels will be stored on LOFIC, and capacitor C may be implemented as a MOS capacitor, a metal-insulator-metal (MIM) capacitor or combinations of types of capacitor, and one side has a metal layer connected to ground, and where the LOFIC capacitor can be a plurality of LOFIC capacitors in a semiconductor substrate chip stacked on a semiconductor substrate chip that includes the photodiode, par. 28, 33, 36, 55-57, and Figs. 2, 3, and 10). As can be seen in par. 33, 36, and 57 this is advantageous in that dynamic range can be increased. Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to include the capacitor being a metal insulator metal (MIM) capacitor having a three-dimensional structure or a metal oxide semiconductor (MOS) capacitor.
Regarding claim 4, see the rejection of claim 1 and note that Mao was shown to disclose second accumulation section includes a plurality of the MIM capacitors (LOFIC capacitor can be a plurality of LOFIC capacitors, par. 55-57 and Fig. 10).
Regarding claim 6, see the rejection of claim 1 and note that Mao was shown to discloses MIM capacitor is provided in a wiring layer stacked on the semiconductor substrate (metal-insulator-metal (MIM) LOFIC capacitor can be a plurality of metal-insulator-metal (MIM) LOFIC capacitors in a semiconductor substrate chip stacked on a semiconductor substrate sensor chip that includes the photodiode, par. 28, 33, 36, 55-57, and Figs. 2, 3, and 10).
Regarding claim 7, see the rejection of claim 1 and note that Mao was shown to disclose MOS capacitor includes an oxide film provided on the semiconductor substrate and an electrode provided on the oxide film (capacitor C may be implemented as a MOS (stacked metal-oxide-semiconductor) capacitor in a semiconductor substrate chip stacked on a semiconductor substrate sensor chip that includes the photodiode, par. 28, 33, 36, 55-57, and Figs. 2, 3, and 10).
Regarding claim 8, see the rejection of claim 7 and note that Mao was shown to disclose electrode is electrically connected to a power supply, a ground, or a well region of the semiconductor substrate (one side has a metal layer connected to ground, par. 28, 33, 36, 55-57, and Figs. 2, 3, and 10).
Regarding claim 9, see the rejection of claim 1 and note that Mao was shown to disclose second accumulation section includes a plurality of the MOS capacitors (LOFIC capacitor can be a plurality of LOFIC capacitors, par. 55-57 and Fig. 10).
Regarding claim 13, see the rejection of claim 1 and note that Sakakibara further discloses:
one terminal of the second accumulation section is electrically connected to one or a plurality of connection pads for connection to a power supply or a ground via wiring (one side of lateral over flow integration capacitor 325 (LOFIC 325) is connected to a wire connected to ground, Figs. 4 and 13).
Regarding claim 14, Sakakibara further discloses:
a positive feedback circuit connected to the differential input circuit (positive feedback circuit 63 is connected to differential input circuit 61 through voltage conversion circuit 62, par. 106 and Fig. 4 and 13); and
a storage section connected to the positive feedback circuit (latch storage unit 52 connected to positive feedback circuit 63, par. 95, 108, 112 and Figs. 4 and 13).
Regarding claim 15, see the rejection of claim 1 and note that Sakakibara further discloses that the light detection element is on a light detection device (pixel array unit 12 has a region in which pixels 21 are arrayed in a matrix form, par. 72) and is mounted within an electronic apparatus (solid-state image pickup device 1 of FIG. 1 includes a pixel array unit 12 and the imaging device is an electronic apparatus, par. 70, 355, 356).
Claim(s) 2 and 3 is/are rejected under 35 U.S.C. 103 as being unpatentable over Sakakibara et al. (U.S. Pub. No. 20180152650) in view of Mao et al. (U.S. Pub No. 20170347047) in further view of Chen et al. (U.S. Pub. No. 20220302019).
Regarding claim 2, note that Mao was shown to disclose the MIM capacitor has a stacked structure including a pair of metal layers sandwiching an insulating layer (metal-insulator-metal (MIM) capacitor, par. 33).
Mao is silent with regards to a cross section along a stacking direction of the stacked structure has a substantially rectangular wave shape. Chen discloses MEM capacitor has a cross section along a stacking direction of the stacked structure has a substantially rectangular wave shape (the MIM capacitor 100 has a plurality of notches n1 and n2 on opposite edges 106b and 106c, where it can be seen in Fig. 2B that a rectangular shape is formed of two of third segments 106b3 and first segment 106b1 or a rectangular shape is formed of two of third segments 106b3 and second segment 106b2, par. 44 and Fig. 2B). As can be seen in par. 44 this is advantageous in that the edges can have a shortened distance to the peripheral metal vias. Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to include a cross section along a stacking direction of the stacked structure has a substantially rectangular wave shape.
Regarding claim 3, see the rejection of claim 2 and note that Mao was shown to have one of the pair of metal layers is electrically connected to a power supply, a ground, or a well region of the semiconductor substrate (one side of MIM capacitor has a metal layer connected to ground, Figs. 2, 3, and 10).
Allowable Subject Matter
Claims 5, 10, 11, and 12 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
Regarding claim 5, no prior art could be located that teaches or fairly suggests one of the pair of metal layers of each of the plurality of MIM capacitors is electrically connected to one destination selected from a power source, a ground, or a well region of the semiconductor substrate, the selected destination of one of the plurality of MIM capacitors being different from that of another of the plurality of MIM capacitors, in combination with the rest of the limitations of the claim and parent claims.
Regarding claim 10, no prior art could be located that teaches or fairly suggests the electrode of each of the plurality of MOS capacitors is electrically connected to one destination selected from a power source, a ground, or a well region of the semiconductor substrate, the selected destination of one of the plurality of MOS capacitors being different from that of another of the plurality of MOS capacitors, in combination with the rest of the limitations of the claim and parent claims.
Regarding claim 11, no prior art could be located that teaches or fairly suggests light detection element further comprises: a pixel separation section that penetrates the semiconductor substrate in a film thickness direction of the semiconductor substrate and defines the photoelectric conversion section; and a diffusion region provided between the photoelectric conversion section and the pixel separation section and containing an impurity of a second conductivity type different from the first conductivity type, in combination with the rest of the limitations of the claim and parent claim.
Claim 12 depends on claim 11 and therefore is objected to.
Conclusion
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/NICHOLAS G GILES/ Primary Examiner, Art Unit 2639
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