Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Response to Amendment
The office action is responding to the arguments filed on 06/22/2026. Claims 1-
10 are pending.
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claim(s) 1-2, 5 and 8 are rejected under 35 U.S.C. 102(a)(1) as being
anticipated by YONEMURA et al. (US 20190171585 A1) hereinafter YONEMURA.
Regarding claim 1, YONEMURA teaches A control device, comprising: at
least one data processing unit; (See Fig 3, paragraph [0035], illustrates hardware unit 30 includes the processor unit 20, a memory unit 23, a memory access control unit 22, the storage 28)
at least one nonvolatile memory for storing program code for the data processing unit; and (See Fig 3, paragraph [0232], illustrates computer program meant to implement processing operations may be stored in memory storage devices)
at least one interface for accessing services provided by the control device; (See Fig 1 and 3, paragraph [0232], illustrates information processing unit 10 has memory accessing unit 25A and memory control unit 22 which control the accesses to the memory unit 23)
wherein the control device is configured to start in an open operating mode if a predetermined memory area of the at least one nonvolatile memory does not contain any data; (See Fig 3, 4 and 5, paragraph [0081], illustrates at SEQ204 the memory accessing unit processing unit 25A identifies from the non-secure page table 34 the target physical addresses for writing operations in non-secure or open operating mode)
to provide, in the open operating mode, a first service for writing keys to the predetermined memory area; (See Fig 3, 4 and 5, paragraph [0082] and [0086], illustrates at SEQ206 non-secure processing unit 25 issues a first-type switching instruction or key to the monitoring unit 27 for switching the mode to the secure mode S and at SEQ214 secure application 33 and the secure processing unit 26 perform writing protection function)
to start in a protected operating mode if the predetermined memory area contains data; and (See Fig 3, 4 and 5, paragraph [0087], illustrates at SEQ218 secure processing unit 26 does the secure mode write operation of the communication data to the storage area 28)
to provide, in the open operating mode, a first service for writing keys to the predetermined memory area; or to start in a protected operating mode if the pre-determined memory area contains data and to provide, in the protected operating mode, at least one second service for querying and/or changing data stored in the at least one data processing unit and/or the at least one nonvolatile memory; wherein accesses to the second service in the protected operating mode are safeguarded by at least one key stored in the predetermined memory area. (See Fig 3, 4 and 5, paragraph [0087], illustrates at SEQ216 secure processing unit 26 uses a storage key in protected mode and cancels the writing restriction with respect to such an area in the storage 28 and it is safeguarded which is indicated and queried by physical address for writing operations)
Regarding claim 2, YONEMURA teaches The control Device (1) as claimed in claim 1, wherein the control device (1) is furthermore configured
to provide, in the open operating mode (S1), a third service for writing validation data, in particular a checksum and/or a validation pattern, for keys stored in the predetermined memory area (9e); and (See Fig 3, 4 and 5, paragraph [0093], illustrates at SEQ236 as third operation, non-secure processing unit 25 determines and analyses or checks headers of the frames or data which was written in the previous non-secure mode)
to check, in the protected operating mode (S2), an unchanged state of the keys stored in the predetermined memory area (9e) by means of the validation data before a query and/or change according to the at least one second service (10b, 10c, 10e) is answered and/or carried out. (See Fig 3, 4 and 5, paragraph [0104], illustrates at step SEQ256 the secure application 33 performs logging in or checks unchanged state of keys where the communication data stored in the shared memory 23A is written in the storage 28)
Regarding claim 5, YONEMURA teaches The control device (1) as claimed in any of claims 1 to 4, wherein the control device (1) is furthermore configured to provide, in the open operating mode (S1) and/or the protected operating mode (S2), at least one fourth service (10d) for providing at least one application function, wherein accesses to the fourth service (10d) are not safeguarded by means of a key stored in the predetermined memory area (9e), either in the open operating mode (S1) or in the protected operating mode (S2). (See Fig 3, paragraph [0069] and [0069], illustrates memory access control unit 22 access operation as fourth service for reading as not safe guarded in both secure locked state or non-secure unlocked state)
Regarding claim 8, YONEMURA teaches A method for initializing a control device (1) comprising at least one data processing unit (7), at least one nonvolatile memory (8) for storing program code for the data processing unit (7), and (See Fig 4, paragraph [0049], illustrates information processing device 10, the processor unit 20 reads a computer program from the ROM 62 and executes it, so that various or operations get implemented)
at least one interface (4, 5) for accessing services provided by the control device (1), in particular the control device (1) as claimed in any of claims 1 to 7, wherein the method comprises the following steps: (See Fig 3, paragraph [0232], illustrates memory access control unit 22 controls the accesses to the memory unit 23)
starting (S11) the control device (1) in an open operating mode (S1); (See Fig 3, 4 and 5, paragraph [0081], illustrates at SEQ204 the memory accessing unit 25A identifies from the non-secure page table 34 the target physical addresses for writing operations in non-secure or open operating mode)
writing (S12), by means of a first service (10a), at least one key to a predetermined memory area (9e) of the at least one nonvolatile memory (8) in the open operating mode (S1); (See Fig 3, 4 and 5, paragraph [0082] and [0086], illustrates at SEQ206 non-secure processing unit 25 issues a first-type switching instruction or key to the monitoring unit 27 for switching the mode to the secure mode S and at SEQ214 secure application 33 and the secure processing unit 26 perform writing protection function)
switching (S13) to a protected operating mode (S2) after writing the at least one key; and (See Fig 3, 4 and 5, paragraph [0087], illustrates at SEQ218 secure processing unit 26 does the write operation of the communication data to the storage area 28)
offering at least one second service (10b, 10c, 10e) for querying and/or changing data stored in the at least one data processing unit (7) and/or the at least one nonvolatile memory (8) in the protected operating mode (S2), wherein an access to the second service (10b, 10c, 10e) is safeguarded by the at least one key written in the predetermined memory area (9e). (See Fig 3, 4 and 5, paragraph [0087], illustrates at SEQ216 secure processing unit 26 uses a storage key and cancels the writing restriction with respect to such an area in the storage 28 which is indicated and queried by physical address for writing operations)
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
Claim(s) 3-4 and 7 are rejected under 35 U.S.C. 103 as being unpatentable over YONEMURA in view of Eckel et al. (US 20190245689 A1) hereinafter Eckel.
Regarding claim 3, YONEMURA teaches control device access control and security key for access in claim 1. However, YONEMURA does not explicitly teach The control device (1) as claimed in claim 1 or 2, wherein the control device (1) is furthermore configured to reject requests to the first service (10a) in the protected operating mode (S2) with an error message indicating the non-availability of the first service (10a)
On the other hand, Eckel which also relates to control device access control and security key for access teaches The control device (1) as claimed in claim 1 or 2, wherein the control device (1) is furthermore configured to reject requests to the first service (10a) in the protected operating mode (S2) with an error message indicating the non-availability of the first service (10a). (See Fig 4, paragraph [0049], illustrates EK input by the host is checked at 434 against EK encrypted and If the check indicates the EK supplied by the host for the current change key operation is not valid, an error can be logged such as “Key Not Valid”)
Both YONEMURA and Eckel relate to control device access control and security key for access (see YONEMURA, abstract, and see Eckel, abstract, regarding access control and security key for access).
Therefore, it would have been obvious to one of ordinary skill at the time the
invention was effectively filed to combine YONEMURA with Eckel by incorporating
control device access control and security key for access, as taught by
Eckel; to enable EK input by the host to be checked at 434 against EK encrypted and If the check indicates the EK supplied by the host for the current change key operation is not valid, an error can be logged such as “Key Not Valid”. The combined system of YONEMURA – Eckel allows enhancements to processing encryption keys and passing keys with respect to a memory sub-system can provide a mechanism to avoid issues associated with hackers attempting to access encryption keys via commands from a host or intended actions by a host that may adversely affect stored secure data as mentioned in paragraph [0019]. Therefore, the combination of YONEMURA - Eckel improves performance. See Eckel, paragraph [0087].
Regarding claim 4, YONEMURA teaches control device access control and security key for access in claim 1. However, YONEMURA does not explicitly teach The control device (1) as claimed in any of claims 1 to 3, wherein the control device (1) is furthermore configured to additionally provide the at least one second service (10b, 10c,10e) in the open operating mode (S1), wherein accesses to the second service in the open operating mode (S1) are not safeguarded by means of a key stored in the predetermined memory area (9e)
On the other hand, Eckel which also relates to control device access control and security key for access teaches The control device (1) as claimed in any of claims 1 to 3, wherein the control device (1) is furthermore configured to additionally provide the at least one second service (10b, 10c,10e) in the open operating mode (S1), wherein accesses to the second service in the open operating mode (S1) are not safeguarded by means of a key stored in the predetermined memory area (9e). (See Fig 4, paragraph [0048], illustrates a timer and a number of checks can be implemented such that if the check of the received access key does not match the unwrapped key from the NOR flash memory within a specific time or specific number of checks, the machine or application attempting to access data would be locked out. In other words, there is timer before a locked-out period begins when access are not safeguarded)
Both YONEMURA and Eckel relate to control device access control and security key for access (see YONEMURA, abstract, and see Eckel, abstract, regarding access control and security key for access).
Therefore, it would have been obvious to one of ordinary skill at the time the
invention was effectively filed to combine YONEMURA with Eckel by incorporating
control device access control and security key for access, as taught by
Eckel; to enable a timer and a number of checks to be implemented such that if the check of the received access key does not match the unwrapped key from the NOR flash memory within a specific time or specific number of checks, the machine or application attempting to access data would be locked out. The combined system of YONEMURA – Eckel allows enhancements to processing encryption keys and passing keys with respect to a memory sub-system can provide a mechanism to avoid issues associated with hackers attempting to access encryption keys via commands from a host or intended actions by a host that may adversely affect stored secure data as mentioned in paragraph [0019]. Therefore, the combination of YONEMURA - Eckel improves performance. See Eckel, paragraph [0087].
Regarding claim 7, YONEMURA teaches control device access control and security key for access in claim 1. However, YONEMURA does not explicitly teach The control device (1) as claimed in any of claims 1 to 6, wherein the at least one nonvolatile memory (8) is configured as a flash memory, in particular as an integrated flash memory of a microcontroller (2), wherein the flash memory has a plurality of only jointly erasable memory pages,
and each of the memory pages has a plurality of memory blocks which are one-time writable after an erase operation, and each key is stored by means of a dedicated write operation in at least one memory block of a common memory page which forms the predetermined memory area (9e)
On the other hand, Eckel which also relates to control device access control and security key for access teaches The control device (1) as claimed in any of claims 1 to 6, wherein the at least one nonvolatile memory (8) is configured as a flash memory, in particular as an integrated flash memory of a microcontroller (2), wherein the flash memory has a plurality of only jointly erasable memory pages, (See Fig 1, paragraph [0023], illustrates NOR flash memory or nonvolatile memory with erasable pages and memory system controller 115 performs erase operations)
and each of the memory pages has a plurality of memory blocks which are one-time writable after an erase operation, and each key is stored by means of a dedicated write operation in at least one memory block of a common memory page which forms the predetermined memory area (9e). (See Fig 4, paragraph [0049], illustrates at step 434 changing access keys includes erase operations which has been encrypted, wrapped, and stored in NOR flash memory)
Both YONEMURA and Eckel relate to control device access control and security key for access (see YONEMURA, abstract, and see Eckel, abstract, regarding access control and security key for access).
Therefore, it would have been obvious to one of ordinary skill at the time the
invention was effectively filed to combine YONEMURA with Eckel by incorporating
control device access control and security key for access, as taught by
Eckel; to enable NOR flash memory or nonvolatile memory with erasable pages and memory system controller 115 to perform erase operations and at step 434 changing access keys to include erase operations which has been encrypted, wrapped, and stored in NOR flash memory. The combined system of YONEMURA – Eckel allows enhancements to processing encryption keys and passing keys with respect to a memory sub-system can provide a mechanism to avoid issues associated with hackers attempting to access encryption keys via commands from a host or intended actions by a host that may adversely affect stored secure data as mentioned in paragraph [0019]. Therefore, the combination of YONEMURA - Eckel improves performance. See Eckel, paragraph [0087].
Claim(s) 6 and 9 are rejected under 35 U.S.C. 103 as being unpatentable over YONEMURA in view of SCHILDER et al. (US 20180189493 A1) hereinafter SCHILDER.
Regarding claim 6, YONEMURA teaches control device access control and security key for access in claim 1. However, YONEMURA does not explicitly teach The control device (1) as claimed in any of claims 1 to 5, wherein the at least one second service (10b, 10c, 10e) comprises at least one of the following services:
a service (10e) for debugging via at least one internal interface (5), in particular a debug interface reachable by means of needle contacts (6), wherein accesses to the service (10e) for debugging in the protected operating mode (S2) are safeguarded by means of at least one key stored at a predetermined address of the at least one nonvolatile memory (8);
a service (10c) for accesses to measurement and calibration data via a bus interface (4), in particular for accesses according to the Universal Measurement and Calibration Protocol, XCP, via a vehicle bus interface (4), wherein the service (10c) for accesses to measurement and calibration data does not allow read accesses to the predetermined memory area (9e); and/or
a service (10b) for writing the program code for the data processing unit (7) via a bus interface, in particular a bootloader or initialization code for writing firmware via a vehicle bus interface (4) to the at least one nonvolatile memory (8), wherein the service (10b) for writing does not allow write accesses to the predetermined memory area (9e)
On the other hand, SCHILDER which also relates to control device access control and security key for access teaches The control device (1) as claimed in any of claims 1 to 5, wherein the at least one second service (10b, 10c, 10e) comprises at least one of the following services:
a service (10e) for debugging via at least one internal interface (5), in particular a debug interface reachable by means of needle contacts (6), wherein accesses to the service (10e) for debugging in the protected operating mode (S2) are safeguarded by means of at least one key stored at a predetermined address of the at least one nonvolatile memory (8); (See Fig 4, paragraph [0073], illustrates when Raw Device 401 is mainly locked, a command maybe sent over debug port to cause a test-mode-enabled bit pattern or key to be written to fuse for test or debug enabled mode 403)
a service (10c) for accesses to measurement and calibration data via a bus interface (4), in particular for accesses according to the Universal Measurement and Calibration Protocol, XCP, via a vehicle bus interface (4), wherein the service (10c) for accesses to measurement and calibration data does not allow read accesses to the predetermined memory area (9e); and/or (See Fig 1, paragraph [0058], illustrates key fuses 125 may store secret data that is a key, or used to derive a key like an Initialization Key (DIK), which may act as the root shared secret between the device 100 and a key management server 307 via debug port which provides path to fuses for management and initialization)
a service (10b) for writing the program code for the data processing unit (7) via a bus interface, in particular a bootloader or initialization code for writing firmware via a vehicle bus interface (4) to the at least one nonvolatile memory (8), wherein the service (10b) for writing does not allow write accesses to the predetermined memory area (9e). (See Fig 1, 4 and 5, paragraph [0100], illustrates software boot code that may be executed out of flash or nonvolatile memory after the boot ROM code executes in Boot Loader 164)
Both YONEMURA and SCHILDER relate to control device access control and security key for access (see YONEMURA, abstract, and see SCHILDER, abstract, regarding access control and security key for access).
Therefore, it would have been obvious to one of ordinary skill at the time the
invention was effectively filed to combine YONEMURA with SCHILDER by incorporating
control device access control and security key for access, as taught by
SCHILDER; to enable a command to be sent when Raw Device 401 is mainly locked over debug port to cause a test-mode-enabled bit pattern or key to be written to fuse for test or debug enabled mode 403 and key fuses 125 may store secret data that is a key, or used to derive a key like an Initialization Key (DIK), which may act as the root shared secret between the device 100 and a key management server 307 via debug port which to provide path to fuses for management and initialization and software boot code that may be executed out of flash or nonvolatile memory after the boot ROM code executes in Boot Loader 164. The combined system of YONEMURA – SCHILDER allows fuses to be used to change the configuration of semiconductor chips after they are manufactured as well as to tune performance and fuses may also be used for chip ID storage and cryptographic key storage as mentioned in paragraph [0003]. Therefore, the combination of YONEMURA - SCHILDER improves performance tuning. See SCHILDER, paragraph [0003].
Regarding claim 9, YONEMURA teaches control device access control and security key for access in claim 8. However, YONEMURA does not explicitly teach The method as claimed in claim 8, wherein at least the steps of starting (S11), writing (S12) and switching (S13) are carried out in a concluding phase of a process for producing the control device (1), after the assembly thereof and before the delivery thereof, in particular in the context of a functional test of the control device (1)
On the other hand, SCHILDER which also relates to control device access control and security key for access teaches The method as claimed in claim 8, wherein at least the steps of starting (S11), writing (S12) and switching (S13) are carried out in a concluding phase of a process for producing the control device (1), after the assembly thereof and before the delivery thereof, in particular in the context of a functional test of the control device (1). (See Fig 7 and 8A, paragraph [0132]- [0135], illustrates when wafer level devices which including processors, controllers are assembled into packages, package devices are powered up for manufacturing tests which includes configuring fuses, booting, writing keys etc)
Both YONEMURA and SCHILDER relate to control device access control and security key for access (see YONEMURA, abstract, and see SCHILDER, abstract, regarding access control and security key for access).
Therefore, it would have been obvious to one of ordinary skill at the time the
invention was effectively filed to combine YONEMURA with SCHILDER by incorporating
control device access control and security key for access, as taught by
SCHILDER; to illustrate when wafer level devices which including processors, controllers are assembled into packages, package devices are powered up for manufacturing tests which includes configuring fuses, booting, writing keys etc. The combined system of YONEMURA – SCHILDER allows fuses to be used to change the configuration of semiconductor chips after they are manufactured as well as to tune performance and fuses may also be used for chip ID storage and cryptographic key storage as mentioned in paragraph [0003]. Therefore, the combination of YONEMURA - SCHILDER improves performance tuning. See SCHILDER, paragraph [0003].
Claim(s) 10 is rejected under 35 U.S.C. 103 as being unpatentable over YONEMURA in view of Patange et al. (US 20190080111 A1) and further in view of SCHILDER hereinafter Patange.
Regarding claim 10, YONEMURA teaches control device access control and security key for access in claim 8. However, YONEMURA does not explicitly teach The method as claimed in claim 8 or 9, wherein the step of switching (S13) to the protected operating mode (S2) comprises the following:
calculating at least one checksum for keys stored in the predetermined memory area (9e);
storing the at least one checksum in the predetermined memory area (9e);
On the other hand, Patange which also relates to control device access control and security key for access teaches The method as claimed in claim 8 or 9, wherein the step of switching (S13) to the protected operating mode (S2) comprises the following:
calculating at least one checksum for keys stored in the predetermined memory area (9e); (See Fig 1, paragraph [0025], illustrates first and also the second check mechanism may apply a deterministic calculation to derive the corresponding check data which may involve as applying a hash function or forming a checksum)
storing the at least one checksum in the predetermined memory area (9e); (See Fig 1, paragraph [0025], illustrates the computing system comprises a memory area 3 where data such as payload data and checksum data may be stored)
Both YONEMURA and Patange relate to control device access control and security key for access (see YONEMURA, abstract, and see Patange, abstract, regarding access control and security key for access).
Therefore, it would have been obvious to one of ordinary skill at the time the
invention was effectively filed to combine YONEMURA with Patange by incorporating
control device access control and security key for access, as taught by
Patange; to illustrate first and also the second check mechanism may apply a deterministic calculation to derive the corresponding check data which may involve as applying a hash function or forming a checksum and the computing system comprises a memory area 3 where data such as payload data and checksum data may be stored. The combined system of YONEMURA – Patange allows method for protecting unauthorized data access from a memory of a computing system and there may be a need for a computing system being configured for protecting unauthorized data access from a memory of the computing system as mentioned in paragraph [0008]. Therefore, the combination of YONEMURA - Patange improves protecting the data/assets in the non-volatile memory. See Patange, paragraph [0049].
YONEMURA in view of Patange teaches control device access control and security key for access above. However, YONEMURA - Patange combination does not explicitly teach optionally, storing a validation pattern in the predetermined memory area (9e);
generating a confirmation signal, after writing the at least one checksum and, optionally, the validation pattern; and
restarting the control device (1), wherein during the restart the data processing unit (7) recognizes the data stored in the predetermined memory area (9e) and puts the control device (1) into the protected operating mode (S2)
On the other hand, SCHILDER which also relates to control device access control and security key for access teaches optionally, storing a validation pattern in the predetermined memory area (9e); (See Fig 1, paragraph [0101], illustrates a validation pattern maybe stored in boot loader 163)
generating a confirmation signal, after writing the at least one checksum and, optionally, the validation pattern; and (See Fig 2, paragraph [0063], illustrates hardware decoder reads the 27 bits device validation pattern and send signal of the state)
restarting the control device (1), wherein during the restart the data processing unit (7) recognizes the data stored in the predetermined memory area (9e) and puts the control device (1) into the protected operating mode (S2) (See Fig 4, paragraph [0083], illustrates a device may be re-provisioned at any time by erasing the firmware and restarting a provisioning process at step 413 where Provisioned Device 413 is defined by firmware 104, keys, and certificates stored within the Device's on-chip flash memory)
Both YONEMURA. Patange and SCHILDER relate to control device access control and security key for access (see YONEMURA, abstract, and see Patange, abstract, and see SCHILDER, abstract, regarding access control and security key for access).
Therefore, it would have been obvious to one of ordinary skill at the time the
invention was effectively filed to combine YONEMURA - Patange combination with SCHILDER by incorporating control device access control and security key for access, as taught by SCHILDER; to enable a validation pattern to be stored in boot loader 163 and hardware decoder to read the 27 bits device validation pattern and send signal of the state and a device may be re-provisioned at any time by erasing the firmware and restarting a provisioning process at step 413 where Provisioned Device 413 is defined by firmware 104, keys, and certificates stored within the Device's on-chip flash memory. The combined system of YONEMURA - Patange – SCHILDER allows fuses to be used to change the configuration of semiconductor chips after they are manufactured as well as to tune performance and fuses may also be used for chip ID storage and cryptographic key storage as mentioned in paragraph [0003]. Therefore, the combination of YONEMURA - Patange - SCHILDER improves performance tuning. See SCHILDER, paragraph [0003].
Response to Arguments
Applicant’s arguments filed on 06/22/2026 have been fully considered but they
are not persuasive.
Applicant’s first argument is claims 1 and 8 mapping by primary reference YONEMURA in page 8 of the response: "There is no teaching, however, that the memory access control unit 22 is an interface for accessing services of the control device. That is, while it may control access within the control device to the memory unit 23, it is not taught in Yonemura that the memory access control unit 22 controls access to a second service from outside the control device. For at least these reasons, Independent Claim 1 is not anticipated by Yonemura. Independent Claim 8 recites analogous limitations and are allowable for analogous reasons. The remaining claims depend from these allowable Independent Claims and are likewise allowable. Applicant, therefore, respectfully requests favorable action on all claims as presented herein”
In summary, applicant argued is commensurate to Applicant’s argument that primary reference YONEMURA does not teach having control device controlling access to memory unit and access to other service of control device. Examiner respectfully disagrees. For further clarification examiner cites portion from YONEMURA. Also, for applicant’s understanding examiner would like to explain the teachings of YONEMURA and examiner’s interpretation in more detail here. See Fig 1- 3, paragraph [0030]-[0035], YONEMURA teaches information processing device 10 in fig 1 has processor unit 20 includes a memory management unit (MMU) 61, which controls the memory accesses requested by the CPU and also processing device 10 in fig 1 contains non securing processing unit 25 and secure processing unit 26 for other service of control device. The cited portions along with fig 1-3 clearly teaches having processing unit of control devices to control memory access and performing other services. Thus, the rejection of claims 1 and 8 are maintained.
Conclusion
THIS ACTION IS MADE FINAL. Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
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/S.K.C./Examiner, Art Unit 2132
/JARED I RUTZ/Supervisory Patent Examiner, Art Unit 2135
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