CTNF 19/105,957 CTNF 100277 DETAILED ACTION Claims 1-22 are presented for examination. This office action is in response to submission of application on 24-FEB-2025 . Notice of Pre-AIA or AIA Status 07-03-aia AIA 15-10-aia The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA. Information Disclosure Statement The information disclosure statements (IDS) submitted on 24-FEB-2025, 18-MARCH-2025, and 23-JAN-2026 are in compliance with the provisions of 37 CFR 1.97. Accordingly, the information disclosure statements are being considered by the examiner. Specification 07-29 AIA The disclosure is objected to because of the following informalities: Page 3, line 22, “Partitions 112a-n” should read “Partitions 122a-n” . Appropriate correction is required. Double Patenting 08-33 AIA The nonstatutory double patenting rejection is based on a judicially created doctrine grounded in public policy (a policy reflected in the statute) so as to prevent the unjustified or improper timewise extension of the “right to exclude” granted by a patent and to prevent possible harassment by multiple assignees. A nonstatutory double patenting rejection is appropriate where the conflicting claims are not identical, but at least one examined application claim is not patentably distinct from the reference claim(s) because the examined application claim is either anticipated by, or would have been obvious over, the reference claim(s). See, e.g., In re Berg , 140 F.3d 1428, 46 USPQ2d 1226 (Fed. Cir. 1998); In re Goodman , 11 F.3d 1046, 29 USPQ2d 2010 (Fed. Cir. 1993); In re Longi , 759 F.2d 887, 225 USPQ 645 (Fed. Cir. 1985); In re Van Ornum , 686 F.2d 937, 214 USPQ 761 (CCPA 1982); In re Vogel , 422 F.2d 438, 164 USPQ 619 (CCPA 1970); In re Thorington , 418 F.2d 528, 163 USPQ 644 (CCPA 1969). A timely filed terminal disclaimer in compliance with 37 CFR 1.321(c) or 1.321(d) may be used to overcome an actual or provisional rejection based on nonstatutory double patenting provided the reference application or patent either is shown to be commonly owned with the examined application, or claims an invention made as a result of activities undertaken within the scope of a joint research agreement. See MPEP § 717.02 for applications subject to examination under the first inventor to file provisions of the AIA as explained in MPEP § 2159. See MPEP § 2146 et seq. for applications not subject to examination under the first inventor to file provisions of the AIA. A terminal disclaimer must be signed in compliance with 37 CFR 1.321(b). The filing of a terminal disclaimer by itself is not a complete reply to a nonstatutory double patenting (NSDP) rejection. A complete reply requires that the terminal disclaimer be accompanied by a reply requesting reconsideration of the prior Office action. Even where the NSDP rejection is provisional the reply must be complete. See MPEP § 804, subsection I.B.1. For a reply to a non-final Office action, see 37 CFR 1.111(a). For a reply to final Office action, see 37 CFR 1.113(c). A request for reconsideration while not provided for in 37 CFR 1.113(c) may be filed after final for consideration. See MPEP §§ 706.07(e) and 714.13. The USPTO Internet website contains terminal disclaimer forms which may be used. Please visit www.uspto.gov/patent/patents-forms. The actual filing date of the application in which the form is filed determines what form (e.g., PTO/SB/25, PTO/SB/26, PTO/AIA/25, or PTO/AIA/26) should be used. A web-based eTerminal Disclaimer may be filled out completely online using web-screens. An eTerminal Disclaimer that meets all requirements is auto-processed and approved immediately upon submission. For more information about eTerminal Disclaimers, refer to www.uspto.gov/patents/apply/applying-online/eterminal-disclaimer. 08-36 AIA Claim s 1, 12 are rejected on the ground of nonstatutory double patenting as being unpatentable over claim s 1 and 15 (respectively) of U.S. Patent No. 11188472 in view of Iyer, U.S. Pub. No. 20050114605 (hereinafter “Iyer”). Although the claims at issue are not identical, they are not patentably distinct from each other for the reasons below. Minor terminology differences are denoted by italics, and limitations which will be addressed in further detail are bolded . Regarding claim 1: Instant Application US 11188472 A system comprising: A plurality of integrated client devices, each client device configured to generate memory requests Each memory request having a respective pre-assigned stream id that represents a type of computing task to which the memory request belongs; and A cache configured to cache memory requests to a memory for each of the plurality of integrated client devices, Wherein the cache has multiple partitions, and wherein the cache is configured to allocate different partitions to respective memory requests according to stream ids of the memory requests A system comprising: One or more integrated client devices, each client device being configured to generate memory requests A cache configured to cache memory requests to the first memory for each of the one or more integrated client devices. Wherein the cache is configured to… allocate different portions of the cache memory to different respective memory requests. As shown above in the mapping, claim 1 of the reference application includes all limitations of claim 1 of the instant application, except for the limitations regarding the memory requests having stream ids. The reference application does not appear to claim Each memory request having a respective pre-assigned stream id that represents a type of computing task to which the memory request belongs; , or allocating partitions according to stream ids of the memory requests However, Iyer teaches Each memory request having a respective pre-assigned stream id that represents a type of computing task to which the memory request belongs; , allocating partitions according to stream ids of the memory requests (Fig. 6, [0028], [0031], and [0013-0014], Iyer teaches a system with multiple devices which are able to interact with a cache and are able to make allocation requests to the cache. Further, in [0017] and [0015], Iyer teaches that a stream identifier may be used for mapping the stream types, and the stream types may be according to streams associated with various types of applications. The devices are interpreted as the claimed integrated client devices, and each one is configured to generate cache allocation requests. The streams with their identifiers, all being associated with a type of application, is interpreted to be the memory requests having respective pre-assigned stream ids that represent a type of computing task) the cache is configured to allocate different partitions to respective memory requests according to stream ids of the memory requests ([0019-0021], Iyer teaches that the cache may partition its space out, and apportion out cache lines according to cache allocation requests, and then store cache lines occupied by data blocks of the priority levels, and by extension, the streams and clients corresponding to them.). Therefore it would have been obvious for one of ordinary skill in the art before the effective filing date of the claimed invention to have combined claim 1 of the reference application and teachings of Iyer to achieve the claimed memory partitioning system to client devices, to also include pre-assigned stream ids that represent a computing task to which the memory requests belongs, and to allocate partitions to respective memory requests according to the stream ids. One of ordinary skill in the art would have been motivated to make this modification in order to avoid the sub-optimal allocation of cache resources associated with sharing cache space with equal priority when there are more important memory intensive applications present, as discussed in Iyer [0004]. Regarding claim 12: Instant Application US 11188472 A method performed by a device comprising: A plurality of integrated client devices, each client device configured to generate memory requests Each memory request having a respective pre-assigned stream id that represents a type of computing task to which the memory request belongs; and A cache having multiple partitions Caching, by the cache, memory requests to a memory for each of the plurality of integrated client devices Allocating, by the cache, different partitions to respective memory requests according to stream ids of the memory requests A computer-implemented method executed by a computing system, the method comprising: Receiving, by the system, One or more memory requests generated by respective ones of the one or more client devices Caching, by a cache of the system, the memory requests to the first memory in a cache memory by… allocating different portions of the cache memory to different respective memory requests As shown above in the mapping, claim 15 of the reference application includes all limitations of claim 12 of the instant application, except for the limitations regarding the memory requests having stream ids. The reference application does not appear to claim Each memory request having a respective pre-assigned stream id that represents a type of computing task to which the memory request belongs; , or allocating partitions according to stream ids of the memory requests However, Iyer teaches Each memory request having a respective pre-assigned stream id that represents a type of computing task to which the memory request belongs; , allocating partitions according to stream ids of the memory requests (Fig. 6, [0028], [0031], and [0013-0014], Iyer teaches a system with multiple devices which are able to interact with a cache and are able to make allocation requests to the cache. Further, in [0017] and [0015], Iyer teaches that a stream identifier may be used for mapping the stream types, and the stream types may be according to streams associated with various types of applications. The devices are interpreted as the claimed integrated client devices, and each one is configured to generate cache allocation requests. The streams with their identifiers, all being associated with a type of application, is interpreted to be the memory requests having respective pre-assigned stream ids that represent a type of computing task) the cache is configured to allocate different partitions to respective memory requests according to stream ids of the memory requests ([0019-0021], Iyer teaches that the cache may partition its space out, and apportion out cache lines according to cache allocation requests, and then store cache lines occupied by data blocks of the priority levels, and by extension, the streams and clients corresponding to them.). Therefore it would have been obvious for one of ordinary skill in the art before the effective filing date of the claimed invention to have combined claim 15 of the reference application and teachings of Iyer to achieve the claimed memory partitioning system to client devices, to also include pre-assigned stream ids that represent a computing task to which the memory requests belongs, and to allocate partitions to respective memory requests according to the stream ids. One of ordinary skill in the art would have been motivated to make this modification in order to avoid the sub-optimal allocation of cache resources associated with sharing cache space with equal priority when there are more important memory intensive applications present, as discussed in Iyer [0004] . Claim Rejections - 35 USC § 102 07-07-aia AIA 07-07 The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action: A person shall be entitled to a patent unless – 07-08-aia AIA (a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention. 07-12-aia AIA (a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention. 07-15 AIA Claim s 1-5, 12-16 are rejected under 35 U.S.C. 102( a)(1)/(a)(2 ) as being anticipated by Iyer, U.S. Pub. No. 20050114605 (hereinafter “Iyer”). Regarding claim 1: Iyer teaches A system comprising: A plurality of integrated client devices, each client device configured to generate memory requests, each memory request having a respective pre-assigned stream id that represents a type of computing task to which the memory request belongs; and (Fig. 6, [0028], [0031], and [0013-0014], Iyer teaches a system with multiple devices which are able to interact with a cache and are able to make allocation requests to the cache. Further, in [0017] and [0015], Iyer teaches that a stream identifier may be used for mapping the stream types, and the stream types may be according to streams associated with various types of applications. The devices are interpreted as the claimed integrated client devices, and each one is configured to generate cache allocation requests, interpreted to be the claimed generating memory requests. The streams with their identifiers, all being associated with a type of application, is interpreted to be the memory requests having respective pre-assigned stream ids that represent a type of computing task). a cache configured to cache memory requests to a memory for each of the plurality of integrated client devices, wherein the cache has multiple partitions, and wherein the cache is configured to allocate different partitions to respective memory requests according to stream ids of the memory requests ([0019-0021], Iyer teaches that the cache may partition its space out, and apportion out cache lines according to cache allocation requests, and then store cache lines occupied by data blocks of the priority levels, and by extension, the streams and clients corresponding to them.). Regarding claim 2: Iyer teaches all limitations of claim 1, from which claim 2 depends. Iyer further teaches memory requests belonging to different types of computing tasks have different stream ids. ([0015] and [0017], Iyer teaches that the priority levels may be assigned according to the type of incoming application streams, and that the priority level is determined for each cache allocation request, which is interpreted as the memory requests belonging to different types of computing tasks having different stream ids.) Regarding claim 3: Iyer teaches all limitations of claim 1, from which claim 3 depends. Iyer further teaches the cache is configured to allocate no partitions to a particular stream id ([0023], Iyer teaches that a cache controller is configured to, based on a condition, deny an allocation request. The denying of an allocation request is interpreted to be a case where the cache is configured to allocate no partitions to a particular stream id.) Regarding claim 4: Iyer teaches all limitations of claim 1, from which claim 4 depends. Iyer further teaches the cache is configured to swap a stream id from using a first partition to using a second partition ([0021], Iyer teaches that the cache controller may re-apportion cache lines according to new needs, including when new ones are needed via new allocations, or when cache lines are evicted and removed. This dynamic changing of the partition sizes/contents is interpreted to be the claimed swapping a stream id from using a first partition to using a second partition.) Regarding claim 5: Iyer teaches all limitations of claim 1, from which claim 5 depends. Iyer further teaches the cache is configured to allocate multiple different stream ids to use a same partition ([0015] and [0017], Iyer teaches that a priority level, to which the cache is partitioned to, can include streams (plural) associated with a certain type of application. The plurality of the streams associated to a priority level, and by extension a partition, is interpreted to be the claimed allocating multiple stream IDs to use a same partition.) Regarding claim 1: Iyer teaches A method performed by a device comprising: A plurality of integrated client devices, each client device configured to generate memory requests, each memory request having a respective pre-assigned stream id that represents a type of computing task to which the memory request belongs, and a cache having multiple partitions (Fig. 6, [0028], [0031], and [0013-0014], Iyer teaches a system with multiple devices which are able to interact with a cache and are able to make allocation requests to the cache. Further, in [0017] and [0015], Iyer teaches that a stream identifier may be used for mapping the stream types, and the stream types may be according to streams associated with various types of applications. The devices are interpreted as the claimed integrated client devices, and each one is configured to generate cache allocation requests, interpreted to be the claimed generating memory requests. The streams with their identifiers, all being associated with a type of application, is interpreted to be the memory requests having respective pre-assigned stream ids that represent a type of computing task. Furthermore, in [0019], Iyer teaches that the cache may partition its space.). Caching, by the cache, memory requests to a memory for each of the plurality of integrated client devices, and allocating, by the cache, different partitions to respective memory requests according to stream ids of the memory requests ([0019-0021], Iyer teaches that the cache may partition its space out, and apportion out cache lines according to cache allocation requests, and then store cache lines occupied by data blocks of the priority levels, and by extension, the streams and clients corresponding to them.). Regarding claim 13: Iyer teaches all limitations of claim 12, from which claim 13 depends. Iyer further teaches memory requests belonging to different types of computing tasks have different stream ids. ([0015] and [0017], Iyer teaches that the priority levels may be assigned according to the type of incoming application streams, and that the priority level is determined for each cache allocation request, which is interpreted as the memory requests belonging to different types of computing tasks having different stream ids.) Regarding claim 14: Iyer teaches all limitations of claim 12, from which claim 14 depends. Iyer further teaches the cache is configured to allocate no partitions to a particular stream id ([0023], Iyer teaches that a cache controller is configured to, based on a condition, deny an allocation request. The denying of an allocation request is interpreted to be a case where the cache is configured to allocate no partitions to a particular stream id.) Regarding claim 15: Iyer teaches all limitations of claim 12, from which claim 15 depends. Iyer further teaches swapping a stream id from using a first partition to using a second partition ([0021], Iyer teaches that the cache controller may re-apportion cache lines according to new needs, including when new ones are needed via new allocations, or when cache lines are evicted and removed. This dynamic changing of the partition sizes/contents is interpreted to be the claimed swapping a stream id from using a first partition to using a second partition.) Regarding claim 16: Iyer teaches all limitations of claim 12, from which claim 16 depends. Iyer further teaches the allocating multiple different stream ids to use a same partition ([0015] and [0017], Iyer teaches that a priority level, to which the cache is partitioned to, can include streams (plural) associated with a certain type of application. The plurality of the streams associated to a priority level, and by extension a partition, is interpreted to be the claimed allocating multiple stream IDs to use a same partition.) Claim Rejections - 35 USC § 103 07-20-aia AIA The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action: A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made. 07-21-aia AIA Claim s 6, 17 are rejected under 35 U.S.C. 103 as being unpatentable over Iyer, U.S. Pub. No. 20050114605 (hereinafter “Iyer”) in view of Suh et al., “Dynamic Cache Partitioning for Simultaneous Multithreading Systems,” 1 August 2001 (hereinafter “Suh”). Regarding claim 6: Iyer teaches all limitations of claim 1, from which claim 6 depends. Iyer further teaches a processing device configured to execute instructions to perform operations ([0022], Iyer teaches that the processes of the invention may be implemented using a processing system that executes machine accessible instructions.) Iyer further teaches providing, to the cache, instructions to allocate partitions to stream ids from a candidate pool of stream ids; ([0015-0021], Iyer teaches a system of a controller controlling a cache to allocate partitions to stream ids from a known set of application streams, interpreted to be the stream ids from a candidate pool of stream ids.) Iyer further teaches providing, to the cache, instructions to alter partition allocations for one or more stream ids ([0014] and [0017], Iyer teaches a mechanism by which, according to hit rates of a thread, the priority levels (which dictate the partition allocations) of the thread may be changed by the controller). While Iyer does teach the usage of counters for tracking hit ratios for threads, Iyer does not appear to explicitly disclose computing per-partition cache hit metrics for each partition However, Suh teaches computing per-partition cache miss metrics for each partition (Pages 3-5, under subheaders 3.1-3.3, Suh teaches both that the cache partitioning is assigned per thread, and teaches a system of computing cache miss rates per thread to determine how a partition should be adjusted. Examiner notes that one of ordinary skill in the art would recognize that a cache miss rate would be easily interchangeable with a cache hit rate in a system, as both rates are inversely proportional to one another and calculated from opposite outcomes of the same binary determination). Iyer and Suh are analogous art because they are from the same field of endeavor, Cache management. Therefore, it would have been obvious for one of ordinary skill in the art before the effective filing date of the claimed invention to have combined the teachings of Iyer and Suh to achieve the combined result of the processing device that executes instructions which instructs a cache to allocate partitions to stream ids from a candidate pool, computes per-partition cache hit metrics for each partition, and provides instructions to alter partition allocations for one or more stream ids. One of ordinary skill in the art would have been motivated to make this modification in order to optimize the partition sizes by identifying which partitions would benefit most from a bigger size as discussed in Suh Page 3, under header 3. Regarding claim 17: Iyer teaches all limitations of claim 12, from which claim 17 depends. Iyer further teaches providing, to the cache, instructions to allocate partitions to stream ids from a candidate pool of stream ids; ([0015-0021], Iyer teaches a system of a controller controlling a cache to allocate partitions to stream ids from a known set of application streams, interpreted to be the stream ids from a candidate pool of stream ids.) Iyer further teaches providing, to the cache, instructions to alter partition allocations for one or more stream ids ([0014] and [0017], Iyer teaches a mechanism by which, according to hit rates of a thread, the priority levels (which dictate the partition allocations) of the thread may be changed by the controller). While Iyer does teach the usage of counters for tracking hit ratios for threads, Iyer does not appear to explicitly disclose computing per-partition cache hit metrics for each partition However, Suh teaches computing per-partition cache miss metrics for each partition (Pages 3-5, under subheaders 3.1-3.3, Suh teaches both that the cache partitioning is assigned per thread, and teaches a system of computing cache miss rates per thread to determine how a partition should be adjusted. Examiner notes that one of ordinary skill in the art would recognize that a cache miss rate would be easily interchangeable with a cache hit rate in a system, as both rates are inversely proportional to one another and calculated from opposite outcomes of the same binary determination). Iyer and Suh are analogous art because they are from the same field of endeavor, Cache management. Therefore, it would have been obvious for one of ordinary skill in the art before the effective filing date of the claimed invention to have combined the teachings of Iyer and Suh to achieve the combined result of the processing device that executes instructions which instructs a cache to allocate partitions to stream ids from a candidate pool, computes per-partition cache hit metrics for each partition, and provides instructions to alter partition allocations for one or more stream ids. One of ordinary skill in the art would have been motivated to make this modification in order to optimize the partition sizes by identifying which partitions would benefit most from a bigger size as discussed in Suh Page 3, under header 3 . 07-21-aia AIA Claim s 7-8, 10-11, 18-19, 21-22 are rejected under 35 U.S.C. 103 as being unpatentable over Iyer, U.S. Pub. No. 20050114605 (hereinafter “Iyer”) in view of Suh et al., “Dynamic Cache Partitioning for Simultaneous Multithreading Systems,” 1 August 2001 (hereinafter “Suh”) further in view of Tong et al., U.S. Patent No. 10691613 (hereinafter “Tong”) further in view of Weiss et al., U.S. Pub. No. 20070079184 (hereinafter “Weiss”) Regarding claim 7: The combination of Iyer and Suh teaches all limitations of claim 6, from which claim 7 depends. Iyer/Suh further teaches computing the per-partition cache hit metrics comprises computing a hit ratio ([0014], Iyer teaches a system which determines a hit ratio using a counter, which, as discussed with respect to claim 6, Iyer/Suh teaches as being per-partition cache hit metrics.). Iyer/Suh does not appear to explicitly disclose determining that the hit ratio for a partition is less than an eviction threshold; and in response, deallocating one or more stream ids from the partition, and allocating a new stream id, from the candidate pool, to the partition. However, Tong teaches determining that the hit ratio for a partition is less than an eviction threshold; and in response, deallocating one or more stream ids from the partition (Col. 8 lines 10-21, Tong teaches a system in which a data entry in a cache is evicted from the cache when the cache hit count of the data entry is not above a cache hit count threshold associated with the layer (partition) of the cache.). Iyer/Suh and Tong are analogous art because they are from the same field of endeavor, Cache management. Therefore, it would have been obvious for one of ordinary skill in the art before the effective filing date of the claimed invention to have combined the teachings of Iyer/Suh and Tong to achieve the combined result of the system which computes per-partition cache hit metrics comprising a hit ratio, which also determines that the hit ratio for a partition is less than an eviction threshold, and in response, evicts (deallocates) the stream ids from the partition. One of ordinary skill in the art would have been motivated to make this modification in order to deal with a well-known issue where the cache becomes too full as discussed in Tong Col. 4 lines 5-7. While Iyer/Suh/Tong teach cache insertion and eviction broadly, and eviction in response to the cache becoming full, Iyer/Suh/Tong do not appear to teach in response… allocating a new stream id, from the candidate pool, to the partition. However, Weiss teaches allocating a new entry to the cache in response to a cache becoming full ([0033], Weiss teaches that when space must be made available for a new line to be brought in to the cache, a replacement logic may select a victim way to evict cache lines from a certain cache level and inserting a new cache line into it.) Iyer/Suh/Tong and Weiss are analogous art because they are from the same field of endeavor, Cache management. Therefore, it would have been obvious for one of ordinary skill in the art before the effective filing date of the claimed invention to have combined the teachings of Iyer/Suh/Tong/Weiss to achieve the combined result of the system which computes per-partition cache hit metrics comprising a hit ratio, which also determines that the hit ratio for a partition is less than an eviction threshold, and in response, evicts (deallocates) the stream ids from the partition, all as a means to perform a replacement where a new stream id is to take the place of the evicted one. One of ordinary skill in the art would have been motivated to make this modification in order to facilitate the well-known need to maintain relevant data in the cache, as discussed in Weiss [0033]. Regarding claim 8: The combination of Iyer, Suh, Tong, and Weiss teaches all limitations of claim 7, from which claim 8 depends. Iyer/Suh/Tong/Weiss further teaches determining that the hit ratio for the partition is less than a revival threshold; and in response, removing the deallocated one or more stream ids from the candidate pool (Col. 5, lines 16-45, Tong teaches a process by which an entry is considered for insertion into a cache, and if the cache hit count of the entry is not greater than a threshold associated with the layer (partition), then the entry is not inserted into the cache hierarchy at all and remains in slow persistent storage instead. The not considering the entry as being insertable into the cache, in combination with the previously discussed elements of the system of Iyer/Suh/Tong/Weiss, renders obvious the claimed determining the hit ratio for the partition is less than a revival threshold and in response, removing the deallocated one or more ids from the candidate pool.) One of ordinary skill in the art would have been motivated to make this modification in order to enforce the hierarchy of a hierarchical cache, and benefits from performance improvements of such a hierarchy, as discussed in Tong Col. 7 lines 37-44. Regarding claim 10: The combination of Iyer, Suh, Tong, and Weiss teaches all limitations of claim 7, from which claim 10 depends. Iyer/Suh/Tong/Weiss further teaches the eviction threshold for at least some of the partitions is different (Col. 8 lines 10-18, Tong teaches that each layer of a cache (corresponding to the partitions of Iyer) has its own eviction threshold.) One of ordinary skill in the art would have been motivated to make this modification in order to enforce the hierarchy of a hierarchical cache, and benefits from performance improvements of such a hierarchy, as discussed in Tong Col. 7 lines 37-44. Regarding claim 11: The combination of Iyer, Suh, Tong, and Weiss teaches all limitations of claim 8, from which claim 11 depends. Iyer/Suh/Tong/Weiss further teaches the revival threshold for at least some of the partitions is different (Col. 5 lines 23-40, Tong teaches that each layer of a cache (corresponding to the partitions of Iyer) has its own threshold for allowing insertion, interpreted as the revival threshold.) One of ordinary skill in the art would have been motivated to make this modification for the same reasons as in claim 8. Regarding claim 18: The combination of Iyer and Suh teaches all limitations of claim 17, from which claim 18 depends. Iyer/Suh further teaches computing the per-partition cache hit metrics comprises computing a hit ratio ([0014], Iyer teaches a system which determines a hit ratio using a counter, which, as discussed with respect to claim 6, Iyer/Suh teaches as being per-partition cache hit metrics.). Iyer/Suh does not appear to explicitly disclose determining that the hit ratio for a partition is less than an eviction threshold; and in response, deallocating one or more stream ids from the partition, and allocating a new stream id, from the candidate pool, to the partition. However, Tong teaches determining that the hit ratio for a partition is less than an eviction threshold; and in response, deallocating one or more stream ids from the partition (Col. 8 lines 10-21, Tong teaches a system in which a data entry in a cache is evicted from the cache when the cache hit count of the data entry is not above a cache hit count threshold associated with the layer (partition) of the cache.). Iyer/Suh and Tong are analogous art because they are from the same field of endeavor, Cache management. Therefore, it would have been obvious for one of ordinary skill in the art before the effective filing date of the claimed invention to have combined the teachings of Iyer/Suh and Tong to achieve the combined result of the system which computes per-partition cache hit metrics comprising a hit ratio, which also determines that the hit ratio for a partition is less than an eviction threshold, and in response, evicts (deallocates) the stream ids from the partition. One of ordinary skill in the art would have been motivated to make this modification in order to deal with a well-known issue where the cache becomes too full as discussed in Tong Col. 4 lines 5-7. While Iyer/Suh/Tong teach cache insertion and eviction broadly, and eviction in response to the cache becoming full, Iyer/Suh/Tong do not appear to teach in response… allocating a new stream id, from the candidate pool, to the partition. However, Weiss teaches allocating a new entry to the cache in response to a cache becoming full ([0033], Weiss teaches that when space must be made available for a new line to be brought in to the cache, a replacement logic may select a victim way to evict cache lines from a certain cache level and inserting a new cache line into it.) Iyer/Suh/Tong and Weiss are analogous art because they are from the same field of endeavor, Cache management. Therefore, it would have been obvious for one of ordinary skill in the art before the effective filing date of the claimed invention to have combined the teachings of Iyer/Suh/Tong/Weiss to achieve the combined result of the system which computes per-partition cache hit metrics comprising a hit ratio, which also determines that the hit ratio for a partition is less than an eviction threshold, and in response, evicts (deallocates) the stream ids from the partition, all as a means to perform a replacement where a new stream id is to take the place of the evicted one. One of ordinary skill in the art would have been motivated to make this modification in order to facilitate the well-known need to maintain relevant data in the cache, as discussed in Weiss [0033]. Regarding claim 19: The combination of Iyer, Suh, Tong, and Weiss teaches all limitations of claim 18, from which claim 19 depends. Iyer/Suh/Tong/Weiss further teaches determining that the hit ratio for the partition is less than a revival threshold; and in response, removing the deallocated one or more stream ids from the candidate pool (Col. 5, lines 16-45, Tong teaches a process by which an entry is considered for insertion into a cache, and if the cache hit count of the entry is not greater than a threshold associated with the layer (partition), then the entry is not inserted into the cache hierarchy at all and remains in slow persistent storage instead. The not considering the entry as being insertable into the cache, in combination with the previously discussed elements of the system of Iyer/Suh/Tong/Weiss, renders obvious the claimed determining the hit ratio for the partition is less than a revival threshold and in response, removing the deallocated one or more ids from the candidate pool.) One of ordinary skill in the art would have been motivated to make this modification in order to enforce the hierarchy of a hierarchical cache, and benefits from performance improvements of such a hierarchy, as discussed in Tong Col. 7 lines 37-44. Regarding claim 21: The combination of Iyer, Suh, Tong, and Weiss teaches all limitations of claim 18, from which claim 21 depends. Iyer/Suh/Tong/Weiss further teaches the eviction threshold for at least some of the partitions is different (Col. 8 lines 10-18, Tong teaches that each layer of a cache (corresponding to the partitions of Iyer) has its own eviction threshold.) One of ordinary skill in the art would have been motivated to make this modification in order to enforce the hierarchy of a hierarchical cache, and benefits from performance improvements of such a hierarchy, as discussed in Tong Col. 7 lines 37-44. Regarding claim 22: The combination of Iyer, Suh, Tong, and Weiss teaches all limitations of claim 19, from which claim 22 depends. Iyer/Suh/Tong/Weiss further teaches the revival threshold for at least some of the partitions is different (Col. 5 lines 23-40, Tong teaches that each layer of a cache (corresponding to the partitions of Iyer) has its own threshold for allowing insertion, interpreted as the revival threshold.) One of ordinary skill in the art would have been motivated to make this modification for the same reasons as in claim 19 . 07-21-aia AIA Claim s 9, 20 are rejected under 35 U.S.C. 103 as being unpatentable over Iyer, U.S. Pub. No. 20050114605 (hereinafter “Iyer”) in view of Suh et al., “Dynamic Cache Partitioning for Simultaneous Multithreading Systems,” 1 August 2001 (hereinafter “Suh”) further in view of Ge, U.S. Pub. No. 20230185723 (hereinafter “Ge”). Regarding claim 9: The combination of Iyer and Suh teaches all limitations of claim 6, from which claim 9 depends. While Iyer/Suh teach the allocating, to partitions, new stream ids from a candidate pool, Iyer/Suh does not appear to explicitly disclose using a selection algorithm based on any one of: randomly, round-robin, first in first out, or priority. However, Ge teaches using a selection algorithm based on any one of: randomly, round-robin, first in first out, or priority ([0046] and [0054], Ge teaches a specific usage of queues that control the processing of access commands, and that they can be used to control the flow of commands specifically with what is to be stored in a buffer. Further, in [0064], Ge teaches that the memory system controller may execute received commands according to an order, such as a first-in first-out order, according to the order of the queues.). Iyer/Suh and Ge are analogous art because they are from the same field of endeavor, Cache management. Therefore, it would have been obvious for one of ordinary skill in the art before the effective filing date of the claimed invention to have combined the teachings of Iyer/Suh and Ge to achieve the combined result of the system which processes cache allocation requests, to incorporate a queue that uses a first-in first-out order to process the incoming cache allocation requests. One of ordinary skill in the art would have been motivated to make this modification in order to gain the benefits for command control in a system that must process more than one access command concurrently as discussed in Ge [0046]. Regarding claim 20: The combination of Iyer and Suh teaches all limitations of claim 17, from which claim 20 depends. While Iyer/Suh teach the allocating, to partitions, new stream ids from a candidate pool, Iyer/Suh does not appear to explicitly disclose using a selection algorithm based on any one of: randomly, round-robin, first in first out, or priority. However, Ge teaches using a selection algorithm based on any one of: randomly, round-robin, first in first out, or priority ([0046] and [0054], Ge teaches a specific usage of queues that control the processing of access commands, and that they can be used to control the flow of commands specifically with what is to be stored in a buffer. Further, in [0064], Ge teaches that the memory system controller may execute received commands according to an order, such as a first-in first-out order, according to the order of the queues.). Iyer/Suh and Ge are analogous art because they are from the same field of endeavor, Cache management. Therefore, it would have been obvious for one of ordinary skill in the art before the effective filing date of the claimed invention to have combined the teachings of Iyer/Suh and Ge to achieve the combined result of the system which processes cache allocation requests, to incorporate a queue that uses a first-in first-out order to process the incoming cache allocation requests. One of ordinary skill in the art would have been motivated to make this modification in order to gain the benefits for command control in a system that must process more than one access command concurrently as discussed in Ge [0046] . Conclusion 07-96 AIA The prior art made of record and not relied upon is considered pertinent to applicant's disclosure. Iyer et al., U.S. Pub. No. 20030177313, teaches a system which allocates subsets of a cache to stream ids, and can perform replacement algorithms to the entire subset. O’Connor et al., U.S. Pub. No. 20040205295, teaches a system which dynamically partitions a cache to cache data for active clients, while for clients that become inactive, their cache partitions are given to other active clients. DeMent et al., U.S. Pub. No. 20070288776, teaches a system which identifies which application is creating data access requests, and assigns cache sets if they do not yet exist, or use previously assigned ones if applicable. Vasquez Lopez et al., U.S. Pub. No. 20120323872, teaches a system which identifies cache entries whose hit counts do not exceed a threshold for eviction purposes. Flemming et al., U.S. Pub. No. 20130054897, teaches a system which evaluates historical hit rates for an application against predefined criteria to prevent the application from accessing the cache if the application does not meet the criteria. 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If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000. /K.H.P./Examiner, Art Unit 2133 /ROCIO DEL MAR PEREZ-VELEZ/Supervisory Patent Examiner, Art Unit 2133 Application/Control Number: 19/105,957 Page 2 Art Unit: 2133 Application/Control Number: 19/105,957 Page 3 Art Unit: 2133 Application/Control Number: 19/105,957 Page 4 Art Unit: 2133 Application/Control Number: 19/105,957 Page 5 Art Unit: 2133 Application/Control Number: 19/105,957 Page 6 Art Unit: 2133 Application/Control Number: 19/105,957 Page 7 Art Unit: 2133 Application/Control Number: 19/105,957 Page 8 Art Unit: 2133 Application/Control Number: 19/105,957 Page 9 Art Unit: 2133 Application/Control Number: 19/105,957 Page 10 Art Unit: 2133 Application/Control Number: 19/105,957 Page 11 Art Unit: 2133 Application/Control Number: 19/105,957 Page 12 Art Unit: 2133 Application/Control Number: 19/105,957 Page 13 Art Unit: 2133 Application/Control Number: 19/105,957 Page 14 Art Unit: 2133 Application/Control Number: 19/105,957 Page 15 Art Unit: 2133 Application/Control Number: 19/105,957 Page 16 Art Unit: 2133 Application/Control Number: 19/105,957 Page 17 Art Unit: 2133 Application/Control Number: 19/105,957 Page 18 Art Unit: 2133 Application/Control Number: 19/105,957 Page 19 Art Unit: 2133 Application/Control Number: 19/105,957 Page 20 Art Unit: 2133 Application/Control Number: 19/105,957 Page 21 Art Unit: 2133 Application/Control Number: 19/105,957 Page 22 Art Unit: 2133 Application/Control Number: 19/105,957 Page 23 Art Unit: 2133 Application/Control Number: 19/105,957 Page 24 Art Unit: 2133 Application/Control Number: 19/105,957 Page 25 Art Unit: 2133 Application/Control Number: 19/105,957 Page 26 Art Unit: 2133 Application/Control Number: 19/105,957 Page 27 Art Unit: 2133 Application/Control Number: 19/105,957 Page 28 Art Unit: 2133
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