CTNF 19/106,190 CTNF 82148 Notice of Pre-AIA or AIA Status 07-03-aia AIA 15-10-aia The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA. Claim Rejections - 35 USC § 101 07-04-01 AIA 07-04 35 U.S.C. 101 reads as follows: Whoever invents or discovers any new and useful process, machine, manufacture, or composition of matter, or any new and useful improvement thereof, may obtain a patent therefor, subject to the conditions and requirements of this title. Claims 12-17 are rejected under 35 U.S.C. 101 because the claimed invention is directed to non-statutory subject matter. The claims does/do not fall within at least one of the four categories of patent eligible subject matter because the broadest reasonable interpretation of the “computer-readable medium” is that the term encompasses signals per se. The BRI of computer-readable medium encompasses signals per se. A claim whose BRI covers both statutory and non-statutory embodiments embraces subject matter that is not eligible for patent protection and therefore is directed to non-statutory subject matter. See MPEP 2106.03(II). It is suggested that the applicant amend the claims to recites “non-transitory computer-readable medium” to overcome the rejection. Claim Rejections - 35 USC § 102 07-06 AIA 15-10-15 In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status. 07-07-aia AIA 07-07 The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action: A person shall be entitled to a patent unless – 07-08-aia AIA (a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention. 07-15-aia AIA Claim 1 is rejected under 35 U.S.C. 102 a as being anticipated by M. Tremblay, J. Chan, S. Chaudhry, A.R. Conigliaro, and S.S. Tse, “The MAJC Architecture: A Synthesis of Parallelism and Scalability,” IEEE Micro, vol. 20, no. 6 Nov./Dec. 2000, pp. 12–25. (hereinafter MAJC) . As per claim 1, MAJC teaches an apparatus comprising: a first plurality of registers to store information of at least a main sequence (page 15 (relying on pages from the article), “global registers.” Main sequence is equivalent to instruction slice or microthread execution stream using the global register portion); a second plurality of registers to store information of at least one concurrent interval (page 15, “private registers per instruction slice. A concurrent interval is equivalent to another instruction slice or another concurrently executed instruction path within the VLIW packet/microthread. It states that each instruction slice has its own private registers), the at least one concurrent interval independent of the main sequence (MAJC in pages 15-16 teach that each instruction slice is an independent execution path and that instructions execute within their own slices without requiring resources from another slice), wherein the second plurality of registers are accessible only by instructions of the at least one concurrent interval (page 15, private registers are accessible only by instructions in the same slice) and the first plurality of registers are accessible by instructions of the main sequence and the at least one concurrent interval (page 15, global registers are shared by all instruction slices to permit interslice communication. Thus, the global register set is accessible by both the main sequence slice and the concurrent interval slice); and an execution circuit coupled to the first plurality of registers and the second plurality of registers (pages 14-15 discloses instruction slices/processor units that execute instruction using register file, including global and private registers. It describes the register file as containing global/private registers and explains that instructions execute in instruction slices) the execution circuit to execute the instructions of the main sequence and the at least one concurrent interval (pages 14-15 teaches that VLIW packets contain one to four instructions, that the instructions in the packet execute at the same time, and that instruction slices provide the execution paths. Thus, the processor execution hardware executes instructions of the main sequence and concurrent interval concurrently) . Claim Rejections - 35 USC § 103 07-06 AIA 15-10-15 In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status. 07-20-aia AIA The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action: A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made. 07-21-aia AIA Claim s 2-5, 8-13, 15-20 are rejected under 35 U.S.C. 103 as being unpatentable over MAJC in view of Vishkin US Patent # 6,463,527 (hereinafter Vishkin) . As per claim 2, MAJC did not specifically teach a first instruction (IP) storage to store an IP for the main sequence or a second IP storage to store an IP for the at least one concurrent interval. However, Vishkin teaches that a thread is a series of instruction guided by a program counter, and that multiple threads may each run with different program counters. Thus, the main sequence has a PC/IP and the spawned/concurrent thread has its own PC/IP (Fig. 3, col. 3, lines 55-67 and col. Col. 10, lines 9-25). It would have been obvious to a person of ordinary skill in the art, before the effective filing date of the claimed invention, to combine MAJC’s teachings of multi-slice execution and shared/private register organization with Vishkin’s known instruction-control mechanism for starting, waiting for, and ending concurrently executed instruction sequences, because doing so would have predictably improved instruction fetch efficiency. As per claim 3, MAJC did not specifically teach wherein the second IP storage comprises a plurality of second IP storages each to store an IP for an active concurrent interval. However, Vishkin teaches spawning any number of threads concurrently, and that multithreading involves a plurality of threads, each guided by different program counters. The vector multithreading reference also expressly teaches a program counter register having a plurality of program counters, each representing a distinct thread (see col. 12, line 62 to col. 13, line 12 and col. 3, lines 55-67). It would have been obvious to a person of ordinary skill in the art, before the effective filing date of the claimed invention, to combine MAJC’s teachings of multi-slice execution and shared/private register organization with Vishkin’s known instruction-control mechanism for starting, waiting for, and ending concurrently executed instruction sequences, because doing so would have predictably improved instruction fetch efficiency. As per claim 4, MAJC did not specifically teach the features of claim 4. However, Vishkin teaches instruction used during the main program to initiate threads, and its syntax includes operands such as registers and thread-count/register parameters. It would have been obvious to use the source operand/register field to identify the starting address or control information for the spawned concurrent interval, because a spawned thread must be supplied with a starting PC/IP to begin execution (col. 3, lines 55-67 and col. Col. 10, lines 9-25; and col. 12, line 62 to col. 13, line 13). It would have been obvious to a person of ordinary skill in the art, before the effective filing date of the claimed invention, to combine MAJC’s teachings of multi-slice execution and shared/private register organization with Vishkin’s known instruction-control mechanism for starting, waiting for, and ending concurrently executed instruction sequences, because doing so would have predictably improved instruction fetch efficiency. . As per claim 5, MAJC teaches a fetch circuit (page 17, last paragraph of first column) but did not specify the fetch circuit to fetch an instruction of the first concurrent interval from the start address. However, Vishkin teaches that threads are series of instructions guided by program counters, and that thread instructions are transferred from instruction memory to local memory in the TCUs for execution (col. 3, lines 55-67 and col. Col. 10, lines 9-25). It would have been obvious to a person of ordinary skill in the art, before the effective filing date of the claimed invention, to combine MAJC’s teachings of multi-slice execution and shared/private register organization with Vishkin’s known instruction-control mechanism for starting, waiting for, and ending concurrently executed instruction sequences, because doing so would have predictably improved instruction fetch efficiency. As per claim 8, MAJC did not teach the features of the claim. However, Vishkin teaches that the number of virtual threads may exceed the physical TCUs, that the spawn control unit tracks virtual threads not yet issued, and that when a TCU terminates, it becomes available to run the next thread not yet issued, and that when a TCU terminates, it becomes available to run the next thread not yet issued (col. 4, line 43 to col. 5, line 8 and col. 6, line 53 to col. 7, line 20). As per claim 9, MAJC teaches multiple instruction slices, each with local control/stage and its own register file/computer structure (Fig. 2 and page 15). Vishkin teaches each TCU executing its own thread and transferring thread instructions to local TCU memory. It would have been obvious to a person of ordinary skill in the art, before the effective filing date of the claimed invention, to combine MAJC’s teachings of a partitioned instruction queue per interval/thread would have been obvious implementation of the MAJC slices/ Vishkin TCUs to keep independent instructions separated, which would improve overall efficiency. As per claim 10, Vishkin further teaches a JOIN instruction that terminates parallel threads and transitions back to serial execution after thread termination (col. 3, lines 21-64). It would have been obvious to a person of ordinary skill in the art, before the effective filing date of the claimed invention, upon thread/interval termination to remove or flush remaining instructions belonging to that interval and invalidates its PC/IP so the content is no longer active, which would improve efficiency. As per claim 11, MAJC failed to teach the features of the claim. However, Vishkin teaches that concurrent execution is synchronized at the join instruction and that sequential execution of the main program then resumes. That is the claimed wait/join behavior: the main sequence waits for the concurrent interval/thread completion before continuing (col. 3, lines 21-64). It would have been obvious to a person of ordinary skill in the art, before the effective filing date of the claimed invention, to combine MAJC’s teachings of multi-slice execution with Vishkin’s known instruction-control mechanism for starting, waiting for, and ending concurrently executed instruction sequences, because doing so would have predictably improved instruction fetch efficiency. As per claim 12, it’s a CRM/method of claim 4 and 1, plus concurrent execution. Vishkin teaches a SPAWN command encountered by the main program, causing transition from serial to parallel state and initiating concurrent threads. It also teaches that the spawned threads run concurrently, each guided by a program counter (see abstract and col. 3, lines 25-56). This renders obvious obtaining/storing a start address in a concurrent IP storage and executing the concurrent interval with the main sequence As per claim 13, it’s rejected for the same reasons as in claim 1. Further MAJC teaches local registers accessible only from the associated functional unit/slice and global registers shared by all slices. This maps to the concurrent interval register file and common register file (see page 15). As per claim 15, it’s rejected for the same reasons set forth above in claim 1. Furthermore, MAJC supports tightly coupled instruction-slice execution, and Vishkin teaches a single main program encountering spawn and then executing spawned instruction sequences derived from the same common program. As per claim 16, it’s rejected for the same reasons set forth above in claim 1 and 2. Furthermore, Vishkin teaches that when physical TCUs are fewer than virtual threads, the spawn control unit tracks not yet issued threads, and when a TCU terminates, it becomes available to run the next thread. This teaches the pending interval queue and next start address selection. Flushing/invalidating interval instructions at termination is an obvious pipeline housekeeping step. See Vishkin, col. 3, lines 21-64. As per claim 17, it’s rejected for the same reasons set forth above in claim 11. As per claim 18, it’s rejected for the same reasons set forth above in claims 1 and 12. Furthermore, MAJC teaches a processor architecture with instruction slices, local/private registers, shared/global registers, and compute structures. Vishkin teaches main and concurrent thread execution with PCs. As per claim 19, it’s rejected for the same reasons set forth above in claim 4. Further, Vishkin teaches spawn instruction initiates concurrent threads from the main program and includes operand/register fields controlling the spawned threads (col. 10, line 49-65). It would have been obvious to store the spawned thread’s starting PC/IP in the corresponding IP storage. As per claim 20, it’s rejected for the same reasons set forth above in claim 11. Furthermore, Vishkin teaches the join instruction synchronizes results of concurrent execution, the main program resumes, and examples show spawned threads computing/copying results and storing them, followed by serial execution using the result (col. 13, lines 7-52) . 07-21-aia AIA Claim s 6-7 and 14 are rejected under 35 U.S.C. 103 as being unpatentable over MAJC in view of Vishkin, and further in view of Yeh US PG-Pub # 2001/0047467 (hereinafter Yeh) . As per claim 6, MAJC and Vishkin failed to teach branch predictor to predict branch directions within the main sequence and concurrent interval. However, Yeh teaches a processor branch predictor coupled to an IP generator, using branch prediction entries associated with IP addresses to predict whether branches are taken and to predict subsequent IP addresses (see Fig. 1 and paragraph 0016-0022). It would have been obvious to a person of ordinary skill in the art, before the effective filing date of the claimed invention, to combine MAJC’s and Vishkin’s teachings of multi-slice execution with known instruction-control mechanism for starting, waiting for, and ending concurrently executed instruction and adding Yeh conventional branch prediction to each active instruction stream would have predictable improved instruction fetch efficiency and improve pipeline fetch performance. As per claim 7, Yeh further teaches predicting subsequent IP addresses and target addresses based on branch prediction information coupled to an IP generated. Applied to the concurrent interval/thread PC of Vishkin, the predicted target subsequent IP would be provided to the thread’s corresponding IP storage (paragraph 0016-0022). It would have been obvious to a person of ordinary skill in the art, before the effective filing date of the claimed invention, to combine MAJC’s and Vishkin’s teachings of multi-slice execution with known instruction-control mechanism for starting, waiting for, and ending concurrently executed instruction and adding Yeh conventional branch prediction to each active instruction stream would have predictable improved instruction fetch efficiency and improve pipeline fetch performance. As per claim 14, it’s rejected for the same reasons set forth above in claims 6 and 7. Further. Yeh teaches predicting a subsequent IP address and target address using branch prediction entries associated with the initial IP address (see Fig. 1 of Yeh and paragraph 0021-023). Applied to the concurrent interval/thread PC of Vishkin, the predicted next IP is stored in the concurrent interval’s IP storage . Conclusion 07-96 AIA The prior art made of record and not relied upon is considered pertinent to applicant's disclosure. US Patent # 7,523,465 shows method for generating speculative helper thread spawn-target points. US Patent # 7,020,763 shows processing architecture having a scalable number of processing paths and pipelines. Any inquiry concerning this communication or earlier communications from the examiner should be directed to IDRISS N ALROBAYE whose telephone number is (571)270-1023. The examiner can normally be reached Mon-Fri, 8am-4:30pm. Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice. 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If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000. /IDRISS N ALROBAYE/Supervisory Patent Examiner, Art Unit 2181 Application/Control Number: 19/106,190 Page 2 Art Unit: 2181 Application/Control Number: 19/106,190 Page 3 Art Unit: 2181 Application/Control Number: 19/106,190 Page 4 Art Unit: 2181 Application/Control Number: 19/106,190 Page 5 Art Unit: 2181 Application/Control Number: 19/106,190 Page 6 Art Unit: 2181 Application/Control Number: 19/106,190 Page 7 Art Unit: 2181 Application/Control Number: 19/106,190 Page 8 Art Unit: 2181 Application/Control Number: 19/106,190 Page 9 Art Unit: 2181 Application/Control Number: 19/106,190 Page 10 Art Unit: 2181 Application/Control Number: 19/106,190 Page 11 Art Unit: 2181
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