DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
Claim(s) 1-2, 7-10, 13, 16-20 is/are rejected under 35 U.S.C. 102(a)(2) as being anticipated by US 20110181261 (Kalechshtein).
Regarding claim 1, Kalechshtein teaches a power supply circuit (Fig. 6A shows power circuit 400), comprising a first power supply end (Fig. 6A shows first power supply end), a second power supply end (Fig. 6A shows second power supply end), a third power supply end (Fig. 6A shows third power supply end), a fourth power supply end (Fig. 6A shows fourth power supply end), a first inductor (Fig. 6A shows inductor 150), a first switch module (Fig. 6A shows switch module 20), a second switch module (Fig. 6A shows switch module 200), and an auxiliary circuit (Fig. 6A shows switches 60 and 70, diodes 130, 140 and inductor 190);
the first power supply end is connected to the second power supply end by means of the first switch module and the first inductor (Fig. 6A shows positive Vin is connected to positive Vout by means of the first switch module 20 and first inductor 150);
the first power supply end is connected to the fourth power supply end by means of the first switch module and the second switch module (Fig. 6A shows positive Vin is connected to negative Vin by means of first switch module 20 and second switch module 200);
wherein the auxiliary circuit comprises a target module (Fig. 6A shows switch 70), a third switch module (Fig. 6A shows switch 60), and a second inductor (Fig. 3A shows inductor 190) connected to the first inductor in parallel (Fig. 3A shows inductor 40 which is inductor 150 in Fig. 6A is in parallel to inductor 190) [0056, 0076]; and
a first connecting end of the target module is connected to a reference ground (Fig. 6A shows first connecting end of switch 70 is connected to ground) [0077], a second connecting end of the target module is connected to a first connecting end of the second inductor (Fig. 6A shows a second connecting end of switch 70 is connected to a first connected end of inductor 190), a second connecting end of the second inductor is connected to a first connecting end of the third switch module (Fig. 6A shows a second connecting end of the inductor 190 is connected to a first connecting end of the third switch 60), and a second connecting end of the third switch module is connected to the reference ground (Fig. 6A shows a second connecting end of the switch 60 is connected to ground).
Regarding claim 1, Kalechshtein teaches a power supply circuit (Fig. 3A shows synchronous buck converter 155), comprising a first power supply end (Fig. 3A shows first power supply end), a second power supply end (Fig. 3A shows second power supply end), a third power supply end (Fig. 3A shows third power supply end), a fourth power supply end (Fig. 3A shows fourth power supply end), a first inductor (Fig. 3A shows inductor 40), a first switch module (Fig. 3A shows switch module 20), a second switch module (Fig. 3A shows switch module 30), and an auxiliary circuit (Fig. 3A shows switches 60 and 70, diodes associated with n-channel mosfets 60 and 70 and inductor 190);
the first power supply end is connected to the second power supply end by means of the first switch module and the first inductor (Fig. 3A shows positive Vin is connected to positive Vout by means of the first switch module 20 and first inductor 40);
the first power supply end is connected to the fourth power supply end by means of the first switch module and the second switch module (Fig. 3A shows positive Vin is connected to negative Vin by means of first switch module 20 and second switch module 30);
wherein the auxiliary circuit comprises a target module (Fig. 3A shows switch 70), a third switch module (Fig. 3A shows switch 60), and a second inductor (Fig. 3A shows inductor 190) connected to the first inductor in parallel (Fig. 3A shows inductor 40 which is connected to inductor 190) [0056, 0076]; and
a first connecting end of the target module is connected to a reference ground (Fig. 3A shows first connecting end of switch 70 is connected to ground) [0077], a second connecting end of the target module is connected to a first connecting end of the second inductor (Fig. 3A shows a second connecting end of switch 70 is connected to a first connected end of inductor 190), a second connecting end of the second inductor is connected to a first connecting end of the third switch module (Fig. 3A shows a second connecting end of the inductor 190 is connected to a first connecting end of the third switch 60), and a second connecting end of the third switch module is connected to the reference ground (Fig. 3A shows a second connecting end of the switch 60 is connected to ground).
Regarding claim 2, Kalechshtein teaches wherein the reference ground is arranged at the first power supply end (Fig. 6A shows common point being reference ground is arranged at the first power supply end) [0077]; the auxiliary circuit further comprises a first diode and a second diode (Fig. 6A shows first and second diodes 130, 140 as part of auxiliary circuit comprising: switches 60 and 70, diodes 130, 140 and inductor 190); the second connecting end of the target module is connected to a first connecting end of the first diode (Fig. 6A shows second connecting end of the switch 70 is connected to a first connecting end of the first diode 130) [0077], and a second connecting end of the first diode is connected to a first clamping point (Fig. 6A shows a second connecting end of the first diode 130 is connected to a first clamping point), wherein the first clamping point is arranged at the second power supply end or the third power supply end (Fig. 6A shows the first clamping point is arranged at the second power supply end); and the second connecting end of the second inductor is connected to a first connecting end of the second diode (Fig. 6A shows the second connecting end of the second inductor 190 is connected to a first connecting end of the second diode 140), and a second connecting end of the second diode is connected to a second clamping point (Fig. 6A shows second connecting end of the second diode 140 is connected to a second clamping point), wherein the second clamping point is arranged at the fourth power supply end (Fig. 6A shows second clamping point arranged at the fourth power supply end).
Regarding claim 7, Kalechshtein teaches wherein a current passing through the first diode flows from the first connecting end of the first diode to the second connecting end of the first diode (Fig. 6A shows a current passing through the first diode flows from the first connecting end of the first diode associated with switch 70 to the second connecting end of the first diode associated with switch 70).
Regarding claim 8, Kalechshtein teaches wherein the target module comprises at least one target diode, or, the target module comprises a fourth switch module (Fig. 3A and Fig. 6A shows target module i.e. switch 70 is a fourth switch module) [0056].
Regarding claim 9, Kalechshtein teaches wherein the power supply circuit further comprises a controller (Fig. 12 shows a control circuitry 800 be used with converter of Fig. 3A to Fig. 6A) [0117], the first switch module is a first field-effect transistor (Fig. 3A shows switch 20 as a FET), the second switch module is a second field-effect transistor (FIG. 3A shows switch 30 and Fig. 6A shows switch 200 as a FET) [0046], the third switch module is a third field-effect transistor (FIG. 3A shows switch 70 as a FET) [0055], and switching on or off of the first field-effect transistor, the second field-effect transistor, or the third field-effect transistor is controlled by the controller (Fig. 12 shows control circuit 800 used to control switching on/off the switches 20, 30, 70 and 60) [0117].
Regarding claim 10, Kalechshtein teaches an electronic device, comprising the power supply circuit according to claim 1 (Fig. 6A shows converter 400 in an electronic device).
Regarding claim 13, Kalechshtein teaches wherein the reference ground is arranged at the first power supply end (Fig. 3A shows common point being reference ground is arranged at the first power supply end) [0056]; the auxiliary circuit further comprises a first diode and a second diode (Fig. 3A shows first and second diodes associated with switches 70 and 60); the second connecting end of the target module is connected to a first connecting end of the first diode (Fig. 3A shows first connecting end of the switch 70 i.e. target module is connected to a first connecting end of the first diode associated with switch 70), and a second connecting end of the first diode is connected to a first clamping point (Fig. 3A shows second connecting end of the first diode is connected to a first clamping point), wherein the first clamping point is arranged at the third power supply end (Fig. 3A shows first clamping point is arranged at the first power supply end); and the second connecting end of the second inductor is connected to a first connecting end of the second diode (Fig. 3A shows second connecting end of the second inductor 190 is connected to a first connecting end of the second diode associated with switch 60), and a second connecting end of the second diode is connected to a second clamping point (Fig. 3A shows a second connecting end of the second diode is connected to a second clamping point), wherein the second clamping point is arranged at the fourth power supply end (Fig. 3A shows wherein the second clamping point is arranged at the fourth power supply end).
Regarding claim 16, Kalechshtein teaches wherein a current passing through the first diode flows from the first connecting end of the first diode to the second connecting end of the first diode (Fig. 3A shows a current passing through first diode flows from the first connecting end of the first diode to the second connecting end of the first diode).
Regarding claim 17, Kalechshtein teaches wherein a current passing through the second diode flows from the first connecting end of the second diode to the second connecting end of the second diode (Fig. 6A shows a current passing through second diode 140 flows from the first connecting end of the second diode to the second connecting end of the second diode).
Regarding claim 18, Kalechshtein teaches wherein a current passing through the second diode flows from the first connecting end of the second diode to the second connecting end of the second diode (Fig. 3A shows a current passing through the second diode flows from the first connecting end of the second diode to the second connecting end of the second diode).
Regarding claim 19, Kalechshtein teaches wherein a current passing through the second diode flows from the first connecting end of the second diode to the second connecting end of the second diode (Fig. 3A shows a current passing through the second diode flows from the first connecting end of the second diode to the second connecting end of the second diode)..
Regarding claim 20, Kalechshtein teaches wherein the target module comprises a fourth switch module (Fig. 6A shows target module i.e. switch 70 is a fourth switch module) [0056].
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 3-6, 11, 14-15 is/are rejected under 35 U.S.C. 103 as being unpatentable over US 20110181261 (Kalechshtein) in view of US 2023/0041194 (Tang).
Regarding claim 3, Kalechshtein teaches wherein the first power supply end is a power supply input negative end (Fig. 6A shows first power supply end being negative end of Vin), the second power supply end is a power supply input positive end (Fig. 6A shows second power supply end is positive end of Vin), the third power supply end is a power supply output negative end (Fig. 6A shows third power supply end is negative end of Vout), and the fourth power supply end is a power supply output positive end (Fig. 6A shows fourth power supply end is positive end of Vout).
However, Kalechshtein does not teach wherein the power supply circuit comprises an inverting buck boost circuit under a direct current-common architecture.
However, Tang teaches wherein the power supply circuit comprises an inverting buck boost circuit under a direct current-common architecture (Fig. 1-2 shows IBB converter 105 i.e. inverting buck boost converter under a direct current-common architecture) [0028, 0041].
It would have been obvious to one with ordinary skill in the art before the effective filing date of the claimed invention to have wherein the power supply circuit comprises an inverting buck boost circuit under a direct current-common architecture as taught by Tang in order to ensure outputting voltages with a negative bias as is required by load demand.
Regarding claim 4, Kalechshtein teaches wherein the reference ground is arranged at the second power supply end (Fig. 3A shows common point being reference ground is arranged at the second power supply end) [0056]; the auxiliary circuit further comprises a first diode and a second diode (Fig. 3A shows first and second diodes associated with n-channel mosfets 60 and 70); the second connecting end of the target module is connected to a first connecting end of the first diode (Fig. 3A shows second connecting end of the switch 70 i.e. target module is connected to a first connecting end of the first diode associated with switch 70), and a second connecting end of the first diode is connected to a first clamping point (Fig. 3A shows a second connecting end of the first diode is connected to a first clamping point), wherein the first clamping point is arranged at the first power supply end (Fig. 3A shows the first clamping point is arranged at the first power supply end); and the second connecting end of the second inductor is connected to a first connecting end of the second diode (Fig. 3A shows second connecting end of the second inductor 190 is connected to a first connecting end of the second diode associated with switch 60), and a second connecting end of the second diode is connected to the first clamping point (Fig. 3A shows a second connecting end of the second diode is connected to the first clamping point).
Regarding claim 5, Kalechshtein teaches wherein the power supply circuit comprises a non-isolated buck circuit under a direct current-common architecture (Fig. 3A shows a non-isolated buck circuit under a direct current-common architecture) [0004, 0055]; and the first power supply end is a power supply input positive end (Fig. 3A shows first power supply end is +VIN), the second power supply end is a power supply output positive end (Fig. 3A shows second power supply end is +VOUT), the third power supply end is a power supply output negative end (Fig. 3A shows third power supply end is -VOUT), and the fourth power supply end is a power supply input negative end (Fig. 3A shows fourth power supply end is -VOUT).
Regarding claim 6, Kalechshtein teaches wherein the power supply circuit comprises a non-isolated boost circuit under a direct current-common architecture (Fig. 4A shows a non-isolated boost circuit 200) [0063]; and the first power supply end is a power supply output positive end (Fig. 4A shows first power supply end is a +VOUT), the second power supply end is a power supply input positive end (Fig. 4A shows second power supply end is a +VIN), the third power supply end is a power supply input negative end (Fig. 4A shows third power supply end is a -VIN), and the fourth power supply end is a power supply output negative end (FIG. 4A shows fourth power supply end is -VOUT).
Regarding claim 11, Kalechshtein teaches comprising a load and the electronic device according to claim 10, wherein the electronic device comprises a power converter connected to the load, and the power converter is configured to supply power to the load (Fig. 6A shows output capacitor 60 connected to a load) [0003-0004].
However, Kalechshtein does not teach a communication system.
However, Tang teaches a communication system [0119-0120, 0123].
It would have been obvious to one with ordinary skill in the art before the effective filing date of the claimed invention to have a communication system as taught by Tang in order to ensure that the power supply circuit includes a communication system there by communicating data with efficiency.
Regarding claim 14, wherein the power supply circuit comprises e first power supply end is a power supply input negative end, the second power supply end is a power supply input positive end, the third power supply end is a power supply output negative end, and the fourth power supply end is a power supply output positive end.
However, Kalechshtein does not teach wherein the power supply circuit comprises an inverting buck boost circuit under a direct current-common architecture.
However, Tang teaches wherein the power supply circuit comprises an inverting buck boost circuit under a direct current-common architecture (Fig. 1-2 shows IBB converter 105 i.e. inverting buck boost converter under a direct current-common architecture) [0028, 0041].
It would have been obvious to one with ordinary skill in the art before the effective filing date of the claimed invention to have wherein the power supply circuit comprises an inverting buck boost circuit under a direct current-common architecture as taught by Tang in order to ensure outputting voltages with a negative bias as is required by load demand.
Regarding claim 15, Kalechshtein teaches wherein a current passing through the first diode flows from the first connecting end of the first diode to the second connecting end of the first diode (Fig. 3A shows a current passing through first diode flows from the first connecting end of the first diode to the second connecting end of the first diode).
Claim(s) 12 is/are rejected under 35 U.S.C. 103 as being unpatentable over US 20110181261 (Kalechshtein) in view of US 2023/0041194 (Tang) further in view of US 2015/0244277 (Wangemann).
Regarding claim 12, Kalechshtein does not teach wherein the communication system further comprises an alternating current-direct current converter, the alternating current-direct current converter is connected to the power converter, and the load comprises a remote radio unit.
However, Tang teaches wherein the communication system (FIG. 17 shows communication system) further comprises the load comprises a remote radio unit (Fig. 1 shows power circuit 100 wherein the load comprises a transmitter i.e. remote radio unit) [0031].
It would have been obvious to one with ordinary skill in the art before the effective filing date of the claimed invention to have the communication system further comprises the load comprises a remote radio unit as taught by Tang in order to ensure that power converter supplies power efficiently to the load in order for the load to transmit information wirelessly in accordance to the load demand thereby.
However, Wangemann teaches further comprises an alternating current-direct current converter (Fig. 8 shows alternating current-direct current converter 9a), the alternating current-direct current converter is connected to the power converter (Fig. 8 shows alternating current-direct current converter 9a connected to DC-DC converter 5) [0048-49].
It would have been obvious to one with ordinary skill in the art before the effective filing date of the claimed invention to have further comprises an alternating current-direct current converter is connected to the power converter as taught by Wangemann in order to ensure that the power supply circuit is operable with AC voltages.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to SWARNA N CHOWDHURI whose telephone number is (571)431-0696. The examiner can normally be reached Mon-Fri 8am-5pm.
Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Rexford Barnie can be reached at 571-272-7496. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000.
SWARNA N. CHOWDHURI
Examiner
Art Unit 2836
/S.N.C/Examiner, Art Unit 2836
/REXFORD N BARNIE/Supervisory Patent Examiner, Art Unit 2836
