Detailed Action
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claim(s) 1, 3-20 is/are rejected under 35 U.S.C. 102(a) (1) as being anticipated by Wilson [20190370217]
As to claim ,1
Wilson [20190370217] teaches A device comprising- a pair of processing cores that are configured to exchange data, wherein the device is configured to enable or disable one or more of the pair of processing cores [0053: “HOST_READY and DEVICE_READY are low frequency signals for connection management. DEVICE_READY is a control signal that is unidirectionally driven by the slave IC, and is configured to enable and disable the HSIC port ”];and
logic circuitry implementing a connect/disconnect interface between the pair of processing cores, wherein the connect/disconnect interface between the pair of processing cores [0010; “An apparatus configured to internally manage connections between a first processor and a second processor is disclosed. In one embodiment, the apparatus includes: logic configured to perform a handshake procedure; responsive to the handshake procedure, logic configured to connect the first processor to the second processor”] is configured to:
assume a connected state in which the pair of processing cores exchange data [0009: “performing a handshake procedure; responsive to the handshake procedure, connecting the first processor to the second processor; transacting data via the connection” Examiner’s note: Assuming connected state in which data is exchanged does not provide clarity. Reader does not need to assume, either it exchanges or not. Other if reader/examiner has to assume connected state exchanges data, it basically does not exchange in another scenario, when it is not assumed. Applicant is requested to clarify the limitation.]; and
a disconnected state in which one or more of the processing cores is unable to receive data [0010: “logic configured to connect the first processor to the second processor; logic configured to transact data via the connection; and responsive to a suspension condition, logic configured to suspend the connection. ”].
As to claim ,3
Wilson teaches any one of wherein when in the disconnected state, the connect/disconnect interface can assume a disconnect-with-wakeup mode during which new traffic causes the connect/disconnect interface to assume a connected state [0037: “In still other embodiments, the parameters may include a possible cause for re-establishing connection (e.g., requested operation, device transfer, update, etc.). Those of ordinary skill in the related arts will recognize the myriad of other parameters which have suitable utility within the connection establishment and/or initialization, given the contents of the present disclosure. ”].
As to claim 4,
Wilson et al teaches when in the disconnected state, the connect/disconnect interface can assume a disconnect-with- terminate mode during which any traffic is terminated by one of the pair of processing cores [0044: “ At step 108 of the method 100, responsive to a termination condition, the connection is suspended and/or terminated. In one embodiment, at least one of the first and second processors request the link be suspended. In other embodiments, the termination condition is an assertion of a reset. In still other embodiments, the termination condition may be based on e.g., a time interval of inactivity, power consumption considerations, an error condition (which presumably can be resolved by resetting the connection), etc.” and 0029: “ The connect/disconnect procedure is used upon a termination condition to trigger either suspension and/or complete termination of the data connection between the ICs.”].
As to claim 5,
Wilson teaches wherein each processing core is further configured to transmit output signals to the other another processing device comprising: i) a send request to connect, ii) a send request to disconnect, and iii) a send denial of a disconnection request [0029: “The connect/disconnect procedure is used upon a termination condition to trigger either suspension and/or complete termination of the data connection between the ICs. ” and 0053: “HOST_READY is a control signal that is unidirectionally driven by the master IC, and is configured to request a change of DEVICE_READY. Specifically, when the HOST_READY is asserted by the master IC, the slave IC should responsively assert the DEVICE_READY and both master IC and slave IC enable HSIC circuitry for transactions. Similarly, when the HOST_READY is deasserted by the master IC, the slave IC can deassert the DEVICE_READY, and both master IC and slave IC can transition to an IDLE state. In some embodiments, the HOST_READY signal has a pull-down resistor to avoid a floating value when the master IC is not driving a value. TABLE 1 and TABLE 2 summarize HOST_READY and DEVICE_READY logic, respectively ”].
As to claim 6,
Wilson teaches processing core is further configured to receive input signals from the other processing device comprising: i) receive a request to connect, ii) receive a request to disconnect, and iii) receive a denial of [[a]] the disconnection request. [0029: “The connect/disconnect procedure is used upon a termination condition to trigger either suspension and/or complete termination of the data connection between the ICs. ” and 0053: “HOST_READY is a control signal that is unidirectionally driven by the master IC, and is configured to request a change of DEVICE_READY. Specifically, when the HOST_READY is asserted by the master IC, the slave IC should responsively assert the DEVICE_READY and both master IC and slave IC enable HSIC circuitry for transactions. Similarly, when the HOST_READY is deasserted by the master IC, the slave IC can deassert the DEVICE_READY, and both master IC and slave IC can transition to an IDLE state. In some embodiments, the HOST_READY signal has a pull-down resistor to avoid a floating value when the master IC is not driving a value. TABLE 1 and TABLE 2 summarize HOST_READY and DEVICE_READY logic, respectively ”].
As to claim 7,
Wilson teaches wherein the output signals and the input signals are implemented using six separate wires between the processing cores [ 0005: “As used herein, the term “inter-chip” refers without limitation to connections between ICs of a device. HSIC (High-Speed Inter-Chip™) is an existing industry standard for an inter-chip communications. HSIC physical signaling is a source synchronous two-wire (STROBE, DATA) serial interface. Existing solutions provide a 480 Mbps data rate (240 MHz Double Data Rate (DDR)). Signaling is bi-directional, and uses Non-Return-to-Zero-Inverted (NRZI) line coding. From a software protocol standpoint, HSIC is based on the Universal Serial Bus™ (USB) software protocol, and is typically compatible with existing USB software stacks. ” and 0062: “The apparatus may further include optional additional peripherals 212 including, without limitation, one or more GPS transceivers, or network interfaces such as IrDA ports, Bluetooth transceivers, USB, FireWire™, WiMAX transceivers, etc. ”].
As to claim 8,
Wilson teaches this claim according to the reasoning set forth in claim 1 supra.
As to claim 9,
Wilson teaches the pair of processing cores sharing the connect/disconnect interface are peer processing cores that are both controlled by a power manager [0061: “ The illustrated power management subsystem 210 provides power to the device, and may include an integrated circuit and or a plurality of discrete electrical components. In portable devices, the power management subsystem 210 may additionally be configured to interface with a rechargeable battery power source within the device.” Nand 0032; “In yet another embodiment, the first and second processors are peer entities. ”].
10-14,
Wilson teaches this claim according to the reasoning set forth in claim 3-7supra.
As to claim 15,
Wilson teaches this claim according to the reasoning set forth in claim 1 supra.
As to claim 16,
Wilson teaches wherein the pair of processing cores sharing the connect/disconnect interface are peer processing cores that are both controlled by a power manager [0061: “The illustrated power management subsystem 210 provides power to the device, and may include an integrated circuit and or a plurality of discrete electrical components. In portable devices, the power management subsystem 210 may additionally be configured to interface with a rechargeable battery power source within the device.” Nand 0032; “In yet another embodiment, the first and second processors are peer entities.”].
.
17-20,
Wilson teaches this claim according to the reasoning set forth in claim 3-6 supra.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 2 is/are rejected under 35 U.S.C. 103 as being unpatentable over Wilson [20190370217], in view of Garg [20220100247].
As to claim 2,
Wilson teaches wherein the pair of processing cores sharing the connect/disconnect interface are controlled by respective power controllers [0061: “The illustrated power management subsystem 210 provides power to the device, and may include an integrated circuit and or a plurality of discrete electrical components. In portable devices, the power management subsystem 210 may additionally be configured to interface with a rechargeable battery power source within the device.” Nand 0032; “In yet another embodiment, the first and second processors are peer entities.”].
But does not explicitly teach interface are controlled by respective power controllers.
However, Garg [20220100247] teaches [0244: “Any number of cores may be provided on a processor (or compute) dielet such as the first dielet or the second dielet, together with further agents at nodes of the fabric. Similarly, to second dielet 2101-1, a third dielet 2101-2, a fourth dielet 2101-3 and a fifth dielet 2101-4 each comprise multiple processor cores and memory controller agents in this example and each dielet has a respective local power management unit 2103 (e.g., 103).”]
It would have been obvious to person of ordinary skill in the art before the effective filing date of the claimed invention o combine teaching of Wilson and Gard because both are directed toward power management of processor core. Gard improves upon teaching of Wilson by being able to control power by individual power management such that power required and load can be efficiently managed based on the power need.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to KESHAB R PANDEY whose telephone number is (571)270-0176. The examiner can normally be reached Monday-Friday 9:00-5:00(ET).
Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Jaweed Abbaszadeh can be reached at (571) 270-1640. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000.
/KESHAB R PANDEY/ Primary Examiner, Art Unit 2176
Prosecution Insights