CTNF 19/106,586 CTNF 87379 Detailed Action 12-151 AIA 26-51 12-51 Status of Claims Notice of Pre-AIA or AIA Status 07-03-aia AIA 15-10-aia The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA. Claims 1-40 are presented for examination. Claims 1-20 are cancelled by the applicant. Claims 21-40 are rejected. This Action is Non-Final. Information Disclosure Statement 06-52 The information disclosure statement (IDS) submitted on 02/25/2025 and 06/09/2025,the submission is in compliance with the provisions of 37 CFR 1.97. Accordingly, the information disclosure statement is being considered by the examiner. Claim Rejections - 35 USC § 103 07-06 AIA 15-10-15 In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status. 07-20-aia AIA The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action: A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made. 07-21-aia AIA Claim s 21-40 are rejected under 35 U.S.C. 103 as being unpatentable over Feritag, Jr. et al. (US Patent No: 7,088,680 B1) in view of Lo (US Patent No: 9,130,746 B1) .. As per claim 21, Feritag, Jr. teaches a host device comprising: first circuitry to receive one or more packets sent by a communication device [col.1,ll.36-40, A receiving digital communication system may receive the serial data stream via the transmission medium,…], over a serial communication interface [Fig.3, a serial interface unit .], between the communication device and the host device [the serial communication system includes a serial communication controller coupled to the host computer, an interface unit coupled between the serial communication controller and the transmission medium, and a timing recovery unit coupled between the serial communication controller and the interface unit;… ], wherein the one or more packets comprise media configuration information stored in a memory of the communication device [col.2,l.65 to col.3,l.6, The microcontroller may be coupled to the each of the functional units and to the memory unit, and may be configured to transfer state information between the functional units and the memory unit such the functional units operate alternately upon the portions of the multiple serial data channels within the serial data stream.]; and second circuitry to transmit data packets over the serial communication interface [Fig.1, col.1,ll.33-40, A transmitting digital communication system may combine the digital data of several individual data channels into a single serial data stream using TDM, then transmit the serial data stream upon the transmission medium.], after the host device has been configured based on the media configuration information [col.5,ll.48-57, Host processor 12 configures serial communication system 10 for operation, provides digital data to serial communication system 10 for transmission upon transmission medium 14, and reads digital data from communication system 10 which has been received via transmission medium 14.]. Feritag, Jr. disclose wherein the one or more packets comprise media configuration information stored in a memory of the communication device but does not explicitly disclose wherein the one or more packets comprise media configuration information stored in a memory of the communication device and an indication of a mapping of the memory of the communication device. Lo discloses wherein the one or more packets comprise media configuration information stored in a memory of the communication device and an indication of a mapping of the memory of the communication device [Abstract,col.1,ll.39-48, The apparatus includes a setup logic configured to control the PHY transceiver to initiate an auto-negotiation sequence over the single twisted pair channel with a remote device upon detecting a transmission from the remote device on the single twisted pair channel.]. It would have been obvious one ordinary skill in the art before the effective filling, date of the claimed invention, to include Lo ’s apparatus for auto-negotiating over single pair physical layer (PHY) into Freitag,Jr. ’s serial communication system for the benefit of avoid collisions between transmissions on the single twisted pair channel when using the half-duplex mode; and the first time interval is a time period to wait in order to avoid a reflection of the signal on the twisted pair channel that interferes with other transmissions; also the communications from the auto-negotiation sequence is traded back and forth while using half-duplex mode and avoiding collisions, by using the fixed time interval between transmissions. Since transmissions occurring at the same time on the single twisted pair channel in half-duplex mode result in a collision, using the fixed time interval to separate communications between device provides for two-way communications on the single twisted pair channel without collisions occurring ( Lo ,col.6, ll.39-52) to obtain the invention as specified in claim 1. As per claim 22, Freitag,Jr. and Lo teach all the limitations of claim 21 above, where Freitag,Jr. and Lo teach, a host device [ Freitag,Jr. , Fig.1, host computer 12.], wherein the media configuration information and the indication of the mapping of the memory are included within one or more Auto- Negotiation Next Pages [ Lo , Abstract, col.1, ll.39-48, The apparatus includes a setup logic configured to control the PHY transceiver to initiate an auto-negotiation sequence over the single twisted pair channel with a remote device upon detecting a transmission from the remote device on the single twisted pair channel.]. As per claim 23, Freitag,Jr. and Lo teach all the limitations of claim 22 above, where Freitag,Jr. and Lo teach, a host device [ Freitag,Jr. , Fig.1, host computer 12.], wherein the one or more Auto-Negotiation Next Pages include a message code field value identifying the Auto-Negotiation Next Pages as including media configuration information [ Lo , Abstract,col.1,ll.39-48, The apparatus includes a setup logic configured to control the PHY transceiver to initiate an auto-negotiation sequence over the single twisted pair channel with a remote device upon detecting a transmission from the remote device on the single twisted pair channel.]. As per claim 24, Freitag,Jr. and Lo teach all the limitations of claim 21 above, where Freitag,Jr. and Lo teach, a host device [ Freitag,Jr. , Fig.1, host computer 12.], wherein configuring the host device based on the media configuration information comprises setting a frequency of at least one clock of the host device [ Lo , col.4, ll.15-23,… the setup logic 120 is configured to listen for a predefined time interval for the transmission. In one embodiment, the predefined time interval includes a first time interval and a second time interval. The first time interval is a time period to wait in order to avoid a reflection of the signal on the twisted pair channel that may interfere with other transmissions.]. As per claim 25, Freitag,Jr. and Lo teach all the limitations of claim 21 above, where Freitag,Jr. and Lo teach, a host device [ Freitag,Jr. , Fig.1, host computer 12. ], wherein configuring the host device based on the media configuration information comprises setting an equalization filter of the host device [ Lo ,col.11,ll.29-39, The selected instructions configure serial communication controller 16 to handle m serial data channels within a time division multiplexed serial data stream, where m is greater than or equal to 1 and less than or equal to n.]. As per claim 26, Freitag,Jr. and Lo teach all the limitations of claim 21 above, where Freitag,Jr. teaches, a host device [ Freitag,Jr. , Fig.1, host computer 12. ], wherein a packet of the one or more packets comprises location information of the memory and media configuration information stored at that location in the memory [ Freitag,Jr. , claim 1,… wherein each functional unit comprises a set of memory elements, and wherein state information stored within the set of memory elements of a given functional unit determines the one of the unique operating states in which the functional unit is operating.]. As per claim 27, Freitag,Jr. and Lo teach all the limitations of claim 26 above, where Freitag,Jr. teaches, a host device [ Freitag,Jr. , Fig.1, host computer 12.], wherein the location information comprises an indication of a byte of the memory [ Freitag, Jr. ,col.7,ll.44-50, Dual-port memory unit 44 includes multiple memory locations for storing instructions and data.]. As per claim 28, Freitag,Jr. and Lo teach all the limitations of claim 21 above, where Freitag,Jr. teaches, a host device [ Freitag,Jr. , Fig.1, host computer 12.], wherein the media configuration information comprises a transceiver identifier value [ Freitag,Jr. , The address field allows identification of the transmitting digital communication system (i.e., transmitter) and the receiving digital communication system (i.e., receiver) involved in the transmission.]. As per claim 29, Freitag,Jr. and Lo teach all the limitations of claim 21 above, where Freitag,Jr. teaches, a host device [ Freitag,Jr. , Fig.1, host computer 12.], wherein the media configuration information comprises an indication of a type of serial data encoding to be used by the communication device to send data packets over the serial communication interface [ Freitag,Jr. , col.1,ll.13-18, A transmission medium carries signal-encoded information (i.e., data) from one point to another.]. As per claim 30, Freitag,Jr. and Lo teach all the limitations of claim 21 above, where Freitag,Jr. teaches, a host device [ Freitag,Jr. , Fig.1, host computer 12.], wherein the media configuration information comprises an indication of a connector type of the communication device [ Freitag, Jr. , col.5,l.64 to col.6,l.14, Interface unit 18 is configured to receive the time division multiplexed serial data stream from transmission medium 14 and to provide a time division multiplexed "Rx Data" serial data stream containing the identical information to timing recovery unit 20.]. As per claim 31, Freitag,Jr. and Lo teach all the limitations of claim 21 above, where Freitag,Jr. teaches, a host device [ Freitag,Jr. , Fig.1 , host computer 12.], wherein the media configuration information comprises an identification of an electronic or optical interface of the communication device [ Freitag,Jr. , The address field allows identification of the transmitting digital communication system (i.e., transmitter) and the receiving digital communication system (i.e., receiver) involved in the transmission.]. As per claim 32, Freitag,Jr. and Lo teach all the limitations of claim 21 above, where Freitag,Jr. teaches, a host device [ Freitag,Jr. , Fig.1, host computer 12.], further comprising a processor [ Freitag,Jr., col.11,ll.29-39, Host processor 12 initializes the operations of serial communication controller 16 by writing selected instructions to instruction store block 84 within dual-port memory system 44 via host processor interface 46,…]. As per claim 33, Freitag,Jr. and Lo teach all the limitations of claim 32 above, where Freitag,Jr. teaches, a host device [ Freitag,Jr. , Fig.1, host computer 12.], further comprising one or more of: a battery communicatively coupled to the processor, a display communicatively coupled to the processor, or a network interface communicatively coupled to the processor [ Freitag,Jr., col.11,ll.29-39, Host processor 12 initializes the operations of serial communication controller 16 by writing selected instructions to instruction store block 84 within dual-port memory system 44 via host processor interface 46,…]. As per claims 34-38, claims 34-38 are rejected in accordance to the same rational and reasoning as the above claims 21-22,26,31 and 33 above, wherein claims 34-38 are the device claims for the device of claims 21-22,26,31 and 33. As per claims 39-40, claims 39-40 are rejected in accordance to the same rational and reasoning as the above claims 21-22 above, wherein claims 39-40 are the method claims for the device of claims 21-22. Any comments considered necessary by applicant must be submitted no later than the payment of the issue fee and, to avoid processing delays, should preferably accompany the issue fee. Such submissions should be clearly labeled “Comments on Statement of Reasons for Allowance.” Conclusion RELEVANT ART CITED BY THE EXAMINER The following prior art made of record and not relied upon is cited to establish the level of skill in the applicant’s art and those arts considered reasonably pertinent to applicant’s disclosure. See MPEP 707.05(c). References Considered Pertinent but not relied upon Severson et al. (US Patent Application Pub. No: 20070214389 A1) teaches performing a debug operation on a processor after a power collapse is provided. Severson discloses an idle state of the processor is detected during an execution mode of the processor. Severson suggests the idle state is determined to be associated with a power collapse event; and a debug state of the processor is restored by loading debug registers within the processor during the execution mode. Stanton et al.(US Patent Application Pub. No: 20100329285 A1) teaches a method and apparatus for synchronizing time between a master device and a target device arranged across a network, wherein the target device communicates to the master device through a PCIe interconnect includes transmitting a first message at a first time from the master device to the target device, the first message including a message indicator; and receiving a reply message at a subsequent time from the target device to the master device, the reply message including the message indicator. Any inquiry concerning this communication or earlier communications from the examiner should be directed to GETENTE A YIMER whose telephone number is (571)270-7106. The examiner can normally be reached on Monday-Friday 6:30-3:00.Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice. If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, IDRISS N ALROBAYE can be reached on 571-270-1023. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.Information regarding the status of an application may be obtained from the Patent Application Information Retrieval (PAIR) system. Status information for published applications may be obtained from either Private PAIR or Public PAIR. Status information for unpublished applications is available through Private PAIR only. For more information about the PAIR system, see https://ppair my.uspto.gov/pair/ PrivatePair. Should you have questions on access to the Private PAIR system, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative or access to the automated information system, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000. /GETENTE A YIMER/Primary Examiner, Art Unit 2181 Application/Control Number: 19/106,586 Page 2 Art Unit: 2181 Application/Control Number: 19/106,586 Page 3 Art Unit: 2181
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