DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
Priority
Acknowledgment is made of applicant’s claim for foreign priority under 35 U.S.C. 119 (a)-(d).
Information Disclosure Statement
The information disclosure statement (IDS) submitted on 02/27/2025 is in compliance with the provisions of 37 CFR 1.97. Accordingly, the information disclosure statement is being considered by the examiner.
Claim Objections
Claims 3 and 14 are objected to because of the following informalities:
Claim 3 lines 6 – 7 recites “…; and having an area K times (where K is a positive number) larger than the area of the first PMOS transistor; …”. However, it appears that it should recite “…; and having an area K times (where K is a positive number) larger than an area of the first PMOS transistor; …”.
Claim 14 line 8 recites “an amplification circuit configured to differentially amplify voltages of sixth and seventh nodes”. However, it appears that it should recite “an amplification circuit configured to differentially amplify voltages of a sixth and a seventh nodes”
Appropriate correction is required.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
Claim(s) 1 and 2 are rejected under 35 U.S.C. 103 as being unpatentable over Rao et al (US Patent No. 7,755,419 B2) in view of Chen (US Pub. No. 2008/0157746 A1); (hereinafter Rao et al and Chen).
Regarding claim 1, Rao et al [e.g., Fig. 2] discloses a bandgap reference voltage generation circuit [e.g., -- refer to Fig. 2 --, circuit 200] comprising: a start-up circuit [e.g., start-up circuit 204] configured to output a start-up signal when a first supply voltage rises [e.g., outputs start signals on node 210, col. 5 lines 45 - 52 recites “In operation, upon start-up, once a start node 210 reaches about 100 mV, transistor N3 can operate in either sub-threshold saturation (VGS < Vtn, VDS > 3*VT (75 mv)) or strong inversion saturation (VGS > Vtn, VGD < Vtn (100 mV)), where VGS is the gate-to-source voltage for transistor N3, Vtn is the threshold voltage of transistor N3, VDS is the drain-to-source voltage for transistor N3, and VT is the "thermal" voltage for the transistor N3.”]; and a bandgap reference core circuit configured to be activated in response to the start-up signal [e.g., self-biased reference circuit 202], and to generate and output a bandgap reference voltage [e.g., generates VREF], wherein the start-up circuit includes: a beta-multiplier reference circuit including a cascode current mirror circuit [e.g., beta multiplier circuit including first current mirror (P1 and P2) and second current mirror (N1 and N2) cascaded] forming a first current path and a second current path between a first power line and a second power line [e.g., forming first current path (P2 and N2) and second current path (P1 and N1) between Vcch and Vgnd]; a start-up output part [e.g., transistor P3] configured to output the start-up signal in response to a voltage at an output node of the second current path [e.g., circuit begins operation when voltage on node 208 is between Vcch and Vgnd, col. 4 – 5 lines 66 and continuing on lines 1 – 2 recites “A self-biased reference circuit 202 can be placed in an operational mode by driving a bias node 208 to a stable potential between Vcch and Vgnd, while second bias node 206 can be isolated from a high power supply voltage (Vcch).”].
Rao et al does not disclose a comparator configured to compare the bandgap reference voltage with a target voltage to inactivate an operation of the start-up circuit.
Chen [e.g., Fig. 7] teaches a comparator [e.g., comparator CP] configured to compare the bandgap reference voltage with a target voltage to inactivate an operation of the start-up circuit [e.g., compares reference voltage Vr and detection voltage VA to control transistor MN0, p. 0047 recites “When the bandgap reference circuit 400A is powered on, the comparator CP in the start-up circuit 420A compares the reference voltage Vr and the detection voltage VA and outputs an enabling signal EN with high level to the transistor MN0 when the detection voltage VA does not exceed the reference voltage Vr. Namely, start-up circuit 420A pulls low the voltage Vbp by the transistor MN0 to trigger the current mirror CM when the detection voltage VA is smaller than the reference voltage Vr after powering on. When the detection voltage VA exceeds the reference voltage Vr, the comparator CP stops outputting the enabling signal EN, such that the transistor MN0 is turned off and the current mirror CM is controlled by output of the operational amplifier OP.”].
It would have been obvious to one of ordinary skill in the art before the effective filing date to modify Rao et al with a comparator configured to compare the bandgap reference voltage with a target voltage to inactivate an operation of the start-up circuit as suggested by Chen to enable/disable operation of the start-up circuit once a desired voltage level is reached and start-up has been completed.
Regarding claim 2, Rao et al [e.g., Fig. 2] discloses wherein the beta-multiplier reference circuit includes: a PMOS current mirror and an NMOS current mirror connected in a cascode form between the first and second power lines [e.g., PMOS current mirror (P1 and P2) and NMOS current mirror (N1 and N2)]; and a start-up control part [e.g., transistor P3] connected between a first node [e.g., gate connection between P4, P1, P2 and P5] connected to a gate terminal of the PMOS current mirror [e.g., connected to P4 which is gate connected to the first node. For examination purposes, the examiner will interpret the term “connected” in its broadest sense to refer as electrical components that are connected directly or indirectly in a way that allows for the transfer of electrical energy or signals between them] and a second node connected to a gate terminal of the NMOS current mirror [e.g., drain of transistor P3 connected to node 208], and configured to start up an operation of the beta-multiplier reference circuit [e.g., col. 5 lines 58 - 64 recites “Said in another way, in a start-up operation, the above-described operation of transistor N3 can ensure start node 210 is pulled low and transistor P3 is enabled to establish a stable operating point for self-biased reference circuit 202. Once such a stable operating point has been reached, transistor P4 can dominate current path P4/N3, resulting in transistor P3 being turned off, completing the start-up operation.”].
Claim(s) 3 and 4 are rejected under 35 U.S.C. 103 as being unpatentable over Rao et al (US Patent No. 7,755,419 B2) in view of Chen (US Pub. No. 2008/0157746 A1) and Askin (US Pub. No. 2021/0341959 A1); (hereinafter Rao et al, Chen and Askin et al).
Regarding claim 3, Rao et al [e.g., Fig. 2] discloses wherein the PMOS current mirror includes: a first PMOS transistor included in the first current path [e.g., P2] and having a gate terminal and a drain terminal connected to the first node [e.g., gate and drain connected to first node (gate connection between P2, P1 and P4)]; a second PMOS transistor included in the second current path [e.g., P1], having a gate terminal connected to the first node [e.g., gate connection between P2, P1 and P4].
Rao et al does not disclose having an area K times (where K is a positive number) larger than the area of the first PMOS transistor; and a resistor connected in series between the first power line and the second PMOS transistor, wherein the current flowing in the second current path is determined by a current gain p of the first PMOS transistor, a multiple of the K, and a resistance value of the resistor.
Askin et al [e.g., Fig.1] teaches having an area K times (where K is a positive number) larger than the area of the first PMOS transistor [e.g., p. 0025 recites “FIG. 1 provides an electric circuit diagram of a simple single-ended NPN bipolar transistor implementation of a current mirror 100 with a current gain of K,…”]; and a resistor connected in series between the first power line and the second PMOS transistor [e.g., resistor generating output current 108], and wherein the current flowing in the second current path is determined by a current gain p of the first PMOS transistor, a multiple of the K, and a resistance value of the resistor [e.g., p. 0025 recites “As shown in FIG. 1, the current mirror 100 may include a first transistor Q1 (which may be referred to as an “input transistor”) and a second transistor Q2 (which may be referred to as an “output transistor”). An input current 102 (IIN) (i.e., the current to be mirrored at the output of the current mirror 100 to generate an output current 108) may be provided by an input current source 104. The current mirror 100 may first generate a control voltage (voltage VN1) at a node 106 (node N1) by placing the transistor Q1 in feedback to force the current at a collector terminal 110 (or, simply, “collector” 110) of the transistor Q1 to be equal to the input current 102. An emitter terminal 112 (or, simply, “emitter” 112) of the transistor Q1 may be connected to ground, as shown in FIG. 1. A base terminal 114 (or, simply, “base” 114) of the transistor Q1 may be coupled to a base 124 of the transistor Q2. The base 124 of the output transistor Q2 may be driven with the voltage VN1 carrying the input current information to generate the output current 108. FIG. 1 also indicates a collector 120 of the transistor Q2 and an emitter 122 of the transistor Q2, where the emitter 122 may be coupled to ground and where the output current 108 is the current at the collector 120, as shown in FIG. 1. When the emitter area of the transistor Q2 is K times larger than that of the transistor Q1, the output current 108 (Ia) may be equal to KIIN.”].
It would have been obvious to one of ordinary skill in the art before the effective filing date to modify Rao et al with having an area K times (where K is a positive number) larger than the area of the first PMOS transistor; and a resistor connected in series between the first power line and the second PMOS transistor, and wherein the current flowing in the second current path is determined by a current gain p of the first PMOS transistor, a multiple of the K, and a resistance value of the resistor as suggested by Askin et al to generate a mirror current with a different gain proportional to the area of the transistors.
Regarding claim 4, Rao et al [e.g., Fig. 2] discloses wherein the NMOS current mirror includes: a first NMOS transistor included in the first current path and having a gate terminal connected to the second node [e.g., N2 with gate connected to node 208]; and a second NMOS transistor included in the second current path and having a gate terminal and a drain terminal connected to the second node [e.g., NMOS N1 with drain and gate connected to node 208].
Claim(s) 15 are rejected under 35 U.S.C. 103 as being unpatentable over Rao et al (US Patent No. 7,755,419 B2) in view of Chen (US Pub. No. 2008/0157746 A1) and Song et al (US Pub. No. 2017/0293314 A1); (hereinafter Rao et al, Chen and Song et al).
Regarding claim 15, Rao et al discloses the claimed invention except for a semiconductor device comprising: (..), and a device circuit configured to receive and use the bandgap reference voltage from the bandgap reference voltage generation circuit.
Song et al [e.g., Fig. 1] teaches a semiconductor device [e.g., semiconductor device 100] comprising: (…), and a device circuit configured to receive and use the bandgap reference voltage from the bandgap reference voltage generation circuit [e.g., comprising Reference voltage circuit 102 and power supply 104 receiving Vref generated by Reference voltage 102].
It would have been obvious to one of ordinary skill in the art before the effective filing date to modify Rao et al with a semiconductor device comprising: ,and a device circuit configured to receive and use the bandgap reference voltage from the bandgap reference voltage generation circuit as suggested by Song et al and as commonly understood in the art to produces a reference voltage Vref for power supply which generates power supply voltage V0 corresponding to a level of Vref.
Examiner’s Note
Examiner has cited particular columns, paragraphs and line numbers in the references applied to the claims above for the convenience of the applicant. Although the specified citations are representative of the teachings of the art and are applied to specific limitations within the individual claim, other passages and figure may apply as well. It is respectfully requested from the applicant in preparing responses, to fully consider the references in their entirety as potentially teaching all or part of the claimed invention, as well as the context of the passage as taught by the prior art disclosed by the Examiner.
In the case of amending the claimed invention, Applicant is respectfully requested to indicate the portion(s) of the specification which dictate(s) the structure relied on for proper interpretation and also to verify and ascertain the metes and bounds of the claimed invention.
Allowable Subject Matter
Claims 5 – 14 are objected to as being dependent upon a rejected base claim but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
The following is a statement of reasons for the indication of allowable subject matter:
The primary reason for the indication of the allowability of claim 5 is the inclusion therein, in combination as currently claimed as a whole, of the limitation of “…wherein the start-up control part includes: a third NMOS transistor connected in the form of a diode between the first node and the second node”.
The primary reason for the indication of the allowability of claim 8 is the inclusion therein, in combination as currently claimed as a whole, of the limitation of “…, wherein the beta-multiplier reference circuit further includes: a third PMOS transistor configured to be controlled by an output of the comparator and connected between the second NMOS transistor and the second PMOS transistor”.
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure:
US Pub. No. 2008/0122526 A1 (Chung) discloses a device and method for starting a low supply bandgap reference circuit.
US Pub. No. 2017/0230044 A1 (Kajita) discloses a startup circuit for supplying a startup current to a constant current circuit for generating a constant current when starting the supply of a power supply voltage.
US Pub. No. 2003/0067291 A1 (Hong) discloses a bandgap reference voltage generator circuit.
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/ULARISLAO CORDOVA/Examiner, Art Unit 2838
/FRED E FINCH III/Primary Examiner, Art Unit 2838
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