DETAILED ACTION
Notice of Pre-AIA or AIA Status
1. The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
In the response to this Office action, the Office respectfully requests that support be shown for language added to any original claims on amendment and any new claims. That is, indicate support for newly added claim language by specifically pointing to page(s) and line numbers in the specification and/or drawing figure(s). This will assist the Office in prosecuting this application.
The Office has cited particular figures, elements, paragraphs and/or columns and line numbers in the references as applied to the claims for the convenience of the applicant. Although the specified citations are representative of the teachings in the art and are applied to the specific limitations within the individual claim, other passages and figures may apply as well. It is respectfully requested from the applicant, in preparing the responses, to fully consider each of the cited references in entirety as potentially teaching all or part of the claimed invention, as well as the context of the passage disclosed by the Office.
Information Disclosure Statement
2. The information disclosure statement (IDS) submitted on 08/20/2025 is being considered by the Examiner.
Disposition of the Claims
3. The instant application was effectively filed on May 23, 2024, wherein claims 1-8, 10-11 and 15-24 are currently pending.
EXAMINER’S NOTE: a review of the entire claims should be conducted to ensure all changes as suggested below are incorporated and reflects the entire claims presented without adding any new matter. Applicant's cooperation is requested in correcting any errors of which Applicant may become aware in the claims.
Claim Objections
4. Claims 1-8, 10-11 and 15-24 are objected to because of the following informalities:
1. (Original) A pixel circuit, comprising a pixel driving circuit, a light-emitting element, and a test switch circuit, wherein a control terminal of the test switch circuit is electrically connected to a test control terminal; the test switch circuit is disposed between a first test terminal and a second test terminal, and is utilized for, under control of a test control signal provided by the test control terminal, controlling the first test terminal and the second test terminal to be connected or disconnected from each other; the pixel driving circuit is electrically connected to the first test terminal, the second test terminal, and the light-emitting element, and is utilized for generating a drive current for driving the light-emitting element; and the first test terminal is electrically connected to a first direct current voltage line, and the first test terminal is electrically connected to a second direct current voltage line or a test node; or the first test terminal is electrically connected to a direct current voltage line, and the second test terminal is electrically connected to a data line.
2. (Original) The pixel circuit according to claim 1, wherein the pixel driving circuit comprises a driving circuit and a driving control circuit; a control terminal of the driving circuit is electrically connected to a first node; a first terminal of the driving circuit is electrically connected to a first test node, a second terminal of the driving circuit is electrically connected to the light-emitting element, and the driving circuit is utilized for generating a drive current under control of a potential of the first node; and the driving control circuit is utilized for controlling the control terminal of the driving circuit and the first terminal of the driving circuit to be connected to each other in response to the test switch circuit controlling the first test terminal and the second test terminal to be connected to each other.
3. (Original) The pixel circuit according to claim 2, wherein the first test terminal is electrically connected to a reference voltage line, and the second test terminal is electrically connected to a power voltage line; or the first test terminal is electrically connected to an initial voltage line, and the second test terminal is electrically connected to the data line; or the first test terminal is electrically connected to a reference voltage line, and the second test terminal is electrically connected to the first test node; or the first test terminal is electrically connected to an initial voltage line, and the second test terminal is electrically connected to a second test node.
4. (Original) The pixel circuit according to claim 1, wherein the test switch circuit comprises a test switch transistor; and a gate electrode of the test switch transistor is electrically connected to the test control terminal, a first electrode of the test switch transistor is electrically connected to the first test terminal, and a second electrode of the test switch transistor is electrically connected to the second test terminal.
5. (Original) The pixel circuit according to claim 3, wherein the driving control circuit comprises a first light-emitting control circuit, a data write circuit, a first reset circuit, and a second reset circuit; the first light-emitting control circuit is electrically connected to a first light-emitting control line, the power voltage line, and the first terminal of the driving circuit, and is utilized for, under control of a first light-emitting control signal provided by the first light-emitting control line, controlling the power voltage line and the first terminal of the driving circuit to be connected or disconnected from each other; the data write circuit is electrically connected to a scan line, the data line, and a write node, and is utilized for, under control of a scan signal provided by the scan line, controlling the data line and the write node to be connected or disconnected from each other; the second test node is electrically connected to the write node; the write node is electrically connected to the first node; the first reset circuit is electrically connected to a first reset control line, the reference voltage line, and the first node, and is utilized for, under control of a first reset control signal provided by the first reset control line, controlling the reference voltage line and the first node to be connected or disconnected from each other; the second reset circuit is electrically connected to a second reset control line, the initial voltage line, and a reset node, and is utilized for, under control of a second reset control signal provided by the second reset control line, controlling the initial voltage line and the reset node to be connected or disconnected from each other; and the reset node is electrically connected to the second terminal of the driving circuit.
6. (Original) The pixel circuit according to claim 5, further comprising a first energy-storage circuit and a second energy-storage circuit, wherein the first energy-storage circuit is electrically connected to the first node and the second terminal of the driving circuit, and is utilized for storing electric energy; and the second energy-storage circuit is electrically connected to the power voltage line and the second terminal of the driving circuit, and is utilized for storing electric energy.
7. (Original) The pixel circuit according to claim 5, further comprising a first energy-storage circuit, a second energy-storage circuit, and a third reset circuit, wherein the first energy-storage circuit is electrically connected to the write node and an intermediate node, and is utilized for storing electric energy; the second energy-storage circuit is electrically connected to the intermediate node and the second terminal of the driving circuit, and is utilized for storing electric energy; and the third reset circuit is electrically connected to a third reset control line, the reference voltage line, and the intermediate node, and is utilized for, under control of a third reset control signal provided by the third reset control line, controlling the reference voltage line and the intermediate node to be connected or disconnected from each other.
8. (Currently amended) The pixel circuit according to claim 7, further comprising a switch control circuit, wherein the first node is electrically connected to the write node through the switch control circuit; and a control terminal of the switch control circuit is electrically connected to a switch control line, and the switch control circuit is utilized for, under control of a switch control signal provided by the switch control line, controlling the first node and the write node to be connected or disconnected from each other; wherein the switch control circuit comprises a sixth transistor; and a gate electrode of the sixth transistor is electrically connected to the switch control line, a first electrode of the sixth transistor is electrically connected to the first node, and a second electrode of the sixth transistor is electrically connected to the write node; and/or, further comprising a second light-emitting control circuit, wherein the reset node is electrically connected to the second terminal of the driving circuit through the second light-emitting control circuit; the reset node is electrically connected to a first electrode of the light-emitting element, and a second electrode of the light-emitting element is electrically connected to a low voltage line; and a control terminal of the second light-emitting control circuit is electrically connected to a second light-emitting control line, and the second light-emitting control circuit is utilized for, under control of a second light-emitting control signal provided by the second light-emitting control line, controlling the reset node and the second terminal of the driving circuit to be connected or disconnected from each other; wherein the second light-emitting control circuit comprises a seventh transistor; and a gate electrode of the seventh transistor is electrically connected to the second light-emitting control line, a first electrode of the seventh transistor is electrically connected to the second terminal of the driving circuit, and a second electrode of the seventh transistor is electrically connected to the reset node; and/or, wherein the first energy-storage circuit comprises a first capacitor, and the second energy-storage circuit comprises a second capacitor; the third reset circuit comprises a fifth transistor; a first terminal of the first capacitor is electrically connected to the write node, and a second terminal of the first capacitor is electrically connected to the intermediate node; a first terminal of the second capacitor is electrically connected to the intermediate node, and a second terminal of the second capacitor is electrically connected to the second terminal of the driving circuit; and a gate electrode of the fifth transistor is electrically connected to the third reset control line, a first electrode of the fifth transistor is electrically connected to the reference voltage line, and a second electrode of the fifth transistor is electrically connected to the intermediate node.
10. (Original) The pixel circuit according to claim 5, wherein the driving circuit comprises a driving transistor, the first light-emitting control circuit comprises a first transistor, the data write circuit comprises a second transistor, the first reset circuit comprises a third transistor, and the second reset circuit comprises a fourth transistor; a gate electrode of the driving transistor is electrically connected to the first node, a first electrode of the driving transistor is electrically connected to the first test node, and a second electrode of the driving transistor is electrically connected to the light-emitting element; a gate electrode of the first transistor is electrically connected to the first light-emitting control line, a first electrode of the first transistor is electrically connected to the power voltage line, and a second electrode of the first transistor is electrically connected to the first electrode of the driving transistor; a gate electrode of the second transistor is electrically connected to the scan line, a first electrode of the second transistor is electrically connected to the data line, and a second electrode of the second transistor is electrically connected to the write node; a gate electrode of the third transistor is electrically connected to the first reset control line, a first electrode of the third transistor is electrically connected to the reference voltage line, and a second electrode of the third transistor is electrically connected to the first node; and a gate electrode of the fourth transistor is electrically connected to the second reset control line, a first electrode of the fourth transistor is electrically connected to the initial voltage line, and a second electrode of the fourth transistor is electrically connected to the reset node.
11. (Original) The pixel circuit according to claim 6, wherein the first energy-storage circuit comprises a first capacitor, and the second energy-storage circuit comprises a second capacitor; a first terminal of the first capacitor is electrically connected to the first node, and a second terminal of the first capacitor is electrically connected to the second terminal of the driving circuit; and a first terminal of the second capacitor is electrically connected to the power voltage line, and a second terminal of the second capacitor is electrically connected to the second terminal of the driving circuit.
15. (Currently amended) A pixel circuit test method, applied to the pixel circuit according to claim 1, wherein the method comprises: in a detection phase, providing a valid test control signal to the test control terminal, and controlling, by the test switch circuit under control of the test control signal, the first test terminal and the second test terminal to be connected to each other.
16. (Original) The pixel circuit test method according to claim 15, wherein the method further comprises: in a display phase, providing an invalid test control signal to the test control terminal, controlling, by the test switch circuit under control of the test control signal, the first test terminal and the second test terminal to be disconnected from each other, and generating, by the pixel driving circuit, the drive current for driving the light-emitting element.
17. (Currently amended) The pixel circuit test method according to claim 15, wherein the pixel driving circuit comprises the driving circuit and a driving control circuit; and the method comprises: in the detection phase, controlling, by the driving control circuit, the control terminal of the driving circuit and the first terminal of the driving circuit to be connected to each other.
18. (Currently amended) A display apparatus, comprising the pixel circuit according to any one of claim 1.
19. (Original) A display panel, comprising pixel circuits in a plurality of rows and a plurality of columns, a plurality of first direct current voltage lines, and a plurality of second direct current voltage lines, wherein the pixel circuits are disposed in a display area; the display panel further comprises a test switch module disposed in a bezel area; the test switch module comprises a plurality of test switch circuits; and each of the test switch circuits is electrically connected to a test control terminal, one of the first direct current voltage lines, and one of the second direct current voltage lines, and is utilized for, under control of a test control signal provided by the test control terminal, controlling the first direct current voltage line and the second direct current voltage line to be connected or disconnected from each other.
20. (Original) The display panel according to claim 19, wherein the first direct current voltage lines and the second direct current voltage lines all extend in a first direction; the display panel comprises N rows of pixel circuits; the pixel circuits located in an nth row are electrically connected to an nth first direct current voltage line of the first direct current voltage lines and an nth second direct current voltage line of the second direct current voltage lines; N is an integer greater than 1, and n is a positive integer less than or equal to N; the test switch module comprises N test switch circuits; and an nth test switch circuit of the test switch circuits is electrically connected to an nth test control terminal, the nth first direct current voltage line, and the nth second direct current voltage line, and is utilized for, under control of an nth test control signal provided by the nth test control terminal, controlling the nth first direct current voltage line and the nth second direct current voltage line to be connected or disconnected from each other.
21. (Original) The display panel according to claim 19, comprising N rows of pixel circuits, wherein the pixel circuits located in an nth row are electrically connected to an nth first direct current voltage line of the first direct current voltage lines and an nth second direct current voltage line of the second direct current voltage lines; N is an integer greater than 1, and n is a positive integer less than or equal to N; m is a positive integer less than N; the test switch module comprises at least one test switch circuit; and an mth test switch circuit of the test switch circuits is electrically connected to an mth test control terminal, an mth first direct current voltage line of the first direct current voltage lines, and an (m+1)th second direct current voltage line of the second direct current voltage lines, and is utilized for, under control of an mth test control signal provided by the mth test control terminal, controlling the mth first direct current voltage line and the (m+1)th second direct current voltage line to be connected or disconnected from each other.
22. (Original) The display panel according to claim 19, wherein the first direct current voltage lines comprise a plurality of rows of first direct current voltage line portions and a plurality of columns of second direct current voltage line portions that are electrically connected to each other, and the second direct current voltage lines comprise a plurality of rows of third direct current voltage line portions and a plurality of columns of fourth direct current voltage line portions that are electrically connected to each other; an extension direction of the first direct current voltage line portions is the same as an extension direction of the third direct current voltage line portions, an extension direction of the second direct current voltage line portions is the same as an extension direction of the fourth direct current voltage line portions, and the extension direction of the first direct current voltage line portions intersects the extension direction of the second direct current voltage line portions; the test switch module comprises a plurality of first test switch circuits and a plurality of second test switch circuits; each of the first test switch circuits is electrically connected to a corresponding test control terminal, one row of the first direct current voltage line portions, and one row of the third direct current voltage line portions, and is utilized for, under control of the test control signal provided by the test control terminal, controlling the row of the first direct current voltage line portions and the row of the third direct current voltage line portions to be connected or disconnected from each other; and each of the second test switch circuits is electrically connected to a corresponding test control terminal, one column of the second direct current voltage line portions, and one column of the fourth direct current voltage line portions, and is utilized for, under control of the test control signal provided by the test control terminal, controlling the column of the second direct current voltage line portions and the column of the fourth direct current voltage line portions to be connected or disconnected from each other.
23. (Original) A display panel, comprising pixel circuits in a plurality of rows and A columns, a plurality of third direct current voltage lines, and data lines in A columns, wherein A is an integer greater than 1; a is a positive integer less than or equal to A; the pixel circuits are disposed in a display area; the pixel circuits located in an ath column are electrically connected to the data line in the ath column; the display panel further comprises a test switch module disposed in a bezel area; the test switch module comprises A test switch circuits; and an ath test switch circuit of the test switch circuits is electrically connected to an ath test control terminal, one of the third direct current voltage lines, and the data line in the ath column, and is utilized for, under control of an ath test control signal provided by the ath test control terminal, controlling the third direct current voltage line and the data line in the ath column to be connected or disconnected from each other.
24. (Currently amended) A display apparatus, comprising the display panel according to claim 19.
Appropriate correction is required.
Claim Rejections - 35 USC § 112
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claims 1-8, 10-11 and 15-18 are rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention.
Regarding claim 1, the phrase " the first test terminal is electrically connected to a first direct current voltage line, and the first test terminal is electrically connected to a second direct current voltage line or a test node" renders the claim indefinite because ithe claimed first test terminal cannot be electrically connected to two different direct current voltage line at the same time. See MPEP § 2173.05(d).
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claim(s) 1, 4 and 18 is/are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Koo et al. US PG-PUB 20230095094 A1 (hereinafter Koo).
Regarding claim 1, Koo teaches A pixel circuit (Fig. 4; 110), comprising a pixel driving circuit (Fig. 4; pixel circuit 110 comprises pixel transistor P-TR which includes driving transistor T6), a light-emitting element (Fig. 4; LED), and a test switch circuit (Fig. 4; T-TR), wherein a control terminal of the test switch circuit is electrically connected to a test control terminal (Fig. 4; gate of T-TR 701 is connected to test signal TGS); the test switch circuit is disposed between a first test terminal and a second test terminal (Fig. 4; test transistor T-TR is disposed between test source terminal 702 and test source terminal 703), and is used for, under control of a test control signal provided by the test control terminal, controlling the first test terminal and the second test terminal to be connected or disconnected from each other (Fig. 4 and Para. [0081]; The test transistor T-TR may be turned on or off in response to the test signal TGS provided to the test gate terminal 701. In addition, the test source voltage V1′ may be provided to the test source terminal 702. Accordingly, the test part 700 including the test transistor T-TR may perform the array test); the pixel driving circuit is electrically connected to the first test terminal, the second test terminal, and the light-emitting element, and is used for generating a drive current for driving the light-emitting element (Fig. 4 and Para. [0096]; The sixth transistor T6 may transmit the driving current to a light emitting diode LED); the first test terminal is electrically connected to a direct current voltage line (Fig. 4; terminal 702 is connected to voltage V1), and the second test terminal is electrically connected to a data line (Fig. 4; terminal 703 is connected to vdata).
Examiner notes: due to the “OR” statement, patentable weight is not given to claimed limitation “the first test terminal is electrically connected to a first direct current voltage line, and the first test terminal is electrically connected to a second direct current voltage line or a test node”
Regarding claim 4, Koo teaches The pixel circuit according to claim 1, Koo further teaches wherein the test switch circuit comprises a test switch transistor; and a gate electrode of the test switch transistor is electrically connected to the test control terminal, a first electrode of the test switch transistor is electrically connected to the first test terminal, and a second electrode of the test switch transistor is electrically connected to the second test terminal (See Fig. 4; transistor T-TR).
Regarding claim 18, Koo further teaches A display apparatus, comprising the pixel circuit according to claim 1 (See Para. [0066]).
Allowable Subject Matter
5. Claims 2-3, 5-8, 10-11, 15-17, 20-22 and 24 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims as well as overcome rejection under 35 USC 112b and claim objections as detailed above.
Claims 19 and 23 are objected to but would be allowed once claim objection as detailed above is overcomed.
Regarding claim 19, none of the references cited either alone or in any obvious combination teaches and/or suggests “a plurality of first direct current voltage lines, and a plurality of second direct current voltage lines, the display panel further comprises a test switch module disposed in a bezel area; the test switch module comprises a plurality of test switch circuits; each of the test switch circuits is electrically connected to a test control terminal, one of the first direct current voltage lines, and one of the second direct current voltage lines, and is used for, under control of a test control signal provided by the test control terminal ”
Regarding claim 23, none of the references cited either alone or in any obvious combination teaches and/or suggests “a plurality of third direct current voltage lines, and data lines in A columns, wherein A is an integer greater than 1; a is a positive integer less than or equal to A; the pixel circuits are disposed in a display area; the pixel circuits located in an ath column are electrically connected to the data line in the ath column; the display panel further comprises a test switch module disposed in a bezel area; the test switch module comprises A test switch circuits; and an ath test switch circuit of the test switch circuits is electrically connected to an ath test control terminal, one of the third direct current voltage lines, and the data line in the ath column, and is used for, under control of an ath test control signal provided by the ath test control terminal, controlling the third direct current voltage line and the data line in the ath column to be connected or disconnected from each other”.
Conclusion
6. Any inquiry concerning this communication or earlier communications from the examiner should be directed to AMY ONYEKABA whose telephone number is (571)270-7633. The examiner can normally be reached on 9-5.
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If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, NITIN K PATEL can be reached on 5712727677. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/AMY ONYEKABA/
Primary Examiner, Art Unit 2628
Prosecution Insights