CTNF 19/107,813 CTNF 93330 DETAILED ACTION 07-03-aia AIA 15-10-aia The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA. This Action is in response to communications filed 02/28/2025. The Examiner acknowledges the Preliminary amendments filed on 02/28/2025 Claims 1-25 are cancelled. Claims 26-45 are newly added. Claims 26-45 are pending. Claims 26-45 are rejected. Priority Applicant’s priority claim as a 371 National Stage entry of foreign document PCT/CN2022/123674 filed 10/02/2022 is herein acknowledged. 02-26 AIA Receipt is acknowledged of certified copies of papers required by 37 CFR 1.55. Information Disclosure Statement As required by M.P.E.P. 609(C), the applicant’s submission of the Information Disclosure Statement dated 02/28/2025 is acknowledged by the examiner and the cited references have been considered in the examination of the claims now pending. As required by M.P.E.P 609 C(2), a copy of the PTOL-1449 initialed and dated by the examiner is attached to the instant office action. Drawings The applicant’s drawings submitted on 02/28/2025 are acceptable for examination purposes. Claim Rejections - 35 USC § 112 07-30-02 AIA The following is a quotation of 35 U.S.C. 112(b): (b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention. The following is a quotation of 35 U.S.C. 112 (pre-AIA), second paragraph: The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention. 07-34-01 AIA Claim s 26-34 and 36 are rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor, or for pre-AIA the applicant regards as the invention. Claim 26 recites “wherein the response to the distributed address translation request identifies that a second physical memory address of a second physical memory…” Herein the “second physical memory” lacks proper antecedent basis with respect to the prior recitation in the “a second portion of the virtual address space is mapped to a second physical memory of a second processor device.” Claims 27-34 do not resolve the issue. Claim 31 recites “wherein a first portion of virtual addresses … a second portion of virtual addresses”. Herein the recitation of “first portion” and “second portion” lack proper antecedent basis with respect to the recited portions in claim 26. Furthermore, Claim 31 recites “wherein physical memory of the processor is mapped to the first portion of virtual addresses, and physical memory of the second processor is mapped…” Herein the recitations of “physical memory” are unclear and lack proper antecedent basis. Specifically, claim 26, from which claim 31 depends, already recites “first physical memory” and “second physical memory” according to the first and second processor devices. Herein the recitations of “processor” and “second processor” also lack proper antecedent with respect to the previously identified “first processor device” and “second processor device” as recited in claim 26. Claims 32-33 do not resolve the issue. Claim 36 recites “receiving … a request to translate a second virtual address” which lacks proper distinction from the “request” as recited in claim 35 which refers to a first virtual address. Appropriate correction is required. Claim Rejections - 35 USC § 102 07-07-aia AIA 07-07 The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action: A person shall be entitled to a patent unless – 07-08-aia AIA (a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention. 07-12-aia AIA (a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention. 07-15 AIA Claim s 37-38 are rejected under 35 U.S.C. 102( a)(1 ) as being anticipated by Burns et al. (US 11,455,247) . Regarding claim 37, Burns teaches a system comprising: a first processing unit comprising: processing circuitry; first physical memory; memory management circuitry to maintain a first page table corresponding to virtual memory of a program ([Col. 4 ln. 6-11] Controller 100 may run on local device 101, and may provide one or more applications running on local device 101 with a virtual memory address space that spans and seamlessly accesses different allocations of physical memory from each of local device 101 and remote device 103. [Col. 6 ln. 58-62] In some embodiments, controller 100 may perform the address translation based on a paging table that is maintained by one or more of controller 100, a memory management unit (“MMU”) of local device 101, or the OS of local device 101.) ; and a second processing unit comprising: processing circuitry; second physical memory; memory management circuitry to maintain a second page table corresponding to the virtual memory of the program ([Col. 3 ln. 13-21] Remote device 103 may be a disaggregated memory device that operates independent of and separate from local device 101. Specifically, an application may run directly on local device 101 using processing and other resources of local device 101 and may be controlled by the OS of local device 101. However, controller 100 may allow the application to access additional RAM or memory resources from remote device 103 via an interconnect fabric that connects local device 101 to remote device 103.) , wherein a first portion of virtual addresses of the virtual memory are mapped to physical addresses of the first physical memory and a second portion of virtual addresses of the virtual memory are mapped to physical addresses of the second physical memory ([Col. 4 ln. 6-16] Controller 100 may run on local device 101, and may provide one or more applications running on local device 101 with a virtual memory address space that spans and seamlessly accesses different allocations of physical memory from each of local device 101 and remote device 103. In particular, controller 100 may control the allocation of memory from local device 101 and remote device 103 to a particular application, and may control the swapping of pages containing data used by the particular application between the memories allocated from the two separate devices 101 and 103.) . Herein Burns teaches a distributed storage configuration wherein memory from a local device and memory from at least a remote device are allocated to the virtual memory address space of an application executing on the local device. Each of the devices maintain respective paging tables for tracking address translations to determine which requests virtual memory address maps to the corresponding device physical memory address. The distributed memory allocation provides increased storage performance across the plurality of devices. In this manner, it is determined that Burns fully teaches the limitations as currently recited. Regarding claim 38, Burns further teaches the system of Claim 37, wherein the memory management circuitry of the first processing unit comprises: address translation server circuitry to handle queries of the first portion of the virtual addresses; and address translation client circuitry to query the second processing unit for virtual address mappings for the second portion of virtual addresses ([Col. 3 ln. 49-54] Controller 100 may communicate with the processor and/or memory management software of remote device 103, and may directly access the physical memory of remote device 103 using different lightweight, low latency, and high-speed interconnect fabrics and/or transport mechanisms.) . Herein the responsibilities of handling queries are demonstrated by the controller circuitry of the local device. As it is previously indicated that the remote devices operate independently of the local device, it is presented that each device comprises circuitry capable of performing the querying functions from other respective remote devices . Claim Rejections - 35 USC § 103 07-20-aia AIA The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action: A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102 of this title, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made. 07-23 AIA The factual inquiries set forth in Graham v. John Deere Co. , 383 U.S. 1, 148 USPQ 459 (1966), that are applied for establishing a background for determining obviousness under 35 U.S.C. 103(a) are summarized as follows: 1. Determining the scope and contents of the prior art. 2. Ascertaining the differences between the prior art and the claims at issue. 3. Resolving the level of ordinary skill in the pertinent art. 4. Considering objective evidence present in the application indicating obviousness or nonobviousness. 07-21-aia AIA Claim s 26-31 and 34-36 are rejected under 35 U.S.C. 103 as being unpatentable over Burns in view of Klein et al. (US 2017/0046277) . Regarding claim 26, Burns discloses, in the italicized portions, an apparatus comprising: a first processor device; first physical memory to store a page table associated with a virtual address space of a process, wherein a first portion of the virtual address space is mapped to the first physical memory and a second portion of the virtual address space is mapped to a second physical memory of a second processor device ([Col. 4 ln. 6-16] Controller 100 may run on local device 101, and may provide one or more applications running on local device 101 with a virtual memory address space that spans and seamlessly accesses different allocations of physical memory from each of local device 101 and remote device 103. In particular, controller 100 may control the allocation of memory from local device 101 and remote device 103 to a particular application, and may control the swapping of pages containing data used by the particular application between the memories allocated from the two separate devices 101 and 103.) ; a memory management unit comprising ([Col. 6 ln. 58-62] In some embodiments, controller 100 may perform the address translation based on a paging table that is maintained by one or more of controller 100, a memory management unit (“MMU”) of local device 101, or the OS of local device 101.) : an address translation client to: send a distributed address translation request to a second processor device, wherein the distributed address translation request identifies a second virtual memory address associated with the process; receive a response to the distributed address translation request, wherein the response to the distributed address translation request identifies that a second physical memory address of a second physical memory associated with the second processor device is mapped to the second virtual memory address ([Col 6 ln. 63 – Col. 7 ln. 2] Process 300 may include retrieving (at 310) the requested page from the mapped physical memory address of remote device 103 using RDMA or another transport mechanism over an interconnect fabric that connects local device 101 to remote device 103. Remote device 103 may read the requested page from the mapped physical memory address, and may return the requested page to controller 100.) ; and add a mapping of the second virtual memory address to the second physical memory address in the page table. Herein Burns discloses a system comprising distributed storage wherein portions of memory of remote devices may be allocated to a virtual address space of an application on a local device and collectively used for access by the application. As part of the shared storage system, when requests for data cannot be serviced locally, the request is then transmitted to a remote device for data retrieval. Burns does not explicitly disclose sending a translation request to a second processor device with the identified second virtual memory address and adding a mapping of the second virtual memory address to the second physical memory address to the page table. Regarding these aspects of the limitations, Klein discloses in Paragraphs [0052-53] “[0052] According to one embodiment, the method further comprises in response to receiving by the MMU a request of a second data block via a second virtual address, determining that a second entry of the entries corresponds to the second virtual address, the second entry comprising a second physical address of the second data block, and using the second physical address for accessing the second data block. This embodiment may have the advantage to be seamlessly integrated in the existing systems having entries encoded with a structure different from the structure of the added entry (of each data block of the first set of the data blocks). [0053] According to one embodiment, the execution of the program instruction further causes the processor to add entries in the page table, wherein entries comprise information indicating physical addresses.” Herein Klein explicitly discloses use of an access request for a second memory block via a second virtual address which is then accessed by the corresponding MMU which translates the second virtual address to a second physical address and returns the data. Furthermore, Klein notes the processor may then add entries to the page table including the physical addresses corresponding to the execution of the program. In this manner, it would be obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to maintain updated page tables of translation mappings according to process execution in order to improve access performance (Klein [0050]). Burns and Klein are analogous art because they are from the same field of endeavor of managing address translation services. Regarding claim 27, Burns and Klein further disclose the apparatus of Claim 26, wherein the memory management unit further comprises: an address translation server to: receive a request to translate a first virtual memory address in the first portion of the virtual address space into a physical address of the first physical memory; determine, from the page table, a mapping of the first virtual memory address to a first physical memory address of the first physical memory; and return the first physical memory address as a response to the request (Burns [Col. 6 ln. 58-62] and Klein [0030]) . Herein both Burns and Klein disclose use of a page table to translate virtual addresses to generate physical addresses. Regarding claim 28, Burns further discloses the apparatus of Claim 26, wherein the first physical memory address addresses a first page of data within the first physical memory, and the second physical memory address addresses a second page of data within the second physical memory ([Col 2 ln. 23-30] Moreover, the controller may expand the virtual address space of the applications, and perform the dynamic mapping and transfer of data from addresses in the virtual address space to addresses in the physical memories of the local device and the remote disaggregated memory device without modifying the applications, the memory management system of the local device, or the operating system (“OS”) of the local device.) . Herein Burns discloses that data is accessed from the disaggregated memory from the translated virtual addresses to respective physical addresses. Regarding claim 29, Burns further discloses the apparatus of Claim 26, wherein the first processor device and the second processor device are interconnected in a distributed computing architecture, and virtual memory for the computing architecture is distributed between memory of at least the first processor device and the second processor device ([Col 2 ln. 66- Col. 3 ln. 1] Local device 101 may include a server, host, and/or another computing node with local or onboard processing, memory, storage, networking, and/or other resources. [Col. 2 ln. 13-21] Remote device 103 may be a disaggregated memory device that operates independent of and separate from local device 101. Specifically, an application may run directly on local device 101 using processing and other resources of local device 101 and may be controlled by the OS of local device 101. However, controller 100 may allow the application to access additional RAM or memory resources from remote device 103 via an interconnect fabric that connects local device 101 to remote device 103.) . Herein Burns discloses the disaggregated memory system used in combination over a networked connection for distributing processing. Regarding claim 30, Burns further discloses the apparatus of Claim 29, wherein the distributed computing architecture comprises pooled memory shared within the distributed computing architecture, and the memory of the first processor device comprises the first physical memory and at least a portion of the pooled memory ([Col 2 ln. 66- Col. 3 ln. 1] Local device 101 may include a server, host, and/or another computing node with local or onboard processing, memory, storage, networking, and/or other resources. [Col. 2 ln. 13-21]) . As similarly presented in the rejection of claim 29, the disaggregated memory between the devices is shared and a local device utilizes a portion of local memory in addition to portions of memory of remote devices for allocation to virtual address spaces. Regarding claim 31, Burns further discloses the apparatus of Claim 26, wherein the first processor device is associated with a first region of virtual address space of the process and the second processor device is associated with a second region of virtual address space of the process, wherein a first portion of virtual addresses in the virtual address space of the process are included in the first region, a second portion of virtual addresses in the virtual address space of the process are included in the second region, wherein physical memory of the processor is mapped to the first portion of virtual addresses, and physical memory of the second processor is mapped to the second portion of virtual addresses ([Col. 4 ln. 6-16]) . Herein, as previously indicated, Burns discloses allocation of both local and remote device memory to a virtual address space. In this manner, the local device is considered as the first processor device associated with the first portion of virtual addresses and the remote device is associated with the second portion of virtual addresses. As noted by Burns, the association may be applied to a plurality of remote devices as determined to be allocated to the virtual address space. Regarding claim 34, Burns further discloses the apparatus of Claim 26, wherein the distributed address translation request comprises a first packet based on a Peripheral Component Interconnect Express (PCIe)-based protocol, and the response to the distributed address translation request comprises a second packet based on the PCIe-based protocol ([Col. 3 ln. 61-65] In some embodiments, the interconnect fabrics may include Ethernet, InfiniBand, Fibre Channel, Peripheral Component Interconnect express (“PCIe”), and/or other communication or networking interfaces for connecting different components or computing devices.) . Herein Burns discloses the interconnect between devices may include PCIe among other formats. Therefore, any communication along this type of network would be packetized according to the respective format. Regarding claim 35, Burns discloses, in the italicized portions, a method comprising: identifying that a first processor device is associated with a first region of virtual memory of a process and that a second processor device is associated with a second region of the virtual memory of the process, wherein a first portion of virtual addresses are included in the first region and a second portion of virtual addresses are included in the second region ([Col. 7 ln. 3-21] Process 300 may include performing (at 312) a memory transfer to load the requested page retrieved from the physical memory of remote device 103 into the physical memory from local device 101 that is allocated for the particular application. In some embodiments, loading (at 312) the retrieved page may include responding to the page fault notification by notifying the kernel or OS that the page has been retrieved and is available for access from the physical memory of local device 101. Controller 100, the OS, or the MMU may update a paging table to identify the memory address within the physical memory of local device 101 where the page is stored. More specifically, the paging table may be modified so that the virtual address for the requested page points to a physical memory address of local device 101 where the requested page is now stored instead of a physical memory address of remote device 103 where the requested page was retrieved and transferred into the physical memory of local device 101.) ; sending a request from the first processor device to the second processor device to translate a first virtual address in the virtual memory, wherein the first virtual address is included in the second region, and the request is sent to the second processor based on identifying the second process is associated with the second region; receiving a response to the request, wherein the response identifies that a first physical address of the second processor device is mapped to the first virtual address ([Col 6 ln. 63 – Col. 7 ln. 2] Process 300 may include retrieving (at 310) the requested page from the mapped physical memory address of remote device 103 using RDMA or another transport mechanism over an interconnect fabric that connects local device 101 to remote device 103. Remote device 103 may read the requested page from the mapped physical memory address, and may return the requested page to controller 100.) ; updating a page table of the first processor device based on the response, wherein the page table comprises local entries and remote entries, the local entries map virtual addresses in the first region to physical addresses in physical memory of the first processor device, and the remote entries map regions of the virtual memory to physical addresses in addresses of other processor devices in a system, wherein the other processor devices comprise the second processor device ([Col. 7 ln. 3-21]) . Herein Burns discloses a system comprising distributed storage wherein portions of memory of remote devices may be allocated to a virtual address space of an application on a local device and collectively used for access by the application. As part of the shared storage system, when requests for data cannot be serviced locally, the request is then transmitted to a remote device for data retrieval. Burns does not explicitly disclose sending a translation request to a second processor device with the identified second virtual memory address and updating the page table of the first process device in response. Regarding these aspects of the limitations, Klein discloses in Paragraphs [0052-53] use of an access request for a second memory block via a second virtual address which is then accessed by the corresponding MMU which translates the second virtual address to a second physical address and returns the data. Furthermore, Klein notes the processor may then add entries to the page table including the physical addresses corresponding to the execution of the program. Claim 35 is rejected on a similar basis as claim 26. Regarding claim 36, Burns and Klein in combination further disclose the method of Claim 35, further comprising: receiving, from the second processor device at the first processor device, a request to translate a second virtual address, wherein the second virtual address is included in the first region; determining, at the first processor device, from the page table, that the second virtual address maps to a second physical address in physical memory of the first processor device ([Col. 4 ln. 6-16] and [Col 6 ln. 63 – Col. 7 ln. 2]) ; sending, from the first processor device to the second processor device, a translation response to the request to translate the second virtual address, wherein the translation response identifies that the second virtual address maps to the second physical address, wherein the translation response is for use in updating a page table of the second processor device (Klein [0052-53]) . In a similar fashion to the rejection of claim 35 wherein the local device performs a translation request to the remote device, it would be obvious to one of ordinary skill in the art that the configuration wherein said local device is the relative remote device to the application executing on the remote device, then the similar steps may be performed for requesting and receiving the translation response as identified . 07-21-aia AIA Claim s 32-33 are rejected under 35 U.S.C. 103 as being unpatentable over Burns in view of Klein and further in view of Talagala et al. (US 2013/0212321) . Regarding claim 32, Burns and Klein do not explicitly disclose the apparatus of Claim 31, wherein the address translation client is further to: send a region query for the virtual address space of the process; and receive a region assignment listing, wherein the region assignment listing identifies a plurality of regions of the virtual address space of the process and maps a plurality of processors in a system to respective regions in the plurality of regions, wherein the first processor device and second processor device are included in the plurality of processors, and the first region and the second region are included in the plurality of regions, wherein the distributed translation request is sent to the second processor device based on the region assignment listing . Regarding these limitations, Talagala discloses in Paragraph [0237] “The populate module 1905 may transfer data between address spaces by preserving, adding, updating, and/or changing a logical-to-physical mapping for transferred data in a mapping structure, index, forward map, or the like as described above with regard to the metadata 1051 and/or forward index 1053 maintained by the SML 1050. For example, to transfer data from an address space of the non-volatile memory media 1110 to an address space of the ACM 1011, 1111 in response to a populate request to transfer the data into the ACM 1011, 1111, the populate module 1905 may remove an entry for the data from a forward index 1053 or other mapping structure for the non-volatile memory media 1110 and add an entry for the data in an index or other mapping structure for the ACM 1011, 1111.” Herein Talagala discloses a distributed storage system which uses a populate module 1905 to maintain a mapping structure. Specifically, a device in the system may transmit a populate command to update and access the mapping structure. This command is interpreted as analogous to the query command as claimed as the requestor receives access to the mapping structure which maintains virtual namespace assignment across the physical storage locations. In this manner, it would be obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to acquire updated mapping information prior to transmitting the translation request in order to determine the current allocation of addresses in the distributed storage system (Talagala [0235]). Burns, Klein, and Talagala are analogous art because they are from the same field of endeavor of managing address translation services. Regarding claim 33, Talagala further discloses the apparatus of Claim 32, wherein the system comprises a root complex, and the region request is sent to and the region assignment listing is received from the root complex ([0257] The communications bus 1040 may be in communication with the processor complex 1012 through a northbridge device, a root complex, or the like of the processor complex 1012.) . Herein Talagala discloses the PCI-e communication being routed through a root complex . 07-21-aia AIA Claim s 39-42 are rejected under 35 U.S.C. 103 as being unpatentable over Burns in view of Hamidouche et al. (US 2021/0191641) . Regarding claim 39, Burns discloses, in the italicized portions, the system of Claim 37, wherein the first processing unit and the second processing units are interconnected by a fabric in a distributed computing environment ([Col. 2 ln. 63-65] Local device 101 may be connected to remote device 103 via one or more interconnect fabrics) , and the first processing unit is of a different type than the second processing unit. Herein Burns notes the devices in the system are connected via one or more interconnect fabrics. Burns does not explicitly disclose that the processing units are of different types. Regarding this aspect of the limitation, Hamidouche discloses in Paragraph [0008] “In some embodiments, the first memory is a central processing unit (CPU) memory (hereinafter also referred to as “CPU memory”) primarily associated with a first processor (hereinafter also referred to as “CPU”)) and the second memory is a graphics processing unit (GPU) memory (hereinafter also referred to as “GPU memory”) primarily associated with a second processor or coprocessor (hereinafter also referred to as “GPU”).” Herein Hamidouche discloses in the context of a shared memory pool system, processing units of different types may share memory for virtual address spaces allocated to processes executing on each respective processing unit. In this manner, it would be obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to allocate memory from different devices to processing units of different types to improved shared memory utilization (Hamidouche [0008]). Burns and Hamidouche are analogous art because they are from the same field of endeavor of managing a shared memory pool. Regarding claim 40, Hamidouche further discloses the system of Claim 39, wherein the first processing unit comprises a central processing unit, and the second processing unit comprises one of a graphics processing unit, data processing unit, or an infrastructure processing unit ([0008]) . Herein Hamidouche explicitly discloses the respective memories belong to a CPU and GPU. Regarding claim 41, Burns does not explicitly disclose the system of Claim 37, wherein the program is to utilize the first processing unit and the second processing unit during execution . Regarding this aspect of the limitation, Hamidouche discloses in Paragraph [0011] “For ease of illustration, the following description refers frequently to implementations of a coprocessor as a GPU. However, the present disclosure is not limited to this example context, but instead is applicable to any of a variety of coprocessors, including application-specific integrated circuits (ASICs) for machine learning and artificial intelligence applications, and the like, using the guidelines provided herein. As such, reference to a GPU as the coprocessor also applies to other types of coprocessors unless explicitly indicated.” Herein Hamidouche discloses that the other processing unit functions as a coprocessor and therefore both processing units are involved in the execution of code. In this manner, it would be obvious to one of ordinary skill in the art before the effective filing date of the claimed invention in the context of coprocessors that both processing units are involved in instruction execution for distributed processing. Regarding claim 42, Hamidouche further discloses the system of Claim 41, wherein the program comprises one of a machine learning or artificial intelligence program ([0011]) . Herein Hamidouche explicitly discloses the processing units as being applicable for machine learning or artificial intelligence execution . 07-21-aia AIA Claim s 43-44 are rejected under 35 U.S.C. 103 as being unpatentable over Burns in view of Feehrer et al. (US 2021/0133123) . Regarding claim 43, Burns does not explicitly disclose the system of Claim 37, further comprising fabric-attached memory, wherein a portion of virtual addresses in the first portion of virtual addresses are mapped to physical addresses of the fabric-attached memory . Regarding this limitation, Feehrer discloses in Paragraph [0060] “Such access by one GPU of the local memory of another GPU may be “the same” (although not quite as fast), from the perspective of an application executing on the GPU originating the access, as if the GPU were accessing its own locally attached memory. Hardware within each GPU 102 and hardware within switch 104 provides necessary address translations to map virtual addresses used by the executing application into physical memory addresses of the GPU's own local memory and the local memory of one or more other GPUs. As explained herein, such peer-to-peer access is extended to fabric attached memory without the concomitant expense of adding further compute-capable GPUs.” Herein Feehrer discloses a shared memory system wherein a plurality of processing units are capable of allocating and accessing distributed memory including fabric attached memory. More specifically, it is identified that the virtual addresses are mapped to physical memory addresses of both local memory and memory local to other processing units. In this manner, it would be obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to allocate memory from different devices to processing units to improve shared memory utilization (Feehrer [0016]). Burns and Feehrer are analogous art because they are from the same field of endeavor of managing a shared memory pool. Regarding claim 44, Feehrer further discloses the system of Claim 43, wherein the fabric-attached memory comprises a pool of memory comprised of physical memory from a plurality of devices in the system ([0121] In accordance with another example non-limiting advantageous feature, a source GPU 102 can use the full inter-GPU communication bandwidth for accessing fabric attached memory by interleaving the fabric attached memory accesses across multiple donor fabric attached memories. The source GPU is thus able to “spray” (interleave) memory accesses across multiple links/interconnects of the fabric attached to it to access an attached memory pool via a plurality of donor memory controller hardware units.) . Herein Feehrer discloses the disaggregated memory from the donor hardware forms a fabric attached memory pool . 07-21-aia AIA Claim 45 is rejected under 35 U.S.C. 103 as being unpatentable over Burns in view of Talagala . Regarding claim 45, Burns does not explicitly disclose the system of Claim 37, wherein the second processing unit comprises host circuitry to: receive a region query from the first processing unit relating to the virtual memory of the program; identify a region mapping for the virtual memory of the program, wherein the region mapping identifies that physical memory of the first processing unit is to be mapped to the first portion of virtual addresses and that physical memory of the second processing unit is to be mapped to the second portion of virtual addresses; and return the region mapping to the first processing unit as a response to the region query . Regarding these limitations, Talagala discloses in Paragraph [0237] “The populate module 1905 may transfer data between address spaces by preserving, adding, updating, and/or changing a logical-to-physical mapping for transferred data in a mapping structure, index, forward map, or the like as described above with regard to the metadata 1051 and/or forward index 1053 maintained by the SML 1050. For example, to transfer data from an address space of the non-volatile memory media 1110 to an address space of the ACM 1011, 1111 in response to a populate request to transfer the data into the ACM 1011, 1111, the populate module 1905 may remove an entry for the data from a forward index 1053 or other mapping structure for the non-volatile memory media 1110 and add an entry for the data in an index or other mapping structure for the ACM 1011, 1111.” Herein Talagala discloses a distributed storage system which uses a populate module 1905 to maintain a mapping structure. Specifically, a device in the system may transmit a populate command to update and access the mapping structure. This command is interpreted as analogous to the query command as claimed as the requestor receives access to the mapping structure which maintains virtual namespace assignment across the physical storage locations. In this manner, it would be obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to acquire updated mapping information prior to transmitting the translation request in order to determine the current allocation of addresses in the distributed storage system (Talagala [0235]). Burns and Talagala are analogous art because they are from the same field of endeavor of managing address translation services . Conclusion 07-96 AIA The prior art made of record and not relied upon is considered pertinent to applicant's disclosure. Rao et al. (US 2014/0049548) – Paragraph [0028] wherein assigning virtual address spaces between processors to a shared memory pool is discussed . Borikar (US 2016/0085684) – Abstract wherein deduplication between virtual address spaces is discussed. Any inquiry concerning this communication or earlier communications from the examiner should be directed to ALEXANDER J YOON whose telephone number is (408)918-7629. The examiner can normally be reached on Monday-Friday 8am-3pm ET. The examiner’s email is alexander.yoon2@uspto.gov. Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice. If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Jared Rutz can be reached on 571-272-5535. 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If you would like assistance from a USPTO Customer Service Representative or access to the automated information system, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000. /ALEXANDER YOON/ Examiner, Art Unit 2135 /JARED I RUTZ/ Supervisory Patent Examiner, Art Unit 2135 Application/Control Number: 19/107,813 Page 2 Art Unit: 2135 Application/Control Number: 19/107,813 Page 3 Art Unit: 2135 Application/Control Number: 19/107,813 Page 4 Art Unit: 2135 Application/Control Number: 19/107,813 Page 5 Art Unit: 2135 Application/Control Number: 19/107,813 Page 6 Art Unit: 2135 Application/Control Number: 19/107,813 Page 7 Art Unit: 2135 Application/Control Number: 19/107,813 Page 8 Art Unit: 2135 Application/Control Number: 19/107,813 Page 9 Art Unit: 2135 Application/Control Number: 19/107,813 Page 10 Art Unit: 2135 Application/Control Number: 19/107,813 Page 11 Art Unit: 2135 Application/Control Number: 19/107,813 Page 12 Art Unit: 2135 Application/Control Number: 19/107,813 Page 13 Art Unit: 2135 Application/Control Number: 19/107,813 Page 14 Art Unit: 2135 Application/Control Number: 19/107,813 Page 15 Art Unit: 2135 Application/Control Number: 19/107,813 Page 16 Art Unit: 2135 Application/Control Number: 19/107,813 Page 17 Art Unit: 2135 Application/Control Number: 19/107,813 Page 18 Art Unit: 2135
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