DETAILED ACTION
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
The text of those sections of Title 35, U.S. Code not included in this action can be found in a prior Office action.
This Action is in response to communications filed 07/20/2026.
Claims 26-27, 31-40, 43, and 45 have been amended.
Claims 26-45 are pending.
Claims 26-45 are rejected.
Response to Amendment
In the Remarks filed 07/20/2026, Applicant has amended:
The language of claim 26 to address the antecedent basis issue regarding the second recitation of the “second physical memory associated with second processor”. The Examiner therefore withdraws the corresponding 112(b) rejection made in the Office action dated 04/20/2026.
The language of claim 31 to address the antecedent basis issues regarding the recitation of the terms “first portion” and “second portion” by establishing proper antecedent basis with respect to claim 26 and “physical memory” and “processor” by removing the offending terms from the claim language. The Examiner therefore withdraws the corresponding 112(b) rejection made in the Office action dated 04/20/2026.
The language of claim 36 to address the antecedent basis issues regarding the recitation of the “a request” by distinguishing the request as “a translation request” from the request recited in claim 35 from which claim 36 depends. The Examiner therefore withdraws the corresponding 112(b) rejection made in the Office action dated 04/20/2026.
Response to Arguments
In Remarks filed on 07/20/2026, Applicant substantially argues:
On Page 2, the amended limitations of claim 37 now requires the “distributed address translation service … to be provided by at least the first memory management unit and the second memory management unit” wherein the units provide respective translation services for a first portion and second portion of the virtual address space which are not taught by Burns et al. Applicant’s arguments filed have been fully considered but they are moot in view of the current rejection made in response to Applicant’s amendments.
On Page 3, the amended limitations of claim 26 and claim 35, similarly amended as claim 37, are not rendered obvious by the prior art references of record for similar reasons as indicated for claim 37 regarding the distributed address translation service. Applicant’s arguments filed have been fully considered but they are moot in view of the current rejection made in response to Applicant’s amendments.
The prior art references fail to teach or render obvious the limitations of dependent claims 27-34, 36, and 38-45 by virtue of dependency on respective independent claims 26, 35, and 37 for the reasons indicated above. Applicant’s arguments filed have been fully considered but they are moot in view of the current rejection made in response to Applicant’s amendments.
All arguments by the applicant are believed to be covered in the body of the office action; thus, this action constitutes a complete response to the issues raised in the remarks dated July 20, 2026.
Claim Rejections - 35 USC § 112
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claim 35 is rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor, or for pre-AIA the applicant regards as the invention.
Claim 35 recites “receiving an address translation response to the address translation request, wherein the response identifies that…” Herein the recitation of “wherein the response” lacks proper antecedent basis with respect to the prior amended term “an address translation response” and should be corrected. Subsequent recitation of “the address translation response” have been amended and therefore the correction should align the term as according to the other uses within the limitation.
Appropriate correction is required.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102 of this title, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries set forth in Graham v. John Deere Co., 383 U.S. 1, 148 USPQ 459 (1966), that are applied for establishing a background for determining obviousness under 35 U.S.C. 103(a) are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
Claims 26-30 and 35-36 are rejected under 35 U.S.C. 103 as being unpatentable over Burns et al. (US 11,455,247) in view of Hornung et al. (US 2022/0292026) and further in view of Klein et al. (US 2017/0046277).
Regarding claim 26, Burns discloses, in the italicized portions, an apparatus comprising: a first processor device; first physical memory to store a page table associated with a virtual address space of a process, wherein a first portion of the virtual address space is mapped to the first physical memory and a second portion of the virtual address space is mapped to a second physical memory of a second processor device ([Col. 4 ln. 6-16] Controller 100 may run on local device 101, and may provide one or more applications running on local device 101 with a virtual memory address space that spans and seamlessly accesses different allocations of physical memory from each of local device 101 and remote device 103. In particular, controller 100 may control the allocation of memory from local device 101 and remote device 103 to a particular application, and may control the swapping of pages containing data used by the particular application between the memories allocated from the two separate devices 101 and 103.); a first memory management unit associated with the first processor device, wherein a distributed address translation service is to be provided by at least the first memory management unit and a second memory management unit associated with the second processor device, the first memory management unit provides address translation services for the first portion of the virtual address space, and the second memory management unit provides address translation services for the second portion of the virtual address space, wherein the first memory management unit comprises ([Col. 6 ln. 58-62] In some embodiments, controller 100 may perform the address translation based on a paging table that is maintained by one or more of controller 100, a memory management unit (“MMU”) of local device 101, or the OS of local device 101.): an address translation client to: send a distributed address translation request to the second processor device, wherein the distributed address translation request identifies a second virtual memory address associated with the process; receive, from the second memory management unit, a response to the distributed address translation request, wherein the response to the distributed address translation request identifies that a second physical memory address of the second physical memory associated with the second processor device is mapped to the second virtual memory address ([Col 6 ln. 63 – Col. 7 ln. 2] Process 300 may include retrieving (at 310) the requested page from the mapped physical memory address of remote device 103 using RDMA or another transport mechanism over an interconnect fabric that connects local device 101 to remote device 103. Remote device 103 may read the requested page from the mapped physical memory address, and may return the requested page to controller 100.); and add a mapping of the second virtual memory address to the second physical memory address in the page table based on the response. Herein Burns discloses a system comprising distributed storage wherein portions of memory of remote devices may be allocated to a virtual address space of an application on a local device and collectively used for access by the application to access memory from the plurality of devices. As part of the shared storage system, when requests for data cannot be serviced locally, the request is then transmitted to a remote device for data retrieval. Burns does not explicitly disclose sending a translation request to a second processor device with the identified second virtual memory address which includes a respective second memory management unit which handles respective distributed address translation services and adding a mapping of the second virtual memory address to the second physical memory address to the page table based on the response to the request. Regarding the second processor device as including the second memory management unit which receives and responds to the distributed address translation request, Hornung discloses in Paragraphs [0034-36] “[0034] The memory devices may each include a memory management unit (MMU) or a processor configured to perform operations on the memory. The MMU or processor of each memory device may be configured to generate a data packet to be transmitted from device-to-device. [0035] The address may be located within the range of the shared virtual address space. By way of example, the a MMU or processor of a first memory device (e.g., a transmitting memory device) may generate a data packet that includes a first field that identifies a second memory device (e.g., a receiving memory device). [0036] The MMU or processor of the first memory device may be configured to transmit the data packet to the second memory device, and the MMU, a controller, or a processor of the second memory device may access a physical address based on the virtual address included in the second field. That is, the MMU, controller, or processor of the second memory device may translate the virtual address to a physical address based on a local address translation table.” Herein Hornung explicitly discloses that each memory device of the plurality devices of the distributed memory may comprise a MMU which is involved in communications with MMUs of other devices. The first MMU transmits the packet to the second MMU which performs the corresponding address translation within the virtual address space of the system to a physical address on the local memory. In this manner, it would be obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to incorporate the respective MMU structure as taught by Hornung into the shared memory system as taught in Burns in order to coordinate memory accesses without requiring the involvement of the host system and thereby reducing access latency (Hornung [0036]). Hornung does not explicitly address adding the mapping of the second virtual memory address to the second physical memory address to the page table based on the second MMU response. Regarding this aspect of the limitation, Klein discloses in Paragraphs [0052-53] “[0052] According to one embodiment, the method further comprises in response to receiving by the MMU a request of a second data block via a second virtual address, determining that a second entry of the entries corresponds to the second virtual address, the second entry comprising a second physical address of the second data block, and using the second physical address for accessing the second data block. This embodiment may have the advantage to be seamlessly integrated in the existing systems having entries encoded with a structure different from the structure of the added entry (of each data block of the first set of the data blocks). [0053] According to one embodiment, the execution of the program instruction further causes the processor to add entries in the page table, wherein entries comprise information indicating physical addresses.” Herein Klein explicitly discloses use of an access request for a second memory block via a second virtual address which is then accessed by the corresponding MMU which translates the second virtual address to a second physical address and returns the data. Furthermore, Klein notes the processor may then add entries to the page table including the physical addresses corresponding to the execution of the program. In this manner, it would be obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to maintain updated page tables of translation mappings according to process execution in order to improve access performance (Klein [0050]). Burns, Hornung, and Klein are analogous art because they are from the same field of endeavor of managing address translation services.
Regarding claim 27, Burns, Hornung and Klein further disclose the apparatus of Claim 26, wherein the first memory management unit further comprises: an address translation server to: receive a request to translate a first virtual memory address in the first portion of the virtual address space into a physical address of the first physical memory; determine, from the page table, a mapping of the first virtual memory address to a first physical memory address of the first physical memory; and return the first physical memory address as a response to the request (Burns [Col. 6 ln. 58-62] and Klein [0030]). Herein both Burns and Klein disclose use of a page table to translate virtual addresses to generate physical addresses. Additionally, Hornung [0036] discloses each MMU of each memory device may perform respective address translation services.
Regarding claim 28, Burns further discloses the apparatus of Claim 26, wherein the first physical memory address addresses a first page of data within the first physical memory, and the second physical memory address addresses a second page of data within the second physical memory ([Col 2 ln. 23-30] Moreover, the controller may expand the virtual address space of the applications, and perform the dynamic mapping and transfer of data from addresses in the virtual address space to addresses in the physical memories of the local device and the remote disaggregated memory device without modifying the applications, the memory management system of the local device, or the operating system (“OS”) of the local device.). Herein Burns discloses that data is accessed from the disaggregated memory from the translated virtual addresses to respective physical addresses.
Regarding claim 29, Burns further discloses the apparatus of Claim 26, wherein the first processor device and the second processor device are interconnected in a distributed computing architecture, and virtual memory for the computing architecture is distributed between memory of at least the first processor device and the second processor device ([Col 2 ln. 66- Col. 3 ln. 1] Local device 101 may include a server, host, and/or another computing node with local or onboard processing, memory, storage, networking, and/or other resources. [Col. 2 ln. 13-21] Remote device 103 may be a disaggregated memory device that operates independent of and separate from local device 101. Specifically, an application may run directly on local device 101 using processing and other resources of local device 101 and may be controlled by the OS of local device 101. However, controller 100 may allow the application to access additional RAM or memory resources from remote device 103 via an interconnect fabric that connects local device 101 to remote device 103.). Herein Burns discloses the disaggregated memory system used in combination over a networked connection for distributing processing.
Regarding claim 30, Burns and Hornung further disclose the apparatus of Claim 29, wherein the distributed computing architecture comprises pooled memory shared within the distributed computing architecture, and the memory of the first processor device comprises the first physical memory and at least a portion of the pooled memory (Burns [Col 2 ln. 66- Col. 3 ln. 1] Local device 101 may include a server, host, and/or another computing node with local or onboard processing, memory, storage, networking, and/or other resources. [Col. 2 ln. 13-21]). As similarly presented in the rejection of claim 29, the disaggregated memory between the devices is shared and a local device utilizes a portion of local memory in addition to portions of memory of remote devices for allocation to virtual address spaces. Additionally Hornung [0048] discloses the shared virtual memory address space as comprising allocated memory from the plurality of memory devices.
Regarding claim 35, Burns discloses, in the italicized portions, a method comprising: identifying that a first processor device is associated with a first region of a virtual memory of a process and that a second processor device is associated with a second region of the virtual memory of the process, wherein a first portion of virtual addresses in the virtual memory are included in the first region and a second portion of the virtual addresses in the virtual memory are included in the second region ([Col. 7 ln. 3-21] Process 300 may include performing (at 312) a memory transfer to load the requested page retrieved from the physical memory of remote device 103 into the physical memory from local device 101 that is allocated for the particular application. In some embodiments, loading (at 312) the retrieved page may include responding to the page fault notification by notifying the kernel or OS that the page has been retrieved and is available for access from the physical memory of local device 101. Controller 100, the OS, or the MMU may update a paging table to identify the memory address within the physical memory of local device 101 where the page is stored. More specifically, the paging table may be modified so that the virtual address for the requested page points to a physical memory address of local device 101 where the requested page is now stored instead of a physical memory address of remote device 103 where the requested page was retrieved and transferred into the physical memory of local device 101.); sending an address translation request from the first processor device to the second processor device to translate a first virtual address in the virtual memory based on identifying that the first virtual address is included in the second region, wherein the address translation request is sent to the second processor device based on identifying that the second processor device is associated with the second region; receiving an address translation response to the address translation request, wherein the response identifies that a first physical address of the second processor device is mapped to the first virtual address ([Col 6 ln. 63 – Col. 7 ln. 2] Process 300 may include retrieving (at 310) the requested page from the mapped physical memory address of remote device 103 using RDMA or another transport mechanism over an interconnect fabric that connects local device 101 to remote device 103. Remote device 103 may read the requested page from the mapped physical memory address, and may return the requested page to controller 100.); updating a page table of the first processor device based on the address translation response, wherein the page table comprises local entries and remote entries, the local entries map virtual addresses in the first region to physical addresses in physical memory of the first processor device, and the remote entries map regions of the virtual memory to physical addresses in physical memory of other processor devices in a system, wherein the other processor devices comprise the second processor device ([Col. 7 ln. 3-21]), wherein address translation services for the virtual memory of the process are distributed between at least the first processor device and the second processor device. Herein Burns discloses a system comprising distributed storage wherein portions of memory of remote devices may be allocated to a virtual address space of an application on a local device and collectively used for access by the application. As part of the shared storage system, when requests for data cannot be serviced locally, the request is then transmitted to a remote device for data retrieval. Burns does not explicitly disclose sending an address translation request to the second processor device with the identified first virtual memory address is included in the second region and which handles respective distributed address translation services and adding a mapping of the second virtual memory address to the second physical memory address to the page table based on the response to the request. Regarding the second processor device which receives and responds to the distributed address translation request, Hornung discloses in Paragraphs [0034-36] that each memory device of the plurality devices of the distributed memory may comprise a MMU which is involved in communications with MMUs of other devices. The first MMU transmits the packet to the second MMU which performs the corresponding address translation within the virtual address space of the system to a physical address on the local memory. In this manner, it would be obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to incorporate the respective MMU structure as taught by Hornung into the shared memory system as taught in Burns in order to coordinate memory accesses without requiring the involvement of the host system and thereby reducing access latency (Hornung [0036]). Hornung does not explicitly address adding the mapping of the second virtual memory address to the second physical memory address to the page table based on the second MMU response. Regarding this aspect of the limitation, Klein discloses in Paragraphs [0052-53] use of an access request for a second memory block via a second virtual address which is then accessed by the corresponding MMU which translates the second virtual address to a second physical address and returns the data. Furthermore, Klein notes the processor may then add entries to the page table including the physical addresses corresponding to the execution of the program. Claim 35 is rejected on a similar basis as claim 26.
Regarding claim 36, Burns, Hornung and Klein in combination further disclose the method of Claim 35, further comprising: receiving, from the second processor device at the first processor device, a translation request to translate a second virtual address, wherein the second virtual address is included in the first region; determining, at the first processor device, from the page table, that the second virtual address maps to a second physical address in physical memory of the first processor device (Burns [Col. 4 ln. 6-16] and [Col 6 ln. 63 – Col. 7 ln. 2]); sending, from the first processor device to the second processor device, a translation response to the translation request to translate the second virtual address, wherein the translation response identifies that the second virtual address maps to the second physical address, wherein the translation response is for use in updating a page table of the second processor device (Klein [0052-53]). In a similar fashion to the rejection of claim 35 wherein the local device performs a translation request to the remote device, it would be obvious to one of ordinary skill in the art that the configuration wherein said local device is the relative remote device to the application executing on the remote device, then the similar steps may be performed for requesting and receiving the translation response as identified.
Claim 31 is rejected under 35 U.S.C. 103 as being unpatentable over Burns in view of Hornung and further in view of Klein and still further in view of Hornung et al. (US 2023/0393970), hereinafter Hornung II.
Regarding claim 31, Burns, Hornung, and Klein in combination further disclose, in the italicized portions, the apparatus of Claim 26, wherein the first portion of the virtual address space corresponds to a first region of the virtual address space of the process, and the second portion of the virtual address space corresponds to a second region of the virtual address space of the process (Burns [Col. 4 ln. 6-16] and Hornung [0048] By way of example, a shared virtual address space may exist across at least a portion of the memory device 215-a, the memory device 215-b, the memory device 220-a, and the memory device 220-b.), wherein the virtual address space corresponds to a Process Address Space Identifier (PASID) associated with the process. Herein, as previously indicated, Burns and Hornung both disclose allocation of both local and remote device memory to a virtual address space. Burns, Hornung, and Klein do not explicitly address the virtual address space as corresponding to a PASID associated with the process. Regarding this aspect of the limitation, Hornung II discloses in Paragraph [0050] “FIG. 5 illustrates an example diagram of a first portion of a virtual to physical translation logic 500 according to some examples of the present disclosure. The virtual address of the memory request and the CXL process address ID (PASID) of the requestor is passed to the virtual-to-physical translation logic 500 shown in FIG. 5. The global shared range check component 512 determines, based upon the virtual address, if the virtual address is part of the global virtual address space.” Herein Hornung II explicitly discloses that requests in the shared memory system may include a process address ID which identifies the request as being allowed access to the shared memory space. It would be obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to incorporate the teaching of Hornung II to further utilize PASID in order to control process access to shared memory (Hornung II [0022]). Burns, Hornung, Klein, and Hornung II are analogous art because they are from the same field of endeavor of managing address translation services.
Claims 32-33 are rejected under 35 U.S.C. 103 as being unpatentable over Burns in view of Hornung and further in view of Klein and still further in view of Hornung II and Talagala et al. (US 2013/0212321).
Regarding claim 32, Burns, Hornung, Klein and Hornung II do not explicitly disclose the apparatus of Claim 31, wherein the address translation client is further to: send a region query for the virtual address space of the process; and receive a region assignment listing, wherein the region assignment listing identifies a plurality of regions of the virtual address space of the process and maps a plurality of processors in a system to respective regions in the plurality of regions, wherein the first processor device and second processor device are included in the plurality of processors, and the first region and the second region are included in the plurality of regions, wherein the distributed address translation request is sent to the second processor device based on the region assignment listing. Regarding these limitations, Talagala discloses in Paragraph [0237] “The populate module 1905 may transfer data between address spaces by preserving, adding, updating, and/or changing a logical-to-physical mapping for transferred data in a mapping structure, index, forward map, or the like as described above with regard to the metadata 1051 and/or forward index 1053 maintained by the SML 1050. For example, to transfer data from an address space of the non-volatile memory media 1110 to an address space of the ACM 1011, 1111 in response to a populate request to transfer the data into the ACM 1011, 1111, the populate module 1905 may remove an entry for the data from a forward index 1053 or other mapping structure for the non-volatile memory media 1110 and add an entry for the data in an index or other mapping structure for the ACM 1011, 1111.” Herein Talagala discloses a distributed storage system which uses a populate module 1905 to maintain a mapping structure. Specifically, a device in the system may transmit a populate command to update and access the mapping structure. This command is interpreted as falling within the broadest reasonable interpretation of the query command as claimed as the requestor receives access to the mapping structure which maintains virtual namespace assignment across the physical storage locations. In this manner, it would be obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to acquire updated mapping information prior to transmitting the translation request in order to determine the current allocation of addresses in the distributed storage system (Talagala [0235]). Burns, Hornung, Klein, Hornung II, and Talagala are analogous art because they are from the same field of endeavor of managing address translation services.
Regarding claim 33, Talagala further discloses the apparatus of Claim 32, wherein the system comprises a root complex, and the region query is sent to and the region assignment listing is received from the root complex ([0257] The communications bus 1040 may be in communication with the processor complex 1012 through a northbridge device, a root complex, or the like of the processor complex 1012.). Herein Talagala discloses the PCI-e communication being routed through a root complex.
Claim 34 is rejected under 35 U.S.C. 103 as being unpatentable over Burns in view of Hornung and further in view of Klein and still further in view of Liu (US 2022/0245067).
Regarding claim 34, Burns, Hornung, and Klein do not explicitly disclose the apparatus of Claim 26, wherein the distributed address translation request comprises a first packet based on a Peripheral Component Interconnect Express (PCIe)-based address translation service (ATS) protocol, and the response to the distributed address translation request comprises a second packet based on the PCIe-based ATS protocol. Regarding this limitation, Liu discloses in Paragraph [0003] “Before accessing a memory of a processor based on a direct memory access (Direct Memory Access, DMA) protocol, a high-speed serial computer extended bus standard (peripheral component interconnect express, PCIe) device may send an address translation request (Address Translation Service, ATS) packet to the processor, to request the processor to feed back information about a page table corresponding to first virtual storage space.” Herein Liu discloses as part of the memory access of a processor to utilize over the PCIe interconnect an ATS packet to obtain mapping information. It would be obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to incorporate the ATS packets over the PCIe interface for collecting mapping information in order to acquire updated mapping information to ensure proper memory addressing on subsequent accesses as the mappings may change over time and this avoids improper addressing based on configuration changes (Liu [0016]). Burns, Hornung, Klein, and Liu are analogous art because they are from the same field of endeavor of managing address translation services.
Claims 37-38 are rejected under 35 U.S.C. 103 as being unpatentable over Burns in view of Hornung.
Regarding claim 37, Burns discloses, in the italicized portions, a system comprising: a first processing unit comprising: processing circuitry; first physical memory; a first memory management unit comprising circuitry to maintain a first page table corresponding to virtual memory of a program ([Col. 4 ln. 6-11] Controller 100 may run on local device 101, and may provide one or more applications running on local device 101 with a virtual memory address space that spans and seamlessly accesses different allocations of physical memory from each of local device 101 and remote device 103. [Col. 6 ln. 58-62] In some embodiments, controller 100 may perform the address translation based on a paging table that is maintained by one or more of controller 100, a memory management unit (“MMU”) of local device 101, or the OS of local device 101.); and a second processing unit comprising: processing circuitry; second physical memory; a second memory management unit comprising circuitry to maintain a second page table corresponding to the virtual memory of the program ([Col. 3 ln. 13-21] Remote device 103 may be a disaggregated memory device that operates independent of and separate from local device 101. Specifically, an application may run directly on local device 101 using processing and other resources of local device 101 and may be controlled by the OS of local device 101. However, controller 100 may allow the application to access additional RAM or memory resources from remote device 103 via an interconnect fabric that connects local device 101 to remote device 103.), wherein a distributed address translation service for the virtual memory is to be provided by at least the first memory management unit and the second memory management unit, the first memory management units provides address translation services for a first portion of a virtual address space for the virtual memory, and the second memory management unit provides address translation services for a second portion of the virtual address space, wherein virtual addresses in the first portion of the virtual address space are mapped to physical addresses of the first physical memory in the first page table and virtual addresses in the second portion of the virtual address space are mapped to physical addresses of the second physical memory in the second page table ([Col. 4 ln. 6-16] Controller 100 may run on local device 101, and may provide one or more applications running on local device 101 with a virtual memory address space that spans and seamlessly accesses different allocations of physical memory from each of local device 101 and remote device 103. In particular, controller 100 may control the allocation of memory from local device 101 and remote device 103 to a particular application, and may control the swapping of pages containing data used by the particular application between the memories allocated from the two separate devices 101 and 103. And [Col. 6 ln. 58-62]). Herein Burns teaches a distributed storage configuration wherein memory from a local device and memory from at least a remote device are allocated to the virtual memory address space of an application executing on the local device and collectively used for access by the application to access memory from the plurality of devices. Each of the devices maintain respective paging tables for tracking address translations to determine which requests virtual memory address maps to the corresponding device physical memory address. The distributed memory allocation provides increased storage performance across the plurality of devices. Burns does not explicitly disclose the second processing unit comprising a respective second memory management unit which handles respective distributed address translation services. Regarding this aspect of the limitation, Hornung discloses in Paragraphs [0034-36] that each memory device of the plurality devices of the distributed memory may comprise a MMU which is involved in communications with MMUs of other devices. The first MMU transmits the packet to the second MMU which performs the corresponding address translation within the virtual address space of the system to a physical address on the local memory. In this manner, it would be obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to incorporate the respective MMU structure as taught by Hornung into the shared memory system as taught in Burns in order to coordinate memory accesses without requiring the involvement of the host system and thereby reducing access latency (Hornung [0036]).
Regarding claim 38, Burns and Hornung in combination further disclose the system of Claim 37, wherein the circuitry of the first memory management unit comprises: address translation server circuitry to handle queries of the first portion of the virtual address space; and address translation client circuitry to query the second processing unit for virtual address mappings for the second portion of the virtual address space (Burns [Col. 3 ln. 49-54] Controller 100 may communicate with the processor and/or memory management software of remote device 103, and may directly access the physical memory of remote device 103 using different lightweight, low latency, and high-speed interconnect fabrics and/or transport mechanisms.). Herein the responsibilities of handling queries are demonstrated by the controller circuitry of the local device. As it is previously indicated that the remote devices operate independently of the local device, it is presented that each device comprises circuitry capable of performing the querying functions from other respective remote devices. In view of Hornung [0034-36] wherein each memory device may comprise a MMU to handle translation requests, it would be obvious to one of ordinary skill in the art that the respective operations may be performed at each device to respond to translation requests.
Claims 39-42 are rejected under 35 U.S.C. 103 as being unpatentable over Burns in view of Hornung and further in view of Hamidouche et al. (US 2021/0191641).
Regarding claim 39, Burns discloses, in the italicized portions, the system of Claim 37, wherein the first processing unit and the second processing unit are interconnected by a fabric in a distributed computing environment ([Col. 2 ln. 63-65] Local device 101 may be connected to remote device 103 via one or more interconnect fabrics), the first processing unit is of a different type than the second processing unit, the first memory management unit comprises a first input-output memory management unit (IOMMU), and the second memory management unit comprises a second IOMMU (Burns [Col. 6 ln. 58-62] and Hornung [0034-36]). Herein Burns notes the devices in the system are connected via one or more interconnect fabrics and both Burns and Hornung disclose that each device may comprise a respective MMU, considered otherwise analogous to the IOMMU. Burns and Hornung do not explicitly disclose that the processing units are of different types. Regarding this aspect of the limitation, Hamidouche discloses in Paragraph [0008] “In some embodiments, the first memory is a central processing unit (CPU) memory (hereinafter also referred to as “CPU memory”) primarily associated with a first processor (hereinafter also referred to as “CPU”)) and the second memory is a graphics processing unit (GPU) memory (hereinafter also referred to as “GPU memory”) primarily associated with a second processor or coprocessor (hereinafter also referred to as “GPU”).” Herein Hamidouche discloses in the context of a shared memory pool system, processing units of different types may share memory for virtual address spaces allocated to processes executing on each respective processing unit. In this manner, it would be obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to allocate memory from different devices to processing units of different types to improved shared memory utilization (Hamidouche [0008]). Burns, Hornung, and Hamidouche are analogous art because they are from the same field of endeavor of managing a shared memory pool.
Regarding claim 40, Hamidouche further discloses the system of Claim 39, wherein the first processing unit comprises a central processing unit, and the second processing unit comprises one of a graphics processing unit, a data processing unit, or an infrastructure processing unit ([0008]). Herein Hamidouche explicitly discloses the respective memories belong to a CPU and GPU.
Regarding claim 41, Burns and Hornung do not explicitly disclose the system of Claim 37, wherein the program is to utilize the first processing unit and the second processing unit during execution. Regarding this aspect of the limitation, Hamidouche discloses in Paragraph [0011] “For ease of illustration, the following description refers frequently to implementations of a coprocessor as a GPU. However, the present disclosure is not limited to this example context, but instead is applicable to any of a variety of coprocessors, including application-specific integrated circuits (ASICs) for machine learning and artificial intelligence applications, and the like, using the guidelines provided herein. As such, reference to a GPU as the coprocessor also applies to other types of coprocessors unless explicitly indicated.” Herein Hamidouche discloses that the other processing unit functions as a coprocessor and therefore both processing units are involved in the execution of code. In this manner, it would be obvious to one of ordinary skill in the art before the effective filing date of the claimed invention in the context of coprocessors that both processing units are involved in instruction execution for distributed processing.
Regarding claim 42, Hamidouche further discloses the system of Claim 41, wherein the program comprises one of a machine learning or artificial intelligence program ([0011]). Herein Hamidouche explicitly discloses the processing units as being applicable for machine learning or artificial intelligence execution.
Claims 43-44 are rejected under 35 U.S.C. 103 as being unpatentable over Burns in view of Hornung and further in view of Feehrer et al. (US 2021/0133123).
Regarding claim 43, Burns and Hornung do not explicitly disclose the system of Claim 37, further comprising fabric-attached memory, wherein a portion of virtual addresses in the first portion of the virtual address space are mapped to physical addresses of the fabric-attached memory. Regarding this limitation, Feehrer discloses in Paragraph [0060] “Such access by one GPU of the local memory of another GPU may be “the same” (although not quite as fast), from the perspective of an application executing on the GPU originating the access, as if the GPU were accessing its own locally attached memory. Hardware within each GPU 102 and hardware within switch 104 provides necessary address translations to map virtual addresses used by the executing application into physical memory addresses of the GPU's own local memory and the local memory of one or more other GPUs. As explained herein, such peer-to-peer access is extended to fabric attached memory without the concomitant expense of adding further compute-capable GPUs.” Herein Feehrer discloses a shared memory system wherein a plurality of processing units are capable of allocating and accessing distributed memory including fabric attached memory. More specifically, it is identified that the virtual addresses are mapped to physical memory addresses of both local memory and memory local to other processing units. In this manner, it would be obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to allocate memory from different devices to processing units to improve shared memory utilization (Feehrer [0016]). Burns, Hornung and Feehrer are analogous art because they are from the same field of endeavor of managing a shared memory pool.
Regarding claim 44, Feehrer further discloses the system of Claim 43, wherein the fabric-attached memory comprises a pool of memory comprised of physical memory from a plurality of devices in the system ([0121] In accordance with another example non-limiting advantageous feature, a source GPU 102 can use the full inter-GPU communication bandwidth for accessing fabric attached memory by interleaving the fabric attached memory accesses across multiple donor fabric attached memories. The source GPU is thus able to “spray” (interleave) memory accesses across multiple links/interconnects of the fabric attached to it to access an attached memory pool via a plurality of donor memory controller hardware units.). Herein Feehrer discloses the disaggregated memory from the donor hardware forms a fabric attached memory pool.
Claim 45 is rejected under 35 U.S.C. 103 as being unpatentable over Burns in view of Hornung and further in view of Talagala.
Regarding claim 45, Burns and Hornung do not explicitly disclose the system of Claim 37, wherein the second processing unit comprises host circuitry to: receive a region query from the first processing unit relating to the virtual memory of the program; identify a region mapping for the virtual memory of the program, wherein the region mapping identifies that physical memory of the first processing unit is to be mapped to the first portion of virtual addresses and that physical memory of the second processing unit is to be mapped to the second portion of the virtual address space; and return the region mapping to the first processing unit as a response to the region query. Regarding these limitations, Talagala discloses in Paragraph [0237] “The populate module 1905 may transfer data between address spaces by preserving, adding, updating, and/or changing a logical-to-physical mapping for transferred data in a mapping structure, index, forward map, or the like as described above with regard to the metadata 1051 and/or forward index 1053 maintained by the SML 1050. For example, to transfer data from an address space of the non-volatile memory media 1110 to an address space of the ACM 1011, 1111 in response to a populate request to transfer the data into the ACM 1011, 1111, the populate module 1905 may remove an entry for the data from a forward index 1053 or other mapping structure for the non-volatile memory media 1110 and add an entry for the data in an index or other mapping structure for the ACM 1011, 1111.” Herein Talagala discloses a distributed storage system which uses a populate module 1905 to maintain a mapping structure. Specifically, a device in the system may transmit a populate command to update and access the mapping structure. This command is interpreted as analogous to the query command as claimed as the requestor receives access to the mapping structure which maintains virtual namespace assignment across the physical storage locations. In this manner, it would be obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to acquire updated mapping information prior to transmitting the translation request in order to determine the current allocation of addresses in the distributed storage system (Talagala [0235]). Burns, Hornung and Talagala are analogous art because they are from the same field of endeavor of managing address translation services.
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure. Michaud et al. (US 10,289,555) – Figure 4 and corresponding disclosure wherein a virtual address space and adding entries to a page table is discussed.
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
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/ALEXANDER YOON/
Examiner, Art Unit 2135
/JARED I RUTZ/Supervisory Patent Examiner, Art Unit 2135
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