Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
DETAILED ACTION
Examiner cites particular columns or paragraphs, and line numbers in the references as applied to the claims below for the convenience of the applicant. Although the specified citations are representative of the teachings in the art and are applied to the specific limitations within the individual claim, other passages and figures may apply as well. It is respectfully requested that, in preparing responses, the applicant fully consider the references in entirety as potentially teaching all or part of the claimed invention, as well as the context of the passage as taught by the prior art or disclosed by the examiner.
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
In reply to the Non-Final Office Action mailed on 2/12/2026, the applicant has filed a response on 5/12/2026 amending claims 1-2, 5 and 8-10. Claim 11 has been added. No claim has been cancelled. Claims 1-11 are pending in this application.
Previous claim objections are withdrawn in view of applicant’s amendments filed on 5/12/2026.
Previous rejections under 35 U.S.C. 112(b) are withdrawn in view of applicant’s amendments filed on 5/12/2026.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claim(s) 1 is/are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Min et al. (US 2022/0215783).
Regarding claim 1, Min discloses a patterned resistance detection circuit for a display panel including a first pad, a second pad, and a patterned resistance connected to the first pad and the second pad (see circuit in Fig. 2 for display panel 100 including first pad 111, second pad 113 and a resistance Rpanel connected to the first pad 111 and the second pad 113), the patterned resistance detection circuit comprising:
a current source generator configured to generate a reference current and apply to the patterned resistance via the first pad to generate a detection voltage corresponding to a resistance value of the patterned resistance (see in Fig. 2, “first pad part 111 receives a first voltage VDD from a power supply” clearly generating and applying a corresponding current to the resistance Rpanel via the first pad 111 to generate a voltage corresponding to a resistance value of the resistance Rpanel, measured at the second pad 113; “The crack resistance measurement circuit 520 is connected to the crack resistance circuit of the display panel 100 through the second pad part 113 to measure the crack resistance Rpanel of the crack resistance circuit”, clearly detected as a voltage to be input to comparator 522, as shown in Fig. 3; this is because a comparator does not inherently measure resistance, and to use resistance in a comparison, it must be first converted to a voltage, since what is compared by a comparator are actual voltages at each of its input terminals; para[0031]-para[0032]; para[0044]; para[0048]);
a reference voltage generator configured regarding Figs. 2-4, see reference resistance generation circuit 521, clearly corresponding to a reference voltage accordingly, to be provided to comparator 522; this is because a comparator does not inherently measure resistance, and to use resistance in a comparison, it must be first converted to a voltage, since what is compared by a comparator are actual voltages at each of its input terminals; para[0049]-para[0050]);
a comparator the detection voltage generated by applying the reference current to the patterned resistance via the first pad , and thereby output a voltage comparison result (regarding Fig. 3, “comparator 522 compares the crack resistance Rpanel of the display panel 100 with the reference resistance Rref of the reference resistance generation circuit 521 and outputs a resistance comparison result”, clearly representing a voltage comparison result; that is, the voltage measurement at the second pad 113 caused by the current applied to the resistance Rpanel via the first pad 111 is compared to the reference voltage provided by the reference resistance generation circuit 521, and the corresponding voltage is output to circuit controller 523; this is because a comparator does not inherently measure resistance, and to use resistance in a comparison, it must be first converted to a voltage, since what is compared by a comparator are actual voltages at each of its input terminals; para[0044]; para[0049]; para[0054]; para[0056]); and
a circuit controller configured to output a reference voltage control signal for controlling the reference voltage generator according to the voltage comparison result (regarding Figs. 3-4, “in order to control the magnitude of the reference resistance Rref according to a comparison result by the comparator 522, the circuit controller 523 supplies the reference resistance control signal RCS for controlling the switches SW.sub.1 to SW.sub.N of the reference resistance generation circuit 521”; para[0056]).
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 2-5 is/are rejected under 35 U.S.C. 103 as being unpatentable over Min et al. (US 2022/0215783), in view of Huang et al. (US 2021/0304823).
Regarding claim 2, Min discloses all the claim limitations as applied above (see claim 1). In addition, Min discloses the current source generator includes: a first power source (see in Fig. 2, “first pad part 111 receives a first voltage VDD from a power supply” clearly generating and applying a corresponding current to the resistance Rpanel via the first pad 111; para[0031]-para[0032]). However, Min does not appear to expressly disclose the current source generator includes: a current source connected to the first power source; a first transistor including a first drain electrode connected to the current source, a first gate electrode connected to the first drain electrode, and a first source electrode connected to a second power source; and a second transistor including a second drain electrode connected to the patterned resistance via the first pad of the display panel, a second gate electrode connected to the first gate electrode of the first transistor, and a second source electrode connected to the second power source.
Huang discloses a current source generator includes: a current source connected to a first power source (see in Fig. 1, current source Irefcell connected to ground; para[0042]); a first transistor including a first drain electrode connected to the current source, a first gate electrode connected to the first drain electrode, and a first source electrode connected to a second power source (see transistor P2 with a first drain electrode connected to Irefcell, a first gate electrode connected to the first drain electrode, and a first source electrode connected to power supply voltage VDD, as shown in Fig. 1; para[0042]); and a second transistor including a second drain electrode connected to an output node connected to a load, a second gate electrode connected to the first gate electrode of the first transistor, and a second source electrode connected to the second power source (see transistor P3 with a second drain electrode connected to a load at node E, a second gate electrode connected to the first gate electrode of transistor P2, and a second source electrode connected to power supply voltage VDD, as shown in Fig. 1; para[0042]).
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention, to combine the teachings in Min’s invention, with the teachings in Huang’s invention, to have the current source generator includes: a current source connected to the first power source; a first transistor including a first drain electrode connected to the current source, a first gate electrode connected to the first drain electrode, and a first source electrode connected to a second power source; and a second transistor including a second drain electrode connected to the patterned resistance via the first pad of the display panel as a result of the combination, a second gate electrode connected to the first gate electrode of the first transistor, and a second source electrode connected to the second power source, for the advantage of mirroring a current from a current source (para[0042]) to provide consistent output current regardless of load variations, as is known for current mirror circuits.
Regarding claim 3, Min and Huang disclose all the claim limitations as applied above (see claim 2). In addition, Huang discloses a first reference current flows through the first transistor, and a second reference current copied from the first reference current flows through the second transistor (regarding Fig. 1, a first reference current from reference current source Irefcell flows through transistor P, and a second reference current mirrored from the first reference current flows through transistor P3; para[0042]).
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention, to have a first reference current flows through the first transistor, and a second reference current copied from the first reference current flows through the second transistor, as also taught by Huang, for the advantage of providing consistent current regardless of load variations, as is known for current mirror circuits.
Regarding claim 4, Min and Huang disclose all the claim limitations as applied above (see claim 2). In addition, Huang discloses the first power source is a low potential voltage and the second power source is a high potential voltage (see the claimed first power source is a ground voltage and the claimed second power source is a higher power supply voltage VDD; para[0042]).
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention, to have the first power source is a low potential voltage and the second power source is a high potential voltage, as also taught by Huang, for the advantage of being able to allow current to flow through the transistors according to their type, as is conventionally known.
Regarding claim 5, Min and Huang disclose all the claim limitations as applied above (see claim 2). In addition, Huang discloses the second drain electrode of the second transistor is connected to the first power source via the load (as shown in Fig. 1, the second drain electrode of transistor P3 is connected to ground through the load between node E and ground).
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention, to have the second drain electrode of the second transistor is connected to the first power source via the first pad, the patterned resistance and the second pad as a result of the combination, for the advantage of being able to allow current to flow through this transistor according to its type, as is conventionally known.
Claim(s) 6 is/are rejected under 35 U.S.C. 103 as being unpatentable over Min et al. (US 2022/0215783), in view of Huang et al. (US 2021/0304823), as applied to claim 2 above, and further in view of Nomura (US 2023/0208360).
Regarding claim 6, Min and Huang disclose all the claim limitations as applied above (see claim 2). However, Min and Huang do not appear to expressly disclose the current source generator further includes: a bias transistor configured to supply a constant bias current to the first transistor.
Nomura discloses a bias transistor configured to supply a constant bias current to a first transistor (regarding Fig. 1, see transistor M1 as the claimed bias transistor configured to supply constant bias current to a transistor M2 of a current mirror; para[0007]; para[0059]; para[0073]).
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention, to combine the teachings in Min’s and Huang’s combination, with the teachings in Nomura’s invention, to have the current source generator further includes: a bias transistor configured to supply a constant bias current to the first transistor, for the advantage of a circuit that achieves low current consumption and high output current (para[0004]; para[0148]).
Claim(s) 7-8 is/are rejected under 35 U.S.C. 103 as being unpatentable over Min et al. (US 2022/0215783), in view of Huang et al. (US 2021/0304823), as applied to claim 2 above, and further in view of Chen et al. (US 2018/0329443).
Regarding claim 7, Min and Huang disclose all the claim limitations as applied above (see claim 2). However, Min and Huang do not appear to expressly disclose the current source generator further includes: a channel length modulation prevention circuit configured to copy a first drain voltage of the first transistor to a second drain voltage of the second transistor.
Chen discloses a channel length modulation prevention circuit configured to copy a first drain voltage of a first transistor to a second drain voltage of the second transistor (para[0024]-para[0026]; see Figs. 4 and 5; “drain voltages of… transistors… are locked using the electrical characteristic of the operational amplifier OP” to prevent “channel length modulation effect”).
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention, to combine the teachings in Min’s and Huang’s combination, with the teachings in Chen’s invention, to have the current source generator further includes: a channel length modulation prevention circuit configured to copy a first drain voltage of the first transistor to a second drain voltage of the second transistor, for the advantage of supplying output current which is an accurate copy of input current in a current mirror (para[0024]).
Regarding claim 8, Min, Huang and Chen disclose all the claim limitations as applied above (see claim 7). In addition, Chen discloses the channel length modulation prevention circuit includes: a differential amplifier configured to amplify a difference between first drain voltage of the first transistor and second drain voltage of the second transistor (para[0024]-para[0026]; see e.g. OP in Figs. 4 and 5); and a third transistor including a third drain electrode, a third gate electrode connected to the differential amplifier, and a third source electrode connected to the second drain electrode of the second transistor (para[0024]-para[0026]; see e.g. T1 in Figs. 4 and 5).
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention, to have the channel length modulation prevention circuit includes: a differential amplifier configured to amplify a difference between the first drain voltage of the first transistor and the second drain voltage of the second transistor; and a third transistor including a third drain electrode connected to the patterned resistance via the first pad of the display panel as a result of the combination, a third gate electrode connected to the differential amplifier, and a third source electrode connected to the second drain electrode of the second transistor, as also taught by Chen, for the advantage of using the electrical characteristic of an operational amplifier OP (high input impedance and low output impedance) to supply output current which is an accurate copy of input current in a current mirror (para[0024]).
Claim(s) 9-10 is/are rejected under 35 U.S.C. 103 as being unpatentable over Min et al. (US 2022/0215783), in view of Kim (US 2010/0283773).
Regarding claim 9, Min discloses all the claim limitations as applied above (see claim 1). In addition, Min discloses the circuit controller is configured to: select one of N reference voltages, N being a positive integer, as the reference voltage based on the voltage comparison result (regarding Figs. 3-4, “in order to control the magnitude of the reference resistance Rref according to a comparison result by the comparator 522, the circuit controller 523 supplies the reference resistance control signal RCS for controlling the switches SW.sub.1 to SW.sub.N of the reference resistance generation circuit 521”, and select voltages accordingly, which include 2N reference voltages, N clearly being a positive integer; para0050]-para[0051]; para[0056]). However, Min does not appear to expressly disclose the circuit controller is configured to: generate an N-bit reference voltage control signal for generating a selected reference voltage; and output the N-bit reference voltage control signal to the reference voltage generator.
Kim discloses a circuit controller configured to: generate an N-bit reference voltage control signal for generating a selected reference voltage (regarding Figs. 4 and 7-8, circuit 180 generates an N-bit signal for generating Vref, N clearly comprising positive integers; para[0089]-para[0093]; para[0095]-para[0096]); and output the N-bit reference voltage control signal to the reference voltage generator (regarding Figs. 4 and 7-8, circuit 180 outputs the N-bit signal to the reference voltage generation circuit 190; para[0089]-para[0093]; para[0095]-para[0096]).
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention, to combine the teachings in Min’s invention, with the teachings in Kim’s invention, to have the circuit controller is configured to: generate an N-bit reference voltage control signal for generating a selected reference voltage; and output the N-bit reference voltage control signal to the reference voltage generator, for the advantage of increasing accuracy while supplying a more constant current (para[0010]; para[0128]).
Regarding claim 10, Min and Kim disclose all the claim limitations as applied above (see claim 9). In addition, in the combination, Kim discloses the circuit controller is configured to: select one of the [2N in the combination] reference voltages less than a current reference voltage from among the [2N in the combination] reference voltages as a new reference voltage when the reference voltage is greater than the detection voltage (see Figs. 4 and 7-8; “The DAC 193 may select, e.g., one reference voltage among the variable reference voltages supplied from the reference voltage source 199 based on the reference voltage signals S0 through Sn-1 supplied from the register 188 of the calibration circuit 180”; in the circuit 180, “the comparator 182 may output a high level signal or a low level signal based on a comparison between the variable reference voltage Vsource and the test voltage V_RT” according to reference voltage signals S0 through Sn-1 based on the N-bit signal, N clearly comprising positive integers, “until the test voltage V_RT has a same voltage as the variable reference voltage Vsource”; this is, selecting a lower reference voltage when Vsource is greater than V_RT; para[0089]-para[0093]; para[0095]-para[0096]); and select one of the [2N in the combination] reference voltages greater than the current reference voltage from among the [2N in the combination] reference voltages as a new reference voltage when the reference voltage is less than the detection voltage (see Figs. 4 and 7-8; “The DAC 193 may select, e.g., one reference voltage among the variable reference voltages supplied from the reference voltage source 199 based on the reference voltage signals S0 through Sn-1 supplied from the register 188 of the calibration circuit 180”; in the circuit 180, “the comparator 182 may output a high level signal or a low level signal based on a comparison between the variable reference voltage Vsource and the test voltage V_RT” according to reference voltage signals S0 through Sn-1 based on the N-bit signal, “until the test voltage V_RT has a same voltage as the variable reference voltage Vsource”; this is, selecting a greater reference voltage when Vsource is less than V_RT; para[0089]-para[0093]; para[0095]-para[0096]).
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention, to have the circuit controller is configured to: select one of the voltages less than a current reference voltage from among the 2N voltages as a new reference voltage when the reference voltage is greater than the detection voltage; and select one of the voltages greater than the current reference voltage from among the 2N voltages as a new reference voltage when the reference voltage is less than the detection voltage, as also taught by Kim in the combination, for the advantage of supplying a more constant current (para[0010]).
Claim(s) 11 is/are rejected under 35 U.S.C. 103 as being unpatentable over Min et al. (US 2022/0215783), in view of Kim (US 2010/0283773), and further in view of Iriguchi et al. (US 2007/0085608).
Regarding claim 11, Min discloses all the claim limitations as applied above (see claim 1). However, Min does not appear to expressly disclose the reference voltage generator includes a digital-to-analog converter comprising a resistor string including a plurality of resistors connected in series between a first voltage and a second voltage, and a plurality of switches connected to respective nodes of the resistor string, wherein the first voltage corresponds to a value obtained by multiplying the reference current by a minimum value of the patterned resistance, wherein the second voltage corresponds to a value obtained by multiplying the reference current by a maximum value of the patterned resistance, and wherein the digital-to-analog converter is configured to select one of a plurality of node voltages of the resistor string as the reference voltage in response to the reference voltage control signal.
Kim discloses a reference voltage generator includes a digital-to-analog converter configured to select a reference voltage in response to a reference voltage control signal (see digital-to-analog converter DAC 193 in Figs. 8 or 10, configured to “select, e.g., one reference voltage among… variable reference voltages… based on the reference voltage signals S0 through Sn-1”; para[0095]).
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention, to combine the teachings in Min’s invention, with the teachings in Kim’s invention, to have the reference voltage generator includes a digital-to-analog converter configured to select the reference voltage in response to the reference voltage control signal, for the advantage of configuration that increases accuracy while supplying a more constant current (Abstract; para[0010]; para[0128]).
Min and Kim do not appear to expressly disclose the digital-to-analog converter comprising a resistor string including a plurality of resistors connected in series between a first voltage and a second voltage, and a plurality of switches connected to respective nodes of the resistor string, wherein the first voltage corresponds to a value obtained by multiplying the reference current by a minimum value of the patterned resistance, wherein the second voltage corresponds to a value obtained by multiplying the reference current by a maximum value of the patterned resistance, and wherein the digital-to-analog converter is configured to select one of a plurality of node voltages of the resistor string as the reference voltage in response to the reference voltage control signal.
Iriguchi discloses a digital-to-analog converter (see digital-to-analog converter in Fig. 7; para[0191]) comprising a resistor string including a plurality of resistors connected in series between a first voltage and a second voltage (see in Fig. 7 “connection terminals of a plurality of resistance elements (resistor array) 301 connected in series between power supply voltages VA and VB”; para[0115]; para[0192]), and a plurality of switches connected to respective nodes of the resistor string (see switches 302 in Fig. 7; para[0194]), wherein the first voltage corresponds to a value obtained by multiplying a reference current by a minimum value of the patterned resistance (regarding Fig. 7, it is clear that lower second potential (VB) (claimed first voltage) is obtained by multiplying a current applied from VA to VB by a minimum value of the resistor array 301 (Ohm’s Law (V=IR)); para[0115]; para[0192]), wherein the second voltage corresponds to a value obtained by multiplying the reference current by a maximum value of the patterned resistance (regarding Fig. 7, it is clear that higher first potential (VA) is obtained by multiplying the current applied from VA to VB by a maximum value of the resistor array 301 (Ohm’s Law (V=IR)); para[0115]; para[0192]), and wherein the digital-to-analog converter is configured to select one of a plurality of node voltages of the resistor string as a reference voltage in response to a reference voltage control signal (“At connection terminals of a plurality of resistance elements (resistor array) 301 connected in series between power supply voltages VA and VB, m voltages of V1 to Vm to be selectively applied… are generated”, and “The voltages are selected by switches 302, respectively”, according to “A selection signal… supplied to the switches 302, so that a voltage level or voltage levels in accordance with the selection signal is or are output”; para[0192]; para[0194]).
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention, to combine the teachings in Min’s and Kim’s combination, with the teachings in Iriguchi’s invention, to have the digital-to-analog converter comprising a resistor string including a plurality of resistors connected in series between a first voltage and a second voltage, and a plurality of switches connected to respective nodes of the resistor string, wherein the first voltage corresponds to a value obtained by multiplying the reference current by a minimum value of the patterned resistance, wherein the second voltage corresponds to a value obtained by multiplying the reference current by a maximum value of the patterned resistance, and wherein the digital-to-analog converter is configured to select one of a plurality of node voltages of the resistor string as the reference voltage in response to the reference voltage control signal, for the advantage of a configuration that allows variously selecting and outputting a lot of voltages levels from a small number of input voltages (para[0196]).
Response to Arguments
Applicant's arguments filed on 5/12/2026 have been fully considered but they are not persuasive.
Regarding claim 1, the applicant argues on pages 10-11 of the remarks that “Min does not disclose the configuration of the present application in which a reference current is applied to a patterned resistance to convert the resistance into a voltage, and the resulting voltage is compared with a reference voltage”. The examiner respectfully disagrees. As shown in the above rejection, Min discloses a current source generator configured to generate a reference current and apply the reference current to a patterned resistance via the first pad to generate a detection voltage corresponding to a resistance value of the patterned resistance (see in Fig. 2, “first pad part 111 receives a first voltage VDD from a power supply” clearly generating and applying a corresponding current to the resistance Rpanel via the first pad 111 to generate a voltage corresponding to a resistance value of the resistance Rpanel, measured at the second pad 113; “The crack resistance measurement circuit 520 is connected to the crack resistance circuit of the display panel 100 through the second pad part 113 to measure the crack resistance Rpanel of the crack resistance circuit”, clearly detected as a voltage to be input to comparator 522, as shown in Fig. 3; this is because a comparator does not inherently measure resistance, and to use resistance in a comparison, it must be first converted to a voltage, since what is compared by a comparator are actual voltages at each of its input terminals; para[0031]-para[0032]; para[0044]; para[0048]); a reference voltage generator configured to generate a reference voltage (regarding Figs. 2-4, see reference resistance generation circuit 521, clearly corresponding to a reference voltage accordingly, to be provided to comparator 522; this is because a comparator does not inherently measure resistance, and to use resistance in a comparison, it must be first converted to a voltage, since what is compared by a comparator are actual voltages at each of its input terminals; para[0049]-para[0050]); a comparator configured to compare a magnitude of the detection voltage generated by applying the reference current to the patterned resistance via the first pad to a magnitude of the reference voltage, and thereby output a voltage comparison result (regarding Fig. 3, “comparator 522 compares the crack resistance Rpanel of the display panel 100 with the reference resistance Rref of the reference resistance generation circuit 521 and outputs a resistance comparison result”, clearly representing a voltage comparison result; that is, the voltage measurement at the second pad 113 caused by the current applied to the resistance Rpanel via the first pad 111 is compared to the reference voltage provided by the reference resistance generation circuit 521, and the corresponding voltage is output to circuit controller 523; this is because a comparator does not inherently measure resistance, and to use resistance in a comparison, it must be first converted to a voltage, since what is compared by a comparator are actual voltages at each of its input terminals; para[0044]; para[0049]; para[0054]; para[0056]). Accordingly, Min does disclose a reference current is applied to a patterned resistance to convert the resistance into a voltage, and the resulting voltage is compared with a reference voltage.
Regarding claims 9-10, the applicant argues on pages 11-14 of the remarks that “Min changes a reference resistance to compare resistance values, and Kim
adjusts a reference voltage for load current calibration”, that “the second technical feature of the present application is based on the premise that the panel resistance is converted into a voltage by the reference current, and sets the expected range of the converted voltage itself as the reference voltage selection range of the DAC”, that “the second technical feature of the present invention is not disclosed in Min”, and that “none of the remaining art of record [disclose] the voltage range setting and DAC selection configuration for detecting a patterned resistance of a display panel as in the present invention”. In response to applicant's argument, the test for obviousness is not whether the features of a secondary reference may be bodily incorporated into the structure of the primary reference; nor is it that the claimed invention must be expressly suggested in any one or all of the references. Rather, the test is what the combined teachings of the references would have suggested to those of ordinary skill in the art. See In re Keller, 642 F.2d 413, 208 USPQ 871 (CCPA 1981). Moreover, in response to applicant's arguments against the references individually, one cannot show nonobviousness by attacking references individually where the rejections are based on combinations of references. See In re Keller, 642 F.2d 413, 208 USPQ 871 (CCPA 1981); In re Merck & Co., 800 F.2d 1091, 231 USPQ 375 (Fed. Cir. 1986).
Regarding newly added claim 11, it has been treated on the merits, as shown in the above rejection.
Conclusion
THIS ACTION IS MADE FINAL. Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
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/GLORYVID FIGUEROA-GIBSON/Patent Examiner, Art Unit 2628
/NITIN PATEL/Supervisory Patent Examiner, Art Unit 2628
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