DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Interpretation
The following is a quotation of 35 U.S.C. 112(f):
(f) Element in Claim for a Combination. – An element in a claim for a combination may be expressed as a means or step for performing a specified function without the recital of structure, material, or acts in support thereof, and such claim shall be construed to cover the corresponding structure, material, or acts described in the specification and equivalents thereof.
The following is a quotation of pre-AIA 35 U.S.C. 112, sixth paragraph:
An element in a claim for a combination may be expressed as a means or step for performing a specified function without the recital of structure, material, or acts in support thereof, and such claim shall be construed to cover the corresponding structure, material, or acts described in the specification and equivalents thereof.
The claims in this application are given their broadest reasonable interpretation using the plain meaning of the claim language in light of the specification as it would be understood by one of ordinary skill in the art. The broadest reasonable interpretation of a claim element (also commonly referred to as a claim limitation) is limited by the description in the specification when 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph, is invoked.
As explained in MPEP § 2181, subsection I, claim limitations that meet the following three-prong test will be interpreted under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph:
(A) the claim limitation uses the term “means” or “step” or a term used as a substitute for “means” that is a generic placeholder (also called a nonce term or a non-structural term having no specific structural meaning) for performing the claimed function;
(B) the term “means” or “step” or the generic placeholder is modified by functional language, typically, but not always linked by the transition word “for” (e.g., “means for”) or another linking word or phrase, such as “configured to” or “so that”; and
(C) the term “means” or “step” or the generic placeholder is not modified by sufficient structure, material, or acts for performing the claimed function.
Use of the word “means” (or “step”) in a claim with functional language creates a rebuttable presumption that the claim limitation is to be treated in accordance with 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph. The presumption that the claim limitation is interpreted under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph, is rebutted when the claim limitation recites sufficient structure, material, or acts to entirely perform the recited function.
Absence of the word “means” (or “step”) in a claim creates a rebuttable presumption that the claim limitation is not to be treated in accordance with 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph. The presumption that the claim limitation is not interpreted under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph, is rebutted when the claim limitation recites function without reciting sufficient structure, material or acts to entirely perform the recited function.
Claim limitations in this application that use the word “means” (or “step”) are being interpreted under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph, except as otherwise indicated in an Office action. Conversely, claim limitations in this application that do not use the word “means” (or “step”) are not being interpreted under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph, except as otherwise indicated in an Office action.
This application includes one or more claim limitations that do not use the word “means,” but are nonetheless being interpreted under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph, because the claim limitation(s) uses a generic placeholder that is coupled with functional language without reciting sufficient structure to perform the recited function and the generic placeholder is not preceded by a structural modifier. Such claim limitation(s) is/are:
“voltage control section” in claims 1-20
Because this/these claim limitation(s) is/are being interpreted under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph, it/they is/are being interpreted to cover the corresponding structure described in the specification as performing the claimed function, and equivalents thereof.
If applicant does not intend to have this/these limitation(s) interpreted under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph, applicant may: (1) amend the claim limitation(s) to avoid it/them being interpreted under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph (e.g., by reciting sufficient structure to perform the claimed function); or (2) present a sufficient showing that the claim limitation(s) recite(s) sufficient structure to perform the claimed function so as to avoid it/them being interpreted under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph.
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
Claim 20 is rejected under 35 U.S.C. 102(a)(1) or (a)(2) as being anticipated by Ayers et al. (US -2013/0258151-A1)
Regarding claim 20, Ayers teach a method of driving an imaging device (Ayers, Figure 2, image sensor 200) including:
a photoelectric converter (Ayers, Figure 4, a photodiode PD);
a floating diffusion (Ayers, Figure 4, a floating diffusion FD);
a transfer transistor (Ayers, Figure 4, a transfer gate transistor M3) configured to electrically couple the photoelectric converter and the floating diffusion to each other (Ayers, Figure 4; transistor M3 is the transfer gate transistor controlled by a transfer signal (TG) and functions to transfer charges on the photodiode PD to the floating diffusion (node 314) when the transfer signal is asserted, paragraph 0033)
a readout circuit (Ayers, Figure 4, a readout circuit comprised of a row select transistor M2, and a transistor M4 that is gated by the floating diffusion FD) and configured to output a first signal that is on a basis of electric charge stored in the floating diffusion; and transistor M4 is gated by the floating diffusion FD (node 314) to sense the charge transferred from the photodiode PD and to pass the output signal from the floating diffusion to the row select transistor M2, paragraph 0033),
a voltage control section configured to control supply of a voltage to the readout circuit, the method comprising:
supplying a first voltage (Ayers, Figure 4, power supply Vdd voltage) to the readout circuit in a case where the first signal is read while the transfer transistor is in an off-state (Ayers, in Figure 5 teaches a timing diagram, where a first signal (i.e. read light dependent pixel value in Figure 4, is performed when the row select transistor RS1 is turned on during the time period T7 and T8 when the transfer transistor gate driver signal TG is low, thereby turning off the transfer transistor is turned off).
While Ayers does not disclose, wherein the voltage control section is configured to:
execute control of supplying a first voltage to the first readout circuit in a case where the first signal is read while the first transfer transistor is in an off-state; and
execute control of supplying a second voltage that is lower than the first voltage to the first readout circuit in a case where the first signal is read while the first transfer transistor is in an on- state,
these limitations are considered to be contingent limitations due to the “ in a case where” language.
In the method claim of 1, according to contingent limitation, the broadest reasonable
interpretation of a method (or process) claim having contingent limitations requires only those steps that must be performed and does not include steps that are not required to be performed because the condition(s) precedent are not met. For example, assume a method claim requires step A if a first condition happens and step B if a second condition happens. If the claimed invention may be practiced without either the first or second condition happening, then neither step A or B is required by the broadest reasonable interpretation of the claim. If the claimed invention requires the first condition to occur, then the broadest reasonable interpretation of the claim requires step A. If the claimed invention requires both the first and second conditions to occur, then the broadest reasonable interpretation of the claim requires both steps A and B. See also MPEP 2111.04 (II).
Based on the above the method of step A that consists of having the transfer transistor in off-state and the step B when the transfer transistor is an on-state are not required to be met. Additionally, requirement of meeting the first condition A is adequate. The first condition of supplying a first voltage which is the Vdd supply as shown in Figure 4, while reading the first readout signal meets the requirement of anticipating the claim 1.
Allowable Subject Matter
Claims 1-19 allowed.
The following is examiner’s statement of reasons for allowance:
With respect to claims 1-8 the prior art does not teach or reasonable suggest: an imaging device comprising: a first photoelectric converter that photoelectrically converts light; a first floating diffusion configured to store electric charge; a first transfer transistor configured to electrically couple the first photoelectric converter and the first floating diffusion to each other; a first readout circuit configured to output a first signal that is on a basis of the electric charge stored in the first floating diffusion; Anda voltage control section configured to control supply of a voltage to the first readout circuit, wherein the voltage control section is configured to: execute control of supplying a first voltage to the first readout circuit in a case where the first signal is read while the first transfer transistor is in an off-state; and execute control of supplying a second voltage that is lower than the first voltage to the first readout circuit in a case where the first signal is read while the first transfer transistor is in an on- state, wherein the first readout circuit includes a first amplification transistor configured to output the first signal, and the voltage control section is configured to control a voltage to be supplied to the first amplification transistor, wherein the first amplification transistor is configured to output, on a basis of the second voltage, the first signal that is on a basis of the electric charge resulting from conversion at the first photoelectric converter while the first transfer transistor is in the on-state, wherein the first readout circuit includes a first reset transistor to be electrically coupled to the first floating diffusion, and the voltage control section is configured to control a voltage to be supplied to the first reset transistor, wherein the first reset transistor is configured to reset, on a basis of the second voltage, a voltage of the first floating diffusion while the first transfer transistor is in the on-state, further comprising a control section that performs control to add a capacitance to the first floating diffusion, wherein the voltage control section is configured 48 to execute the control of supplying the second voltage to the first readout circuit in a case where the capacitance is added to the first floating diffusion, wherein the voltage control section is configured to execute the control of supplying the first voltage to the first readout circuit in a case where no capacitance is added to the first floating diffusion.
The prior art teaches various imaging device comprising a first photoelectric converter, a first floating diffusion, a first transfer transistor, a first readout circuit and a voltage supply to the readout circuit.
For example, Abe et al. (US-2019/0280029-A1) teaches an imaging device 100 in Figure 2, that includes a first photoelectric converter 111, a first transfer transistor 112, a first floating diffusion formed in a diffusion layer of a substrate that is connected to a charge holding section 116 and the charge transfer section 112, a first readout circuit comprising of a signal generation section 114 and a selection section 115 and a pixel reset section 103.
The imaging device of Abe provides a supply voltage Vdd via power line. However, Abe does not teach supplying a first and second voltage with a voltage control section.
Abe teaches of a first amplification transistor (Abe, Figure 2, signal generation section 114) that is configured to output the first signal (Abe, The signal generation section 114 generates a signal as the image signal in accordance with a charge that has been held by the charge holding section 116, paragraph 0061) and the drain electrode of the signal generation section 114 is connected to the power line Vdd and a source electrode thereof is connected to a drain electrode of the selection section 115, paragraph 0055.
Abe teaches of first readout circuit (Abe, Figure 2, a first readout circuit comprising of a signal generation section 114 and a selection section 115 and a pixel reset section 103) includes a reset transistor in the pixel reset section 103, that is connected between the floating diffusion and the supply voltage Vdd. The gate of the pixel reset section transistor is connected to RST1. The signal RST1 are part of the signal line 101 and are powered by Vdd.
Abe further teaches a charge control section 113 that performs control to add a capacitance, i.e. a second charge holding section 117 to the first diffusion.
With respect to claims 1-18 the prior art does not teach or reasonable suggest: an imaging device comprising: a second photoelectric converter that photoelectrically converts light; a second floating diffusion configured to store electric charge; a second transfer transistor configured to electrically couple the second photoelectric converter and the second floating diffusion to each other; a second readout circuit configured to output a second signal that is on a basis of the electric charge stored in the second floating diffusion; Anda first transistor configured to electrically couple the first floating diffusion and the second floating diffusion to each other, wherein the voltage control section is configured to execute the control of supplying the second voltage to the first readout circuit in a case where the first transistor electrically couples the first floating diffusion and the second floating diffusion to each other, wherein the voltage control section is configured to execute the control of supplying the second voltage to the first readout circuit in a case where the first transfer transistor and the second transfer transistor are each in the on-state and the first transistor electrically couples the first floating diffusion and the second floating diffusion to each other, further comprising: a second photoelectric converter that photoelectrically converts light; Anda second transfer transistor configured to electrically couple the second photoelectric converter and the first floating diffusion to each other, wherein the voltage control section is configured to execute the control of supplying the second voltage to the first readout circuit in a case where the first signal is read while the first transfer transistor and the second transfer transistor are each in the on-state, a capacitor element configured to store electric charge; Anda second transistor configured to electrically couple the first floating diffusion and the capacitor element to each other, wherein the voltage control section is configured to execute the control of supplying the second voltage to the first readout circuit in a case where the second transistor electrically couples the first floating diffusion and the capacitor element to each other, wherein the first photoelectric converter comprises a photodiode buried and formed in a semiconductor substrate, further comprising a memory section buried and formed in the semiconductor substrate, wherein the memory section is configured to hold the electric charge resulting from conversion at the first photoelectric converter, wherein the voltage control section includes a circuit configured to select and output the first voltage or the second voltage, a resistor divider circuit, an amplifier circuit, or a DC-DC converter.
The prior art teaches various imaging device comprising a second photoelectric converter, a second floating diffusion, a second transfer transistor, a second readout circuit and a first transistor configured to electrically couple the first floating diffusion and the second floating diffusion to each other.
For example, Abe et al. (US-2019/0280029-A1) teaches an imaging device 100 in Figure 2, that includes a second photoelectric converter 121, a second charge transfer section 122, a second floating diffusion formed in a diffusion layer of a substrate that is connected to a second charge holding section 126 and a second charge transfer section 122, a second readout circuit comprising of a signal generation section 124 and a second selection section 125. Abe also teaches a first transistor (i.e. a pixel connection section 104) configured to electrically couple the first floating diffusion and the second floating diffusion to each other.
Abe further teaches the first photoelectric converter (i.e. the pixels) are formed in semiconductor substrate. The pixels are assumed to be formed in a well region of a P-type semiconductor, paragraph 0116.
For example, Yorikado, Yuhi (US-2021/0352232-A1) teaches in Figure 3A, a similar solid-state imaging device that includes a unit pixel 900, that has a first photoelectric converter 901, a first floating diffusion 903, a first transfer transistor 902, and a first readout circuit comprising of a first amplification transistor 905, a selection switch 906 and a reset transistor 904.
Yorikado further teaches of the first readout circuit including the first amplification transistor configured to output the first signal to a vertical signal line VSL, the unit pixel 900, as a circuit that amplifies a voltage that is read out from each unit pixel 900 via a vertical signal line VSL, paragraph 0063.
Yorikado teaches a voltage control section in Figure 11, where a voltage control is executed via switches SW15, SW16, SW17. The switches SW15, SW16 and SW17 controls applying supply voltages VDD and Vrst to the readout circuit that is comprised of an amplification transistor 1052, a selection transistor 1062 and a reset transistor 102. However, the voltage control section in Yorikado is not included in the solid-state imaging device.
However, Yorikado does not teach or fails to reasonably suggest execute control of supplying a first voltage to the first readout circuit in a case where the first signal is read while the first transfer transistor is in an off-state; and execute control of supplying a second voltage that is lower than the first voltage to the first readout circuit in a case where the first signal is read while the first transfer transistor is in an on- state.
Kato, Atsushi (US-2023/0007202-A1) teaches in Figure 3, a similar imaging element, that includes one of plurality of pixels 111 which are arrayed in a matrix. The pixel circuit includes a transfer transistor Ttrg, a photodiode PD, and floating diffusion node FD, and a readout circuit comprising of an amplification transistor Tamp, a selection transistor Tsel and a reset transistor Trst. The amplification transistor is connected to a voltage supply VDD and the selection transistor Tsel. The reset transistor Trst is connected to a plurality of voltage supply VDR1 and VDR2 via voltage control section comprising of switches SW1 and SW2.
Kato fails to teach or reasonably suggest to include the supply for the readout circuit, the amplification transistor Tamp connected to the plurality of the supplies VDR1 and VDR2.
Regarding claim 19, prior art fails to teach or reasonably suggest an imaging system comprising: an imaging device; and a voltage control section configured to control supply of a voltage to the imaging device, 51 wherein the imaging device includes: a photoelectric converter that photoelectrically converts light; a floating diffusion configured to store electric charge; a transfer transistor configured to electrically couple the photoelectric converter and the floating diffusion to each other; and a readout circuit configured to output a first signal that is on a basis of the electric charge stored in the floating diffusion, and the voltage control section is configured to: execute control of supplying a first voltage to the readout circuit in a case where the first signal is read while the transfer transistor is in an off-state; and execute control of supplying a second voltage that is lower than the first voltage to the readout circuit in a case where the first signal is read while the transfer transistor is in an on-state.
Yorikado, Yuhi (US-20210352232-A1) teaches a similar solid-state imaging device that includes a unit pixel 900, that has a first photoelectric converter 901, a first floating diffusion 903, a first transfer transistor 902, and a first readout circuit comprising of a first amplification transistor 905, a selection switch 906 and a reset transistor 904.
Yorikado further teaches of the first readout circuit including the first amplification transistor configured to output the first signal to a vertical signal line VSL, the unit pixel 900, as a circuit that amplifies a voltage that is read out from each unit pixel 900 via a vertical signal line VSL, paragraph 0063.
Yorikado further teaches a separate voltage control section in Figure 11, where a voltage control is executed via switches SW15, SW16, SW17. The switches SW15, SW16 and SW17 controls applying supply voltages VDD and Vrst to the readout circuit that is comprised of an amplification transistor 1052, a selection transistor 1062 and a reset transistor 102.
However, Yorikado fails to teach or reasonably suggest execute control of supplying a first voltage to the first readout circuit in a case where the first signal is read while the first transfer transistor is in an off-state; and execute control of supplying a second voltage that is lower than the first voltage to the first readout circuit in a case where the first signal is read while the first transfer transistor is in an on- state.
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant’s disclosure. The following show additional prior art systems/methods for imaging apparatus:
YORIKADO; YUHI US-20210352232-A1
KATO; ATSUSHI US-20230007202-A1
ABE; Takashi US-20190280029-A1
MURAO; Fumihide US-20170187972-A1
Sakakibara; Masaki US-20130307837-A1
IKEDA; Masataka US-20230208658-A1
Any inquiry concerning this communication or earlier communications from the examiner should be directed to MEHEDI NMN HASSAN whose telephone number is (571)272-7173. The examiner can normally be reached 8am-5pm.
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If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Sinh Tran can be reached at 5712727564. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/MEHEDI NMN HASSAN/Examiner, Art Unit 2637
/SINH TRAN/
Supervisory Primary Examiner, Art Unit 2637
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