Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Detailed Action
Claim Rejections - 35 USC § 112
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claims 2-6 and 10-14 are rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor, or for pre-AIA the applicant regards as the invention.
Claims 2 and 10 comprise the limitation, “architectural voltage mitigation” and claims 5 and 13 comprise the limitation, “architectural mitigations”, emphasis added. The terms are vague, unclear, and not commonly known or used in the art of power control. Therefore, these terms do not provide the Examiner with a basis for establishing metes and bounds for comparing against the prior art.
Claims 2, 4, 5, 10, 12, and 13 are indefinite due to their limitations attempting to define the subject matter in terms of an intended use or result. Each of the claims comprise limitations stating that the generation of the synthetic voltage signal is “to compensate for”, followed by various “mitigations”. However, neither the device nor processor core are claimed as performing or being configured to perform the specific mitigations. Therefore, each of these claims will be treated as the synthetic voltage signal is generated to facilitate the transition of the processing core from an idle mode (low-power state) to an active mode (high-power state).
Claims 6 and 14 comprise the limitation, “causes the power manager to increase current supplied to the processing core in fewer steps”. In the context of “increasing current supplied”, it is unclear what the “steps” represent. For examination purposes, the “steps” will be interpreted as a unit of time to help facilitate the scope of the independent claims.
Claim Objections
Claim 9 is objected to because of the following informalities: Line 2 states, “the comprising,”. The Examiner suggests either removing the word “the”, or adding the word “method” to read, “the method comprising”. Appropriate correction is required.
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claims 1-16 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Dinh, U.S. PGPUB No. 2022/0236754 (cited in the IDS filed 8/28/2025).
Per Claim 1, Dinh discloses:
a device (Paragraphs 17 and 22; electronic apparatus) comprising:
a processing core (CPU 720) configured to initiate a transition from executing in a low-power state to executing in a high-power state (Paragraphs 36-38 discuss high speed processing pipelines operating in parallel. The pipelines can be loaded up for processing after being idle. This represents a transition from a low-power state to a high-power state.); and
a power manager (voltage regulator 120) configured to increase current supplied to the processing core when the processing core transitions from the low-power state to the high-power state, wherein the device is configured to inject a synthetic voltage signal into a voltage feedback line (control feedback circuitry 740) of the power manager to cause the power manager to react sooner to the transition by increasing the current supplied to the processing core according to the synthetic voltage signal (Paragraphs 36-39; An anticipatory load signal 712 can be activated prior to transitioning the high speed processing pipelines from an idle to an active state. The anticipatory load signal 712 is provided to the voltage regulator 712 so it can properly account for the increased load current ILOAD required by the state transition. “By generating the load signal in anticipation of such a change in load, the CPU may provide an early warning signal of sorts, causing the voltage regulator 120 to adjust the supply voltage to compensate.” –Paragraph 40, “the load signal may result in faster regulator response time”; Paragraph 49, Fig. 6).
Per Claim 2, Dinh discloses the device of claim 1, wherein the device is configured to generate the synthetic voltage signal to compensate for architectural voltage mitigations that limit how quickly instructions can be executed when the processing core transitions to the high-power state (Please see the 112 rejection above. Dinh, Paragraphs 36-40, details how a voltage regulator 120 receives an anticipatory load control signal from feedback circuit 740 to prepare for an anticipated load increase due to transitioning a number of high-speed processing pipelines from an idle state to an active state.).
Per Claim 3, Dinh discloses the device of claim 2, wherein the synthetic voltage signal has a trajectory that matches an expected voltage drop due to transitioning to the high-power state (Figure 3; “ANTICIPATORY LOAD CONTROL” signal matches that of the expected voltage drop.).
Per Claim 4, Dinh discloses the device of claim 1, wherein the device is configured to generate the synthetic voltage signal to compensate for frequency throttling mitigations that limit a clock frequency of the processing core when the processing core transitions to the high-power state (Please see the 112 rejection above. Dinh, paragraphs 36-40, details how a voltage regulator 120 receives an anticipatory load control signal from feedback circuit 740 to prepare for an anticipated load increase due to transitioning a number of high-speed processing pipelines from an idle state to an active state. Additionally, Dinh teaches throttling frequencies, Paragraph 56).
Per Claim 5, Dinh discloses the device of claim 4, wherein the device is configured to generate different synthetic voltage signals to compensate for frequency throttling mitigations and for architectural mitigations (Please see the 112 rejection above. Dinh, paragraphs 36-40, details how a voltage regulator 120 receives an anticipatory load control signal from feedback circuit 740 to prepare for an anticipated load increase due to transitioning a number of high-speed processing pipelines from an idle state to an active state. Additionally, Dinh teaches throttling frequencies, Paragraph 56).
Per Claim 6, Dinh discloses the device of any one of claim 1, wherein injecting the synthetic voltage signal causes the power manager to increase current supplied to the processing core in fewer step ups than would be required without the synthetic voltage signal (Paragraph 39; Generating the load signal in anticipation of an increase in load allows the CPU 720 to provide an early warning signal to cause the voltage regulator 120 to adjust the supply voltage to compensate. This early warning and compensation reads on the claimed “fewer steps”.).
Per Claim 7, Dinh discloses the device of claim 1, wherein injecting the synthetic voltage signal reduces an amount of clock frequency throttling on the processing core when transitioning to the high-power state (Paragraph 33 discusses clock rate throttling as a method for reducing power consumption and also notes that this may not be efficient given different workloads and operating conditions. Paragraph 34 notes how the current invention, detailed in paragraphs 36-40, more efficiently manages the system power and energy consumption, which in effect, could represent a reduction or elimination of the clock rate throttling technique.).
Per Claim 8, Dinh discloses the device of any one of claim 1, wherein injecting the synthetic voltage signal causes a core frequency of the processing core to regain a voltage level from the low-power state faster than without using synthetic voltage signals (Paragraphs 36-40, Figure 3; “faster regulator response time”).
Per Claims 9-16, please refer to the above rejection of claims 1-8 as the limitations are substantially similar and the mapping of the reference to the limitations is equally applicable.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to BRIAN T MISIURA whose telephone number is (571)272-0889 - (Direct Fax: 571-273-0889). The examiner can normally be reached on M-F: 8-4:30PM.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Andrew Jung can be reached on (571) 272-3779. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/Brian T Misiura/
Primary Examiner, Art Unit 2175
