DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Remarks
This Office Action is in response to the Election/Restriction filed on 07/23/26. Examiner acknowledged that claim 1-15 are pending.
Applicant's election with traverse of Specie A (Fig. 2) in the reply filed on 07/23/26 is acknowledged. The traversal is on the ground(s) that all of the claims can be examined together without posing a serious burden. This is not found persuasive because applicant admitted that claim 1 directed to Fig. 2. However, claims 5-7 recites a “third node” which is illustrated as a different specie by Fig. 5.
The requirement is still deemed proper and is therefore made FINAL.
The information disclosure statement (IDS) submitted on 03/12/25 is in compliance with the provisions of 37 CFR 1.97. Accordingly, the information disclosure statement is being considered by the examiner.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 1-3, 10-15 are rejected under 35 U.S.C. 103 as being unpatentable over Lopez (US 2014/0117868).
Regarding Claim 1, Lopez teaches a driver (Fig. 5b: 50e) for driving a load (Fig. 5b : 22), the driver comprising: a first node (Fig. 5b: 53) adapted to be coupled to a fluctuating voltage (Fig. voltage from Lo); a second node (Fig. 5b: 70a) adapted to be coupled to a stable voltage (Fig. 5b: voltage from rectifier); a switched mode power converter (Fig. 5b: 60) configured to convert the fluctuating voltage into the stable voltage or to convert the stable voltage into the fluctuating voltage; a first ceramic capacitor (Fig. 5b: Co) coupled to the first node; and a second ceramic capacitor (Fig. 5b: Cs) coupled between the first node and the second node.
Lopez does not explicitly teach in Fig. 5b wherein the second ceramic capacitor is arranged to provide a dominant capacitance between the first node and the second node and the first ceramic capacitor is arranged to provide a dominant capacitance to the first node. However, Cs provides Vc voltage which is higher than the input Vr and output load Vo; Co would provide a stable voltage across the LED load. It would have been obvious to one of ordinary skill in the art before the effective filling of the claimed invention to combine the teachings of Lopez in order to provide a main voltage across the load as well as an intermediate voltage stabilization between different nodes.
Regarding Claim 2, Lopez teaches the driver according to claim 1, wherein a ratio between a capacitance of the first ceramic capacitor and a capacitance of the second ceramic capacitor is based on a ratio between a peak voltage of the fluctuating voltage and an amplitude of the stable voltage ([0074] “the storage capacitor Cs can be as low as 1 .mu.F (i.e. 100 nF/W) while guaranteeing a constant output power and a high power factor”; NOTE: it would have been obvious to one of ordinary skill in the art to select the appropriate capacitance ratio between fluctuating voltage and stable voltage for the circuit to operate properly Figs. 6-10).
Regarding Claim 3, Lopez teaches the driver according to claim 1, wherein the switched mode power converter is a boost converter [0054] “a switched mode power supply (SMPS), e.g. a boost converter”) wherein the first node is coupled to an input (Fig. 5b: ih entering the switching 60) of the switched mode power converter and wherein the second node is coupled to an output of the switched mode power converter and the load (Fig. 5b: 70a is the output of switch 60 coupled to the negative side of the load via capacitor Cm).
Regarding Claim 10, Lopez teaches the driver according to claim 1, wherein the switched mode power converter is arranged to provide power factor correction ([0028] “their applications to power factor correction in switching converters”).
Regarding Claim 11, Lopez teaches the driver according to claim 1, wherein the switched mode power converter is a synchronous switched mode power converter ([0096] “only a single switch (e.g., a MOSFET)”; NOTE: synchronous uses MOSFET transistors).
Regarding Claim 12, Lopez teaches the driver according to claim 1, wherein the first ceramic capacitor and the second ceramic capacitor have a substantial identical capacitance (the two capacitors have similar voltage since they are connected to the same node therefore needing similar capacitance).
Regarding Claim 13, Lopez teaches the driver according to claim 1, further comprising a rectifier circuit (Fig. 5a: 62) adapted to rectify an alternating current (Fig. 5a: 20), AC, voltage into a rectified voltage (Fig. 5a: vr), wherein the rectified voltage is the fluctuating voltage.
Regarding Claim 14, Lopez teaches a system comprising the driver according to claim 1 and the load (Fig. 5a: 22).
Regarding Claim 15, Lopez teaches the system according to claim 14, wherein the load is a semiconductor lighting load and wherein the system is a luminaire or a lamp (Fig. 5a: 22 is LED).
Claim(s) 8 is/are rejected under 35 U.S.C. 103 as being unpatentable over Lopez as applied to claim 1 in view of Wong (US 2019/0006937).
Regarding Claim 8, Lopez teaches the driver according to claim 1, wherein the first ceramic capacitor and the second ceramic capacitor except being multilayer ceramic capacitors, MLCC capacitors.
Wong is in the field of load control using time and frequency domain signal condition (abstract) and teaches capacitor being multilayer ceramic capacitors, MLCC capacitors ([0007] “capacitor except being multilayer ceramic capacitors, MLCC capacitors.”).
It would have been obvious to one of ordinary skill in the art before the effective filling of the claimed invention to modify the device of Lopez with MLCC as taught by Wong in order to use MLCC capacitors since the can provide smaller ripple voltage amplitudes.
Claim(s) 9 is/are rejected under 35 U.S.C. 103 as being unpatentable over Lopez as applied to claim 1 in view of Xiong (US 2016/0270165).
Regarding Claim 9, Lopez teaches the driver according to claim 1 except the first ceramic capacitor and the second ceramic capacitor are of the X7R type.
Xiong is in the field of lighting (abstract) and teaches the first ceramic capacitor and the second ceramic capacitor are of the X7R type ([0361] “the capacitor is the X7R multi-layer ceramic chip capacitor”).
It would have been obvious to one of ordinary skill in the art before the effective filling of the claimed invention to modify the device of Lopez with Xiong with X7R capacitors as taught in order to have wide application since the capacitor can withstand a wide range of temperatures.
Allowable Subject Matter
Claims 4-7 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to HENRY T LUONG whose telephone number is (571)270-7008. The examiner can normally be reached Monday-Thursday: 8:00-6:00.
Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Alexander Taningco can be reached at (571) 272-8048. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/Henry Luong/Primary Examiner, Art Unit 2845
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