Prosecution Insights
Last updated: October 24, 2026
Application No. 19/111,521

SLOT-COUPLING TYPE COUPLER

Non-Final OA §102§103
Filed
Mar 13, 2025
Priority
Sep 16, 2022 — nonprovisional of PCTJP2022034781
Examiner
COLE, VICTOR
Art Unit
2843
Tech Center
2800 — Semiconductors & Electrical Systems
Assignee
Nippon Telegraph and Telephone Corporation
OA Round
1 (Non-Final)
92%
Grant Probability
Favorable
1-2
OA Rounds
11m
Est. Remaining
99%
With Interview

Examiner Intelligence

Grants 92% — above average
92%
Career Allowance Rate
46 granted / 50 resolved
+24.0% vs TC avg
Moderate +10% lift
Without
With
+10.1%
Interview Lift
resolved cases with interview
Typical timeline
2y 6m
Avg Prosecution
35 currently pending
Career history
91
Total Applications
across all art units

Statute-Specific Performance

§101
0.4%
-39.6% vs TC avg
§103
32.3%
-7.7% vs TC avg
§102
34.7%
-5.3% vs TC avg
§112
25.8%
-14.2% vs TC avg
Black line = Tech Center average estimate • Based on career data from 50 resolved cases

Office Action

§102 §103
DETAILED ACTION Election/Restrictions Applicant’s election of Group I, claims 8-20, in the reply filed on 8/4/2026 (“Reply”) is acknowledged. Rather than pointing out any errors in the restriction requirement mailed 6/9/2026, the applicant has amended the claims and argued that the amended claims overcome the reference cited by the examiner in the restriction requirement (Reply at 7). This argument is found not persuasive because it relates to the patentability of the claims over the cited reference and does not address the supposed errors in the restriction requirement. Because applicant did not distinctly and specifically point out the supposed errors in the restriction requirement, the election has been treated as an election without traverse. MPEP § 818.01(a). The requirement is still deemed proper and is therefore made FINAL. Accordingly, Claims 21-27 are withdrawn from further consideration pursuant to 37 CFR 1.142(b), as being drawn to a nonelected invention, there being no allowable generic or linking claim. Claims 21-27 will be considered for rejoinder once the claim(s) they depend upon are found allowable. Information Disclosure Statement The information disclosure statement(s) (IDS) submitted 3/13/2025 is/are in compliance with the provisions of 37 CFR 1.97 and being considered by the examiner. Specification The title of the invention is not descriptive. A new title is required that is clearly indicative of the invention to which the claims are directed. The following title is suggested: SLOT-COUPLING COUPLER USING COMPLEMENTARY METAMATERIAL CELLS. Appropriate correction is required. Claim Rejections - 35 USC § 102 The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action: A person shall be entitled to a patent unless – (a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention. Claims 8, 10, 12, 14-16, 18 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Y.-H. Ren et al., A Broadband Magnetic Coupling Microstrip to Waveguide Transition Using Complementary Split Ring Resonators, IEEE Access, vol. 7, pp. 17347-17353, 2019 (“Ren”). Ren discloses in Figs. 2-5, 9 and the corresponding description: Claims 8, 12, 15 A slot-coupling type coupler (Fig. 3, microstrip to waveguide transition, pp. 17347-17352) for connecting a high-frequency circuit (p. 17347, microwave integrated circuits (MMICs)) to a waveguide tube (Fig. 3a, p. 17348, WR-90 waveguide), comprising: a substrate (Fig. 3, annotated, p. 17348, microstrip structure implemented on a 0.5mm-thick F4BM-2 substrate), at least a part of the substrate being inserted into the waveguide tube (Fig. 3a); and a conductor patch (Fig. 3, two symmetrical step-like patches, metal ground plane) on the substrate and configured to emit a high-frequency wave generated by the high-frequency circuit into the waveguide tube (pp. 17347-8, If the microstrip port is energized, there is a high frequency alternating current around the ring, which excites alternating magnetic field in the waveguide); the conductor patch comprising a first conductor patch on a first side of the substrate (one step-like patch), the first conductor patch comprising a plurality of complementary metamaterial cells (Figs. 3, 9; complementary split ring resonators, CSRRs), each complementary metamaterial cell including one or more conductor portions and one or more gaps (Figs. 3, 9; p. 17352, Table 1, CSRR outer ring, inner ring and spacing between them), the first conductor patch further comprising a continuous metal plane between adjacent ones of the plurality of complementary metamaterial cells (Fig. 3, annotated, p. 17348, CSRRs arrays are etched out on F4BM-2 substrate, whose copper layer correspond to the continuous metal plane between adjacent CSRRs). Claims 10 and 16 wherein the conductor patch is configured to change a mode of the high-frequency wave (p. 17350, mode transformation between TE10 and quasi-TEM, and impedance matching between a rectangular waveguide and microstrip are two major functions of the microstrip to waveguide transition.”). Claims 14 and 18 wherein the conductor patch further comprises a second conductor patch (Fig. 3, metal ground plane) on a second side of the substrate opposite the first side; the second conductor patch is opposite the first conductor patch via the substrate and does not include a complementary metamaterial cell (the metal ground plane does not include any CSRRs, is located on the opposite side of the substate and is, therefore, at least indirectly opposite the first conductor patch via the substrate); and the first conductor patch is grounded (Fig. 3, p. 17348, “the waveguide inner surface is in contact with the ground plane and the lower edge of the patches”, which means the first conductor patch is grounded). PNG media_image1.png 839 493 media_image1.png Greyscale Claim Rejections - 35 USC § 103 The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action: A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made. The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows: 1. Determining the scope and contents of the prior art. 2. Ascertaining the differences between the prior art and the claims at issue. 3. Resolving the level of ordinary skill in the pertinent art. 4. Considering objective evidence present in the application indicating obviousness or nonobviousness. This application currently names joint inventors. In considering patentability of the claims the examiner presumes that the subject matter of the various claims was commonly owned as of the effective filing date of the claimed invention(s) absent any evidence to the contrary. Applicant is advised of the obligation under 37 CFR 1.56 to point out the inventor and effective filing dates of each claim that was not commonly owned as of the effective filing date of the later invention in order for the examiner to consider the applicability of 35 U.S.C. 102(b)(2)(C) for any potential 35 U.S.C. 102(a)(2) prior art against the later invention. Claims 8, 9, 11, 13, 15, 17, 20 are rejected under 35 U.S.C. 103 as being unpatentable over U.S. Patent Application Publication No. 2011/0140811, published 6/16/2011 (“Leiba”) in view of Ren. Regarding claims 8 and 15, Leiba discloses in Figs. 3, 17, 19, 20, 21, 24 and the corresponding description: A slot-coupling type coupler for connecting a high-frequency circuit to a waveguide tube (Figs. 17-21, a system enabling interface between a millimeter-wave integrated circuit mounted on a PCB and a waveguide, Abstract, ¶¶4-13), comprising: a substrate (PCB substrate), at least a part of the substrate being inserted into the waveguide tube (Figs. 20, 21, at least some PCB lamina are inserted into waveguides 507 or 529; in addition, as shown in Figs. 6B, 11C, PCB may be attached to a discrete waveguide 195 or 301); and a conductor patch (probe patches, for example, 163, 166, 166b, 166d, 312, 502, 525, 572u, 575p, 628) on the substrate and configured to emit a high-frequency wave generated by the high-frequency circuit into the waveguide tube (¶¶7, 10-13, 80); the conductor patch comprising a first conductor patch on a first side of the substrate (probe patches as indicated above and shown in the corresponding figures). Leiba does not disclose the first conductor patch comprising a plurality of complementary metamaterial cells, each complementary metamaterial cell including one or more conductor portions and one or more gaps, the first conductor patch further comprising a continuous metal plane between adjacent ones of the plurality of complementary metamaterial cells. However, as set forth above, Ren, in the same field of endeavor, discloses a similar microstrip-to-waveguide transition, including the conductor patch comprising a first conductor patch on a first side of the substrate (one step-like patch), the first conductor patch comprising a plurality of complementary metamaterial cells (Figs. 3, 9; complementary split ring resonators, CSRRs), each complementary metamaterial cell including one or more conductor portions and one or more gaps (Figs. 3, 9; p. 17352, Table 1, CSRR outer ring, inner ring and spacing between them), the first conductor patch further comprising a continuous metal plane between adjacent ones of the plurality of complementary metamaterial cells (Fig. 3, annotated, p. 17348, CSRRs arrays are etched out on F4BM-2 substrate, whose copper layer correspond to the continuous metal plane between adjacent CSRRs). It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to have modified the microstrip-to-waveguide transition of Leiba by adding a plurality of complementary metamaterial cells to its probe patches for the benefit of broader bandwidth and increased efficiency, as taught by Ren (Abstract). Leiba in view of Ren discloses: Claims 9 and 17 a coplanar waveguide including a portion of the substrate in front of the conductor patch, the coplanar waveguide being configured to transmit the high-frequency wave (Leiba, Figs. 3D, 19B, ¶¶82, 146). Claim 11 wherein the high-frequency circuit is on the substrate (Leiba, Figs. 17, 19-21, millimeter-wave IC 471, 509 or 521 mounted on the PCB). Claims 13 and 20 wherein the high-frequency circuit is a differential output circuit (Leiba, Fig. 19C, ¶169, millimeter-wave IC 471v) including a first output terminal (479a) and a second output terminal (479b); the first conductor patch (first probe patch 575p) is connected to the first output terminal (via 575d); and the conductor patch further comprises a second conductor patch (second probe patch 575p) on the first side of the substrate (Fig. 19C, both probe patches 575p are coplanar), the second conductor patch having a shape symmetrical to the first conductor patch (Fig. 19C, both probe patches 575p are symmetrical), and connected to the second output terminal (via 576d). Allowable Subject Matter Claim 19 is objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims. Conclusion The prior art made of record and not relied upon is considered pertinent to applicant's disclosure. U.S. Patent Application Publication No. 2008/0030284, published 2/7/2008 (“Tanaka”) discloses a line-waveguide converter with a backside electrode disposed on a first face of a dielectric substrate, a waveguide attached to a second face of the dielectric substrate opposite the first face including multiple cells disposed inside the waveguide (Figs. 4-5, Abstract, ¶¶40-60). H.A. Jang et al., Size Reduction of Patch Antenna Array Using CSRRs Loaded Ground Plane, Progress In Electromagnetics Research Symposium Proceedings, March 27-30, 2012, pp. 1487-1489 (“Jang”) discloses a two-elements microstrip patch array antenna including two symmetrical patches on one side of a dielectric substrate and two corresponding, CSRRs-loaded patches etched on the ground plane of the antenna (Figs. 1-3). Any inquiry concerning this communication or earlier communications from the examiner should be directed to VICTOR COLE, telephone number (571) 272-4686. The examiner can be reached Monday-Friday, 9AM-5PM ET. Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at www.uspto.gov/interviewpractice. If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, ANDREA LINDGREN BALTZELL, can be reached at (571) 272-5918. The fax phone number for the organization where this application or proceeding is assigned is (571) 273-8300. Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit www.uspto.gov/patents/apply/patent-center for more information about Patent Center and www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at (866) 217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call (800) 786-9199 (IN USA OR CANADA) or (571) 272-1000. /VICTOR COLE/ Examiner, Art Unit 2843 /ANDREA LINDGREN BALTZELL/Supervisory Patent Examiner, Art Unit 2843
Read full office action

Prosecution Timeline

Mar 13, 2025
Application Filed
Sep 29, 2026
Non-Final Rejection mailed — §102, §103 (current)

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Study what changed to get past this examiner. Based on 5 most recent grants.

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Prosecution Projections

1-2
Expected OA Rounds
92%
Grant Probability
99%
With Interview (+10.1%)
2y 6m (~11m remaining)
Median Time to Grant
Low
PTA Risk
Based on 50 resolved cases by this examiner. Grant probability derived from career allowance rate.

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