DETAILED ACTION
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
This Office Action is responsive to communication(s) filed on 03/14/2025. Claims 1-20 have been examined and are pending in this application.
Information Disclosure Statement
The information disclosure statements (IDSs) were submitted on 04/08/2026 and 10/03/2025. The submission is in compliance with the provisions of 37 CFR 1.97. Accordingly, the information disclosure statements are being considered by the examiner.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claims 1-5, 9-13, and 17-20 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Zhou US 2011/0302376 (“Zhou”).
As per independent claim 1, Zhou teaches A computer-implemented method for concurrently accessing memory banks of a hardware accelerator (“A method of accessing and storing data in the plurality of data memory banks” para 0009. “simultaneous read and write operations” para 0026), the method comprising:
receiving a plurality of requests, each of the plurality of requests being used to access a tile memory of the hardware accelerator (“simultaneous read and write requests are pending (i.e., a read request and a write request in [is] received in the same clock cycle by controller 120).” Para 0036);
for each of the plurality of requests: identifying, in the request, a respective logical address represented by a sequence of bits (“Next, in step 222, controller 120 checks to see if BRL [logical bank number for read] equals BWL [logical bank number for write]. If they are not equal, different logical banks are being read and written in the same cycle” para 0037 and FIGS. 1 and 2);
obtaining a first subset of bits from the sequence of bits (“The controller 120 passes the read and write logical bank numbers, BRL, BWL to mapping memory 104 via buses 122, 124, respectively,” para 0022 and FIG. 1. “The read and write addresses are of the form [Logical Bank Number].[Offset Address], where ‘.’ indicates a concatenation of the logical bank number and the offset address.” Para 0020);
generating, based on a bank generation function that uses the first subset of bits, a respective bank identifier that identifies a particular bank among a plurality of physical memory banks of the tile memory (“and retrieves from the mapping memory 104 the read and write physical bank numbers, BRP, BWP, via buses 126, 128, respectively,” para 0022 and FIG. 1);
processing each of the plurality of requests using the respective bank identifier that is generated for the request (“and retrieves from the mapping memory 104 the read and write physical bank numbers, BRP, BWP, via buses 126, 128, respectively,” para 0022 and FIG. 1);
concurrently accessing, during a clock cycle, multiple distinct physical memory banks of the tile memory in response to processing each of the plurality of requests (“If they are not equal, different logical banks are being read and written in the same cycle” para 0037 and FIGS. 1 and 2. “simultaneous read and write operations” para 0026).
As per dependent claim 2, Zhou discloses the method of claim 1. Zhou teaches wherein concurrently accessing the multiple distinct physical memory banks comprises: accessing, for a particular stride value, the multiple distinct physical memory banks during a single clock cycle (“The read and write addresses are of the form [Logical Bank Number].[Offset Address], where ‘.’ indicates a concatenation of the logical bank number and the offset address.” Para 0020. “If they are not equal, different logical banks are being read and written in the same cycle” para 0037 and FIGS. 1 and 2).
As per dependent claim 3, Zhou discloses the method of claim 2. Zhou teaches wherein the particular stride value is a memory access stride that is equal to a difference between particular rows of the same physical memory bank (“The read and write addresses are of the form [Logical Bank Number].[Offset Address], where ‘.’ indicates a concatenation of the logical bank number and the offset address.” Para 0020).
As per dependent claim 4, Zhou discloses the method of claim 3. Zhou teaches wherein concurrently accessing the multiple distinct physical memory banks comprises: accessing the multiple distinct physical memory banks without a bank conflict (“If they are not equal, different logical banks are being read and written in the same cycle” para 0037 and FIGS. 1 and 2).
As per dependent claim 5, Zhou discloses the method of claim 4. Zhou teaches wherein a bank conflict is when two or more requesters request access to the same physical memory bank of the tile memory during the same clock cycle (“The controller also provides two updated write physical bank numbers to the mapping memory 104 when a read and write conflict occurs,” para 0022).
As per claims 9-13, these claims are respectively rejected based on arguments provided above for similar rejected claims 1-5. For processor and memory see para 0042 of Zhou. For hardware accelerator, see para 0018 of Zhou (packet processor or video graphics system).
As per claims 17-20, these claims are respectively rejected based on arguments provided above for similar rejected claims 1-4. For computer program product on a non-transitory computer readable storage medium, see para 0042 of Zhou.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 6 and 14 are rejected under 35 U.S.C. 103 as being unpatentable over Zhou in view of Ruckerbauer et al. US 2009/0046534 (“Ruckerbauer”).
As per dependent claim 6, Zhou discloses the method of claim 5. Zhou may not explicitly disclose, but in an analogous art in the same field of endeavor, Ruckerbauer teaches wherein each physical memory bank comprises a plurality of rows and the method comprises: for each of the plurality of requests: obtaining a second subset of bits from the sequence of bits; providing the second subset of bits as an input to the bank generation function; and based on the bank generation function being applied to the second subset of bits, generating a respective row identifier that identifies a particular row in the particular bank among the plurality of physical memory banks of the tile memory (“The row activation command may contain a predetermined number of row address bits, a predetermined subset of the row address bits being able to determine a particular memory device in which a word line is activated. For example, the row address bits may be identified by A0 to A16 based on an addressing standard (e.g., JEDEC standard).” Para 0024).
Given the teaching of Ruckerbauer, it would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention to further modify the scope of the invention of Zhou with “wherein each physical memory bank comprises a plurality of rows and the method comprises: for each of the plurality of requests: obtaining a second subset of bits from the sequence of bits; providing the second subset of bits as an input to the bank generation function; and based on the bank generation function being applied to the second subset of bits, generating a respective row identifier that identifies a particular row in the particular bank among the plurality of physical memory banks of the tile memory”. The motivation would be that a common JEDEC standard may be used by the memory manufacturing companies.
As per dependent claim 14, this claim is rejected based on arguments provided above for similar rejected claim 6.
Claims 7 and 15 are rejected under 35 U.S.C. 103 as being unpatentable over Zhou in view of Ruckerbauer and in further view of Curley et al. US 3,800,292 (“Curley”) and in further view of Heap US 2004/0093457 (“Heap”).
As per dependent claim 7, Zhou in combination with Ruckerbauer discloses the method of claim 6. Zhou and Ruckerbauer do not explicitly teach “wherein: each row of the plurality of rows comprises a width of 16 bytes; a partition of the tile memory comprises 32 physical memory banks; and the memory access stride is equal to: row_width * num_banks”.
However, in an analogous art in the same field of endeavor, Curley teaches wherein: each row of the plurality of rows comprises a width of 16 bytes (“16 byte word stored in the upper bank (row upper)” col 12 lines 57-58);
a partition of the tile memory comprises 32 physical memory banks (“upper and lower banks 401, 402 and 403, 404 respectively; whereas buffer directory module 305 is further subdivided into row upper fields 405 and row lower fields 406.” Col 6 lines 51-54).
Given the teaching of Curley, it would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention to further modify the scope of the invention of Zhou and Ruckerbauer with “wherein: each row of the plurality of rows comprises a width of 16 bytes; a partition of the tile memory comprises 32 physical memory banks”. The motivation would be that the invention provides an improved multi-level storage system, col 2 lines 55-56 of Curley.
Zhou in combination with Ruckerbauer and Curley may not explicitly disclose, but in an analogous art in the same field of endeavor, Heap teaches the memory access stride is equal to: row_width * num_banks (Consecutively addressed transactions, that is addresses with stride 1, will be mapped to different banks. This is referred to as least significant bit (LSB) interleaving, because the LSB determines the bank address, para 0006).
Given the teaching of Heap, it would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention to further modify the scope of the invention of Zhou, Ruckerbauer, and Curley with “the memory access stride is equal to: row_width * num_banks”. The motivation would be that interleaving provides for bandwidth efficiencies, para 0007 of Heap..
As per dependent claim 15, this claim is rejected based on arguments provided above for similar rejected claim 7.
Claims 8 and 16 are rejected under 35 U.S.C. 103 as being unpatentable over Zhou in view of Heap.
As per dependent claim 8, Zhou discloses the method of claim 1. Zhou may not explicitly disclose, but in an analogous art in the same field of endeavor, Heap teaches wherein obtaining a first subset of bits from the sequence of bits comprises: obtaining two or more bits that are among the least significant bits (LSB) in the sequence of bits (Consecutively addressed transactions, that is addresses with stride 1, will be mapped to different banks. This is referred to as least significant bit (LSB) interleaving, because the LSB determines the bank address, para 0006).
Given the teaching of Heap, it would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention to further modify the scope of the invention of Zhou with “wherein obtaining a first subset of bits from the sequence of bits comprises: obtaining two or more bits that are among the least significant bits (LSB) in the sequence of bits”. The motivation would be that interleaving provides for bandwidth efficiencies, para 0007 of Heap..
As per dependent claim 16, this claim is rejected based on arguments provided above for similar rejected claim 8.
Conclusion
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/ZUBAIR AHMED/Examiner, Art Unit 2132
/HOSAIN T ALAM/Supervisory Patent Examiner, Art Unit 2132
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