DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claims 1-8 and 12-23 are pending.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 1-4, 6-15, and 17-23 is/are rejected under 35 U.S.C. 103 as being unpatentable over Jang et al. (US 20190220288) in view of Mishra et al (US 20220222200)
Regarding claim 1, Jang teaches
A method, comprising:
monitoring a radio frequency front-end (RFFE) control bus (Fig. 1 (300 – bus)) in real time in a low power state; and (Figs. 1, 5, and 7, [0031-33], “The CPU 210, the wake-up control circuit 220, the interface 230, and the bus 240 may be integrated into a system on chip (SoC). Although it is described herein that the CPU 210 operates in a low-power mode (or, a sleep mode) or a normal mode, it may mean that the integrated circuit device 200 operates in a low-power mode or a normal mode. … The wake-up control circuit 220 may wake up the CPU 210 or control a clock signal applied to the CPU 210 based on signals received from the interface 230. … The interface 230 may communicate with the electronic device 100 through the interface bus 300.” And [0066], “The detecting circuit 221-1 may detect a start flag using the serial data SDA and the serial clock signal SCL.”)
sending a wakeup signal to a register status control module when a signal characteristic of a signal transmitted on the RFFE control bus meets a preset requirement, ([0064], “the integrated circuit device 200 illustrated in FIG. 1 may communicate with the electronic device 100 through an I2C interface bus. The I2C interface bus may include two bidirectional open-drain lines. The bidirectional open-drain lines may include a line for the serial data SDA and a line for the serial clock signal SCL.”, [0066], “the detecting circuit 221-1 may detect a start flag when the serial data SDA transits from a high level to a low level in a state where the serial clock signal SCL is at a high level. When the start flag is detected, the detecting circuit 221-1 may generate a detection signal DS. The detecting circuit 221-1 may generate the detection signal DS that may have the same period as the start flag. The details will be described with reference to FIG. 8 later. The detecting circuit 221-1 may output the detection signal DS to the flip-flop circuit 221-2.”)
wherein the preset requirement is set based on a signal characteristic of a mobile industry processor interface (MIPI) RFFE control instruction, and ([0066], “the detecting circuit 221-1 may detect a start flag when the serial data SDA transits from a high level to a low level in a state where the serial clock signal SCL is at a high level. When the start flag is detected, the detecting circuit 221-1 may generate a detection signal DS. The detecting circuit 221-1 may generate the detection signal DS that may have the same period as the start flag. The details will be described with reference to FIG. 8 later. The detecting circuit 221-1 may output the detection signal DS to the flip-flop circuit 221-2.”)
wherein the wakeup signal is configured to indicate to the register status control module to output an enable signal, so that a system switches from the low power state to a working state or to a standby state. ([0067-68], “The flip-flop circuit 221-2 may enable a wake-up signal WU, which has been stored therein, based on the detection signal DS. … The CPU 210 may enter the normal mode from the low-power mode according to the wake-up signal WU. In detail, the CPU 210 may enter the normal mode by starting a wake-up sequence when receiving the wake-up signal WU having the high level.”)
Jang teaches a bus which issues a start/wakeup signal/instruction but does not teach that the start/wakeup comes from an MIPI RFFE bus.
Mishra teaches
a radio frequency front-end (RFFE) control bus (Figs. 4-5 and [0050], “The first timing diagram 500 illustrates timing of an SSC 508 that is transmitted to signal the start of a datagram 510. The SSC 508 is transmitted when the serial bus is in an idle state 506. In the idle state 506, SCLK 502 is driven at full strength by a bus master while slave devices coupled to the serial bus present a high impedance to SCLK 502. SCLK 502 is held in the low signaling state (here, at zero volts) by the bus master.”)
mobile industry processor interface (MIPI) RFFE control instruction (Figs. 4-5 and [0050], “The first timing diagram 500 illustrates timing of an SSC 508 that is transmitted to signal the start of a datagram 510. The SSC 508 is transmitted when the serial bus is in an idle state 506. In the idle state 506, SCLK 502 is driven at full strength by a bus master while slave devices coupled to the serial bus present a high impedance to SCLK 502. SCLK 502 is held in the low signaling state (here, at zero volts) by the bus master.”)
Mishra is cited to teach a similar concept of waking/starting a system based on a start signal/instruction. Jang teaches using an I2C bus for waking/starting a system. Mishra teaches different bus protocols can be used interchangeably, “The serial bus 220 may be operated in accordance with RFFE, I2C, I3C, SPMI, or other protocol.”, [0042] and therefore there is a reasonable expectation of success when using an RFEE bus instead of an I2C bus. Based on Mishra and the KSR rationale "Obvious to try" – choosing from a finite number of identified, predictable solutions, with a reasonable expectation of success, it would have been obvious before the effective filing date of the invention to a person having ordinary skill in the art to which said subject matter pertains to have modified Jang to use a MIPI RFEE bus and instructions with a reasonable expectation of success.
Regarding claim 2, Mishra teaches wherein the preset requirement is set in advance based on an instruction start flag of the MIPI RFFE control instruction. (Fig. 5, [0050], “The first timing diagram 500 illustrates timing of an SSC 508 that is transmitted to signal the start of a datagram 510. The SSC 508 is transmitted when the serial bus is in an idle state 506. In the idle state 506, SCLK 502 is driven at full strength by a bus master while slave devices coupled to the serial bus present a high impedance to SCLK 502. SCLK 502 is held in the low signaling state (here, at zero volts) by the bus master.”)
Regarding claim 3, Mishra teaches wherein RFFE control bus comprises a serial clock line and a serial data line, and wherein the signal characteristic of the signal transmitted on the RFFE control bus meets the preset requirement if no clock signal is received on the serial data line and a signal transmitted on the serial data line meets a characteristic of the instruction start flag. (Fig. 5, [0050], “The timing diagrams 500, 520 show the relative timing of signals transmitted on SCLK 502 and SDATA 504. The first timing diagram 500 illustrates timing of an SSC 508 that is transmitted to signal the start of a datagram 510. The SSC 508 is transmitted when the serial bus is in an idle state 506. In the idle state 506, SCLK 502 is driven at full strength by a bus master while slave devices coupled to the serial bus present a high impedance to SCLK 502. SCLK 502 is held in the low signaling state (here, at zero volts) by the bus master.”)
Regarding claim 4, Jang teaches wherein the register status control module is configured to modify, after receiving the wakeup signal, a status of an interrupt register, so that the interrupt register outputs the enable signal. (Fig. 7, [0004], “A stimulus is needed to wake up the integrated circuit device in the low-power mode. The stimulus may be an internal interrupt or an external input.”, [0066-68], “the detecting circuit 221-1 may detect a start flag when the serial data SDA transits from a high level to a low level in a state where the serial clock signal SCL is at a high level. When the start flag is detected, the detecting circuit 221-1 may generate a detection signal DS. The detecting circuit 221-1 may generate the detection signal DS that may have the same period as the start flag. The details will be described with reference to FIG. 8 later. The detecting circuit 221-1 may output the detection signal DS to the flip-flop circuit 221-2. … The flip-flop circuit 221-2 may enable a wake-up signal WU, which has been stored therein, based on the detection signal DS. … The CPU 210 may enter the normal mode from the low-power mode according to the wake-up signal WU. In detail, the CPU 210 may enter the normal mode by starting a wake-up sequence when receiving the wake-up signal WU having the high level.” [0074], “When the start flag is detected (i.e., in case of YES) in operation S330, the controller 221A may enable and output the wake-up signal WU to the CPU 210 in operation S340.”)
Regarding claim 6, Jang teaches wherein after sending the wakeup signal to the register status control module the enable signal is provided to a control module, so that the control module enters a configuration procedure of a gated clock control module, to enable clock gating. (Fig. 3, [0041], “the wake-up control circuit 220 may disable the wake-up signal WU transmitted to the CPU 210 and may stop generating the internal clock signal IC.” [0046], “When the CPU 210 enters the normal mode, the controller 221 may output a clock enable signal EN to the clock generator 222. For instance, the controller 221 may output the clock enable signal EN to the clock generator 222”)
Regarding claim 7, Jang teaches wherein the wakeup signal is a control level. ([0053], “The wake-up signal WU may be at a low level.”)
Regarding claim 8, Jang teaches wherein the control level is a high level or a low level. ([0053], “The wake-up signal WU may be at a low level.”)
As to claims 12 and 20, Jang and Mishra teach these claims according to the reasoning provided in claim 1.
As to claims 13 and 21, Jang and Mishra teach these claims according to the reasoning provided in claim 2.
As to claims 14 and 22, Jang and Mishra teach these claims according to the reasoning provided in claim 3.
As to claims 15 and 23, Jang and Mishra teach these claims according to the reasoning provided in claim 4.
As to claims 17, Jang and Mishra teach this claim according to the reasoning provided in claim 6.
As to claims 18, Jang and Mishra teach this claim according to the reasoning provided in claim 7.
As to claims 19, Jang and Mishra teach this claim according to the reasoning provided in claim 8.
Claim(s) 5 and 16 is/are rejected under 35 U.S.C. 103 as being unpatentable over Jang and Mishra as applied to claim 1 above, and further in view of Noh et al. (US 20210216223).
Regarding claim 5, Jang teaches wherein after sending the wakeup signal to the register status control module the enable signal is provided to a digital system clock phase locked loop module, so that the digital system clock phase locked loop module outputs a clock signal.
Jang teaches enabling a clock system with a wake/start signal but does not teach the clock system has a phase locked loop. ([0053], “The UFS device 2200 may generate clocks of various frequencies from the reference clock provided from the UFS host 2100, by using a phase-locked loop (PLL) or the like.”)
Noh is cited to teach a similar concept of power management. Jang teaches using an I2C bus for waking/starting a system from low power mode where the clock may be gated during low power mode but does mention that the clock system has a phase-locked loop. Noh teaches that the clock may include a phase-locked loop to be able to operate the system at different frequencies. Based on Noh, it would have been obvious before the effective filing date of the invention to a person having ordinary skill in the art to which said subject matter pertains to have modified Jang and Misra to use a phase-locked loop in the clock system. Furthermore, being able to use a phase locked loop in the clock system improves on Jang and Misra by being able to operate the system at different frequencies. To one of ordinary skill in the art before the effective filing data of the invention it would have been advantageous to make this modification to operate the system at different frequencies.
As to claims 16, Jang, Mishra and Noh teach this claim according to the reasoning provided in claim 5.
Conclusion
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/CHERI L HARRINGTON/Examiner, Art Unit 2176 July 22, 2026
/JAWEED A ABBASZADEH/Supervisory Patent Examiner, Art Unit 2176
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