DETAILED ACTION
Response to Amendment
The applicant’s amendment filed 8/10/2026 has been entered.
Information Disclosure Statement
The information disclosure statement (IDS) submitted on 5/20/2026 was filed and is being considered by the examiner.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 1, 2, and 13-15 is/are rejected under 35 U.S.C. 103 as being unpatentable over Li (CN 204083871 U).
In regard to claim 1, Li discloses a Light Emitting Diode (LED) lamp bead, comprising:
a substrate, wherein the substrate is of a polygonal structure;
a chip one or more chips, provided on the substrate, wherein the one or more chips comprise a white light chip and/or one or more monochromatic chips; and
a signal pin group, comprising a signal input terminal and a signal output terminal electrically connected to at least one corresponding chip of the one or more chips;
wherein the signal pin group is provided on a peripheral side of the substrate.
Li fails to disclose that each side of the polygonal structure of the substrate is provided with the signal pin group.
However, this is merely a duplication of parts. It would have been obvious to one of ordinary skill in the art at the time of filing to place the pins on all four sides of the polygon to increase the number of possible connections.
In regard to claim 2, Li discloses fails to disclose that each side of the polygonal structure of the substrate is provided with at least one signal input terminal and at least one signal output terminal.
However, this is merely a duplication of parts. It would have been obvious to one of ordinary skill in the art at the time of filing to place the pins on all four sides of the polygon to increase the number of possible connections.
In regard to claim 13-15, Li discloses the signal input terminals and output terminals are in set order and are arranged symmetrically. Li fails to disclose that they are on all four sides.
However, this is merely a duplication of parts. It would have been obvious to one of ordinary skill in the art at the time of filing to place the pins on all four sides of the polygon to increase the number of possible connections.
Claim(s) 3-5 and 8-10 is/are rejected under 35 U.S.C. 103 as being unpatentable over Li (CN 204083871 U) in view of Stoyan (US 2015/0167910 A1).
In regard to claim 3, Li discloses fails to disclose when one or more chips comprise the white light chip, the signal pin group comprises a positive signal input terminal and a negative signal output terminal electrically connected to the white light chip, and at least one positive signal input terminal and at least one negative signal output terminal are provided on each side of the substrate (it is a white chip—conditionals only require one conditional to be true under BRI); when the chip is one or more chips comprise the one or more monochromatic chips, and the one or more monochromatic chip comprises chips comprise at least one R chip and/or at least one G chip, and/or and at least one B chip; the signal pin group comprises a first signal input terminal and a first signal output terminal electrically connected to the at least one R chip, a second signal input terminal and a second signal output terminal electrically connected to the at least one G chip, and a third signal input terminal and a third signal output terminal electrically connected to the at least one B chip; and each side of the polygonal structure of the substrate is provided with the first signal input terminal, the first signal output terminal, the second signal input terminal, the second signal output terminal, the third signal input terminal and the third signal output terminal when the one or more chips comprise the one or more monochromatic chips, and the one or more monochromatic chips comprise the at least one R chip; the signal pin group comprises the first signal input terminal and the first signal output terminal electrically connected to the at least one R chip; and each side of the polygonal structure of the substrate is provided with the first signal input terminal, and the first signal output terminal; when the one or more chips comprise the one or more monochromatic chips, and the one or more monochromatic chips comprise the at least one G chip; the signal pin group comprises the second signal input terminal and the second signal output terminal electrically connected to the at least one G chip; and each side of the polygonal structure of the substrate is provided with the second signal input terminal, and the second signal output terminal; when the one or more chips comprise the one or more monochromatic chips, and the one or more monochromatic chips comprise the at least one B chip; the signal pin group comprises the third signal input terminal and the third signal output terminal electrically connected to the at least one B chip; and each side of the polygonal structure of the substrate is provided with the third signal input terminal, and the third signal output terminal; when the one or more chips comprise the one or more monochromatic chips, and the one or more monochromatic chips comprise the at least one R chip and the at least one G chip; the signal pin group comprises the first signal input terminal and the first signal output terminal electrically connected to the at least one R chip, and the second signal input terminal and the second signal output terminal electrically connected to the at least one G chip; and each side of the polygonal structure of the substrate is provided with the first signal input terminal, the first signal output terminal, the second signal input terminal, and the second signal output terminal; when the one or more chips comprise the one or more monochromatic chips, and the one or more monochromatic chips comprise the at least one R chip and the at least one B chip; the signal pin group comprises the first signal input terminal and the first signal output terminal electrically connected to the at least one R chip, and the third signal input terminal and the third signal output terminal electrically connected to the at least one B chip; and each side of the polygonal structure of the substrate is provided with the first signal input terminal, the first signal output terminal, the third signal input terminal, and the third signal output terminal; and when the one or more chips comprise the one or more monochromatic chips, and the one or more monochromatic chips comprise the at least one G chip and the at least one B chip; the signal pin group comprises the second signal input terminal and the second signal output terminal electrically connected to the at least one G chip, and the third signal input terminal and the third signal output terminal electrically connected to the at least one B chip; and each side of the polygonal structure of the substrate is provided with the second signal input terminal, the second signal output terminal, the third signal input terminal, and the third signal output terminal.
However, this is merely a duplication of parts. It would have been obvious to one of ordinary skill in the art at the time of filing to place the pins on all four sides of the polygon to increase the number of possible connections.
Where the RGB chips are argued, Stoyan teaches when the chip is the monochromatic chip, the monochromatic chip comprises at least one R chip and/or at least one G chip and/or at least one B chip; the signal pin group comprises a first signal input terminal and a first signal output terminal electrically connected to the R chip, a second signal input terminal and a second signal output terminal electrically connected to the G chip, and a third signal input terminal and a third signal output terminal electrically connected to the B chip. (Figures 14; see at least [0064])
Stoyan fails to teach each side of the substrate is provided with the first signal input terminal, the first signal output terminal, the second signal input terminal, the second signal output terminal, the third signal input terminal and the third signal output terminal.
However, Li already teaches a first signal output and input and a second signal output and input on two sides of the board. It would have been obvious to one of ordinary skill in the art at the time of filing to replace the two white light LEDs of Li with the RGB LEDs of Stoyan in order to provide for wider chromaticity.
Moreover, the combination if Li and Stoyan fail to disclose that the input/output terminals are on all sides of the board. Yet, where two sides are taught, all four sides would merely be a duplication of parts. It would have been obvious to one of ordinary skill in the art at the time of filing to duplicate the terminals on all sides of the board in order to provide more contacts to connect multiple boards in multiple arrangements.
In regard to claim 4, the combination of Li and Stoyan fail to explicitly disclose wherein the signal pin group comprises the first signal input terminal, the first signal output terminal, the second signal input terminal, the second signal output terminal, the third signal input terminal, and the third signal output terminal, and wherein the LED lamp bead further comprises signal wires; the wires comprise: a first signal input wire connected to the first signal input terminal and a first signal output wire connected to the first signal output terminal; a second signal input wire connected to the second signal input terminal and a second signal output wire connected to the second signal output terminal; and a third signal input wire connected to the third signal input terminal and a third signal output wire connected to the third signal output terminal and wherein the first signal input wire, the second signal input wire and the third signal input wire, and the first signal output wire, the second signal output wire and the third signal output wire are provided on one or two sides of the polygonal structure of the substrate.
However, it would have been obvious to one of ordinary skill in the art at the time of filing to duplicate pins relative to the number of unique LED chips in order to power a plurality of LED colors, and it would have been obvious to one of ordinary skill in the art at the time of filing to provide a plurality of connection wires in order to connect a plurality of polygons.
In regard to claim 5, the combination of Li and Stoyan fail to explicitly disclose each side of the polygonal structure of the substrate is provided with the first signal input terminal, the first signal output terminal, the second signal input terminal, the second signal output terminal, the third signal input terminal and the third signal output terminal; and the first signal input wire, the second signal input wire and the third signal input wire, and the first signal output wire, the second signal output wire and the third signal output wire are provided on two adjacent sides of the polygonal structure of the substrate, respectively.
However, it would have been obvious to one of ordinary skill in the art at the time of filing to duplicate pins relative to the number of unique LED chips in order to power a plurality of LED colors, and it would have been obvious to one of ordinary skill in the art at the time of filing to provide pins on all sides of the polygon in order to provide additional connection points—this is all mere duplication of parts.
In regard to claim 8, Li discloses fails to disclose that each side of the polygonal structure of the substrate is provided with the positive signal input terminal and the negative signal output terminal.
However, this is merely a duplication of parts. It would have been obvious to one of ordinary skill in the art at the time of filing to place the pins on all four sides of the polygon to increase the number of possible connections.
In regard to claim 9 and 10, the combination of Li and Stoyan fail to explicitly disclose the LED lamp bead further comprises a signal wire, and the signal wire comprises a positive signal wire connected to the positive signal input terminal and a negative signal wire connected to the negative signal output terminal, and as recited in claim 10, that the positive signal wire and the negative signal wire are provided on two adjacent sides of the substrate.
However, it would have been obvious to one of ordinary skill in the art at the time of filing to provide signal wires in order to circuit the board.
Response to Arguments
Applicant's arguments filed 8/10/2026 have been fully considered but they are not persuasive.
The Examiner is not motivated by limitations that recite that the terminals are on all four sides. We have a teaching of them on two sides, and putting them on four sides is an obvious motivation.
Moreover, Li teaches two differently colored LED chips. It is obvious to a phosita that these can be any color and in any combination with any number of pins required.
Conclusion
THIS ACTION IS MADE FINAL. Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
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/CHRISTOPHER E DUNAY/ Primary Examiner, Art Unit 2875
