DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or
nonobviousness.
This application currently names joint inventors. In considering patentability of the claims the examiner presumes that the subject matter of the various claims was commonly owned as of the effective filing date of the claimed invention(s) absent any evidence to the contrary. Applicant is advised of the obligation under 37 CFR 1.56 to point out the inventor and effective filing dates of each claim that was not commonly owned as of the effective filing date of the later invention in order for the examiner to consider the applicability of 35 U.S.C. 102(b)(2)(C) for any potential 35 U.S.C. 102(a)(2) prior art against the later invention.
Claim(s) [ 1-3, 6-10, 13-15, 19-20 ] are rejected under 35 U.S.C. 103 as being unpatentable over [ Gorti et al. (US Pub No. 20140173345), hereinafter "Gorti", in view of Yoshida (US Pub No. 20181372803), hereinafter "Yoshida" ].
As per claim 1, Gorti significantly teaches a chip test method (The MBIST architecture of the present invention provides many benefits. In some embodiments, the architecture is arranged in a master/slave relationship where a Master MBIST controller is connected to a plurality MBIST Slave controllers through two or more MBIST Data Path (MBISTDP) Interfaces (I/Fs) [Gorti PP 0009]), comprising: sending, by a main controller, a test instruction to respective sub-controllers in a memory built-in self-test circuit (The Master controller streams generic address, data, control, and test commands to the first MBISTDP I/F in the ring [Gorti PP 0009], Master controller 100 generates generic address and test data and commands and/or control data and transmits them to MBISTDP I/F 110 A over ring portion 50 A. MBISTDP I/F 110 A receives the data and forwards one copy of it to Slave controller 120 A and another copy to the next MBISTDP I/F in the ring [Gorti PP 0027]);
configuring, by a test control circuit, the respective sub-controllers according to a preset group (The Master MBIST controller designates the order of testing based on a MacroID generated and sent to the Slave controllers over the ring. [Gorti PP 0011], As part of the test data, Master controller 100 generates a MacroID which is sent over MBIST_Bus [31:0]. Each Slave controller 120 A-D decodes the MacroID to determine whether a test is to be run by that Slave controller and which memory array is to be tested. [Gorti PP 0032]), MacroID [8:5] Controller ID ... 0000 Slave Controller 120A Test; 0001 Slave Controller 120B Test; 0010 Slave Controller 120C Test; 0011 Slave Controller 120D Test; 1000 All Slave Controllers (in parallel) [Gorti PP 0032]);
performing, by each sub-controller in the preset group, a test according to the test instruction (Each Slave controller 120 A-D may conduct MBIST testing in parallel or in serial with the other controllers. For example, a MacroID of '1000 0xx' instructs all Slave controllers to conduct the next test on their respective Tag Array, whereas a MacroID of '0001 100' instructs Slave controller 120 B alone to conduct the next test on its respective LRU array. [Gorti PP 0033]);
Gorti does not explicitly teach “and in a case where a test result indicates that the preset group does not comply with a preset standard, re-grouping the respective sub-controllers based on the test result and performing an iterative test until a test result of the iterative test indicates that a current group complies with the preset standard.”
However, Yoshida, in an analogous art, teaches and in a case where a test result indicates that the preset group does not comply with a preset standard, re-grouping the respective sub-controllers based on the test result and performing an iterative test until a test result of the iterative test indicates that a current group complies with the preset standard (The calculation unit 420 calculates a “first electric energy balance” of the battery cells 100 on the basis of voltages and currents, determines internal resistances of the battery cells 100 on the basis of temperatures, and calculates a “second electric energy balance” of the internal resistances on the basis of currents and the internal resistances. Thereby, the calculation unit 420 calculates an “accumulated electric energy balance” (electric energy E(t)) accumulated in the battery cells 100 on the basis of the first electric energy balance of the battery cells 100 and the second electric energy balance of the internal resistances. [Yoshida PP 0023], The calculation unit 420 compares the present electric energy E(t.sub.f) with the initial electric energy E.sub.0 used as a reference, and calculates a deterioration ratio 1 [Yoshida PP 0092], the calculation unit 420 corrects the total internal resistance R.sub.temp(t) using the deterioration ratio 1. In this case, the calculation unit 420 multiplies the immediately preceding total internal resistance R.sub.temp(t) by the reciprocal number of the deterioration ratio 1, and corrects the total internal resistance R.sub.temp(t) (S127). Specifically, the power variation .DELTA.E(t) is calculated using a value obtained by increasing the total internal resistance R.sub.temp(t) [Yoshida PP 0095]).
Therefore, It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to have modified the MBIST architecture disclosed by Gorti to incorporate Yoshida's teaching of iterative feedback-based adjustment, in order to improve test efficiency by dynamically adjusting test groupings based on test results until a preset standard is met (The calculation unit 420 calculates the "first electric energy balance" of the battery cells 100 on the basis of voltages and currents, determines the internal resistances of the battery cells 100 on the basis of temperatures, and calculates the "second electric energy balance" of the internal resistances on the basis of currents and the internal resistances. Thereby, the calculation unit 420 calculates the "accumulated electric energy balance" (electric energy E(t)) accumulated in the battery cells 100 [Yoshida PP 0081]). Applying these teachings would have been a predictable variation for someone of ordinary skill in the art to Gorti's invention.
As per claim 2, Gorti significantly teaches wherein before sending, by the main controller, the test instruction to the respective sub-controllers in the memory built-in self-test circuit, the chip test method further comprises (The MBIST architecture of the present invention provides many benefits. In some embodiments, the architecture is arranged in a master/slave relationship where a Master MBIST controller is connected to a plurality MBIST Slave controllers through two or more MBIST Data Path (MBISTDP) Interfaces (I/Fs) [Gorti PP 0009]): reading, by the main controller, a preset engineering file (The respective Data 140 and Tag Slave controllers 130 are configured with the specific topologies of the memories each tests. When Master controller 100 generates generic address and test data, each respective slave controller translates the data into the physical addresses needed to test the particular memory's topology. [Gorti PP 0036]); and
performing, by the main controller, configuration according to the engineering file so as to generate a test vector, wherein the test vector comprises the test instruction (The respective Data 140 and Tag Slave controllers 130 are configured with the specific topologies of the memories each tests. When Master controller 100 generates generic address and test data, each respective slave controller translates the data into the physical addresses needed to test the particular memory's topology. [Gorti PP 0036]).
As per claim 3, Gorti significantly teaches wherein performing, by the each sub-controller in the preset group, the test according to the test instruction comprises (The Master controller streams generic address, data, control, and test commands to the first MBISTDP I/F in the ring [Gorti PP 0009], Master controller 100 generates generic address and test data and commands and/or control data and transmits them to MBISTDP I/F 110 A over ring portion 50 A. MBISTDP I/F 110 A receives the data and forwards one copy of it to Slave controller 120 A and another copy to the next MBISTDP I/F in the ring [Gorti PP 0027]):
acquiring, by the each sub-controller in the preset group, the test vector according to the test instruction to perform the test (Each Slave controller 120 A-D may conduct MBIST testing in parallel or in serial with the other controllers. For example, a MacroID of ‘1000 0xx’ instructs all Slave controllers to conduct the next test on their respective Tag Array, whereas a MacroID of ‘0001 100’ instructs Slave controller 120 B alone to conduct the next test on its respective LRU array. [Gorti PP 0033]).
As per claim 6, Gorti significantly teaches wherein after performing, by the each sub-controller in the preset group, the test according to the test instruction, the chip test method further comprises (When testing is complete, each Slave controller returns test result data back to the MBISTDP I/F, which forwards the test data on to the next MBISTDP I/F in the ring for delivery to the Master controller. [Gorti PP 0010]):
acquiring, by the main controller, a test result of the each sub-controller in the preset group (MBISTDP I/F 110 B receives Data_BIST_Err [7:0] 217 and Tag_BIST_Err [7:0] 218 on Mux 207 . Mux 207 selects which error bus to return to Master controller 100 by the state of TagSlaveEn 252 [Gorti PP 0038]);
comparing, by the main controller, the test result with preset data to acquire a comparison result (When testing is complete, each Slave controller returns test result data back to the MBISTDP I/F, which forwards the test data on to the next MBISTDP I/F in the ring for delivery to the Master controller. [Gorti PP 0010], Test result data may include error codes that indicate that no error was encountered during testing, that an un-repairable error was encountered, or any other type of information. [Gorti PP 0037]); and
determining, by the main controller, whether the preset group complies with the preset standard according to the comparison result (Test result data may include error codes that indicate that no error was encountered during testing, that an un-repairable error was encountered, or any other type of information. [Gorti PP 0037]).
As per claim 7, Gorti significantly teaches configuring, by the test control circuit, the respective sub-controllers according to a new group determined by the re-grouping (The Master MBIST controller designates the order of testing based on a MacroID generated and sent to the Slave controllers over the ring [Gorti PP 0011], As part of the test data, Master controller 100 generates a MacroID which is sent over MBIST_Bus [31:0]. Each Slave controller 120 A-D decodes the MacroID to determine whether a test is to be run by that Slave controller and which memory array is to be tested. [Gorti PP 0032]);
performing, by each sub-controller in the new group, the iteration test according to the test instruction (Each Slave controller 120 A-D may conduct MBIST testing in parallel or in serial with the other controllers. For example, a MacroID of ‘1000 0xx’ instructs all Slave controllers to conduct the next test on their respective Tag Array, whereas a MacroID of ‘0001 100’ instructs Slave controller 120 B alone to conduct the next test on its respective LRU array. [Gorti PP 0033]).
Gorti does not explicitly teach “wherein re-grouping the respective sub-controllers based on the test result and performing the iterative test comprises: re-grouping the respective sub-controllers based on the test result;”
However, Yoshida, in an analogous art, teaches wherein re-grouping the respective sub-controllers based on the test result and performing the iterative test comprises (The calculation unit 420 calculates a "first electric energy balance" of the battery cells 100 on the basis of voltages and currents, determines internal resistances of the battery cells 100 on the basis of temperatures, and calculates a "second electric energy balance" of the internal resistances on the basis of currents and the internal resistances. Thereby, the calculation unit 420 calculates an "accumulated electric energy balance" (electric energy E(t)) accumulated in the battery cells 100 on the basis of the first electric energy balance of the battery cells 100 and the second electric energy balance of the internal resistances. [Yoshida PP 0023]):
re-grouping the respective sub-controllers based on the test result (The calculation unit 420 compares the present electric energy E(t.sub.f) with the initial electric energy E.sub.0 used as a reference, and calculates a deterioration ratio 1 [Yoshida PP 0092]);
Therefore, It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to have modified the MBIST architecture disclosed by Gorti to incorporate Yoshida's teaching of iterative feedback-based adjustment, in order to improve test efficiency by dynamically adjusting test groupings based on test results until a preset standard is met (The calculation unit 420 calculates the "first electric energy balance" of the battery cells 100 on the basis of voltages and currents, determines the internal resistances of the battery cells 100 on the basis of temperatures, and calculates the "second electric energy balance" of the internal resistances on the basis of currents and the internal resistances. Thereby, the calculation unit 420 calculates the "accumulated electric energy balance" (electric energy E(t)) accumulated in the battery cells 100 [Yoshida PP 0081]). Applying these teachings would have been a predictable variation for someone of ordinary skill in the art to Gorti's invention.
As per claim 8, Gorti significantly teaches A chip test apparatus, comprising: a memory built-in self-test circuit comprising a main controller and sub-controllers connected with the main controller (The MBIST architecture of the present invention provides many benefits. In some embodiments, the architecture is arranged in a master/slave relationship where a Master MBIST controller is connected to a plurality MBIST Slave controllers through two or more MBIST Data Path (MBISTDP) Interfaces (I/Fs) [Gorti PP 0009]); and
a test control circuit (Slave controller interface 125 receives MBIST_Bus_Local [31:0] and BIST_EN_Local from MBISTDP I/F 110 B and decodes the commands, addresses, controls and/or test data, including the MacroID [Gorti PP 0034]), wherein the main controller is adapted to send a test instruction to respective sub-controllers in the memory built-in self-test circuit (The Master controller streams generic address, data, control, and test commands to the first MBISTDP I/F in the ring. [Gorti PP 0009], Master controller 100 generates generic address and test data and commands and/or control data and transmits them to MBISTDP I/F 110 A over ring portion 50 A. MBISTDP I/F 110 A receives the data and forwards one copy of it to Slave controller 120 A and another copy to the next MBISTDP I/F in the ring [Gorti PP 0027]);
the test control circuit is adapted to configure the respective sub-controllers according to a preset group (The Master MBIST controller designates the order of testing based on a MacroID generated and sent to the Slave controllers over the ring. [Gorti PP 0011], As part of the test data, Master controller 100 generates a MacroID which is sent over MBIST_Bus [31:0]. Each Slave controller 120 A-D decodes the MacroID to determine whether a test is to be run by that Slave controller and which memory array is to be tested. [Gorti PP 0032]);
each sub-controller in the preset group is adapted to perform a test according to the test instruction (Each Slave controller 120 A-D may conduct MBIST testing in parallel or in serial with the other controllers. For example, a MacroID of ‘1000 0xx’ instructs all Slave controllers to conduct the next test on their respective Tag Array, whereas a MacroID of ‘0001 100’ instructs Slave controller 120 B alone to conduct the next test on its respective LRU array. [Gorti PP 0033]);
Gorti does not explicitly teach “the main controller is adapted to, in a case where a test result indicates that the preset group does not comply with a preset standard, re-group the respective sub-controllers based on the test result and perform an iterative test until a test result of the iterative test indicates that a current group complies with the preset standard.”
However, Yoshida, in an analogous art, teaches the main controller is adapted to, in a case where a test result indicates that the preset group does not comply with a preset standard, re-group the respective sub-controllers based on the test result and perform an iterative test until a test result of the iterative test indicates that a current group complies with the preset standard (The calculation unit 420 calculates a “first electric energy balance” of the battery cells 100 on the basis of voltages and currents, determines internal resistances of the battery cells 100 on the basis of temperatures, and calculates a “second electric energy balance” of the internal resistances on the basis of currents and the internal resistances. Thereby, the calculation unit 420 calculates an “accumulated electric energy balance” (electric energy E(t)) accumulated in the battery cells 100 on the basis of the first electric energy balance of the battery cells 100 and the second electric energy balance of the internal resistances. [Yoshida PP 0023], The calculation unit 420 compares the present electric energy E(t.sub.f) with the initial electric energy E.sub.0 used as a reference, and calculates a deterioration ratio 1 [Yoshida PP 0092], the calculation unit 420 corrects the total internal resistance R.sub.temp(t) using the deterioration ratio 1. In this case, the calculation unit 420 multiplies the immediately preceding total internal resistance R.sub.temp(t) by the reciprocal number of the deterioration ratio 1, and corrects the total internal resistance R.sub.temp(t) (S127). Specifically, the power variation .DELTA.E(t) is calculated using a value obtained by increasing the total internal resistance R.sub.temp(t) [Yoshida PP 0095]).
Therefore, It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to have modified the MBIST architecture disclosed by Gorti to incorporate Yoshida's teaching of iterative feedback-based adjustment, in order to improve test efficiency by dynamically adjusting test groupings based on test results until a preset standard is met (The calculation unit 420 calculates the "first electric energy balance" of the battery cells 100 on the basis of voltages and currents, determines the internal resistances of the battery cells 100 on the basis of temperatures, and calculates the "second electric energy balance" of the internal resistances on the basis of currents and the internal resistances. Thereby, the calculation unit 420 calculates the "accumulated electric energy balance" (electric energy E(t)) accumulated in the battery cells 100 [Yoshida PP 0081]). Applying these teachings would have been a predictable variation for someone of ordinary skill in the art to Gorti's invention.
As per claim 9, Gorti significantly teaches a chip, comprising: a memory, a processor and a computer program stored on the memory and operable on the processor, wherein the computer program, when executed by the processor, implements operations comprising (The MBIST architecture of the present invention provides many benefits. In some embodiments, the architecture is arranged in a master/slave relationship where a Master MBIST controller is connected to a plurality MBIST Slave controllers through two or more MBIST Data Path (MBISTDP) Interfaces (I/Fs) [Gorti PP 0009]):
sending, by a main controller, a test instruction to respective sub-controllers in a memory built-in self-test circuit (The Master controller streams generic address, data, control, and test commands to the first MBISTDP I/F in the ring. [Gorti PP 0009], Master controller 100 generates generic address and test data and commands and/or control data and transmits them to MBISTDP I/F 110 A over ring portion 50 A. MBISTDP I/F 110 A receives the data and forwards one copy of it to Slave controller 120 A and another copy to the next MBISTDP I/F in the ring [Gorti PP 0027]);
configuring, by a test control circuit, the respective sub-controllers according to a preset group (The Master MBIST controller designates the order of testing based on a MacroID generated and sent to the Slave controllers over the ring. [Gorti PP 0011], As part of the test data, Master controller 100 generates a MacroID which is sent over MBIST_Bus [31:0]. Each Slave controller 120 A-D decodes the MacroID to determine whether a test is to be run by that Slave controller and which memory array is to be tested. [Gorti PP 0032]);
performing, by each sub-controller in the preset group, a test according to the test instruction (Each Slave controller 120 A-D may conduct MBIST testing in parallel or in serial with the other controllers. For example, a MacroID of ‘1000 0xx’ instructs all Slave controllers to conduct the next test on their respective Tag Array, whereas a MacroID of ‘0001 100’ instructs Slave controller 120 B alone to conduct the next test on its respective LRU array. [Gorti PP 0033]);
Gorti does not explicitly teach “in a case where a test result indicates that the preset group does not comply with a preset standard, re-grouping the respective sub-controllers based on the test result and performing an iterative test until a test result of the iterative test indicates that a current group complies with the preset standard.”
However, Yoshida, in an analogous art, teaches in a case where a test result indicates that the preset group does not comply with a preset standard, re-grouping the respective sub-controllers based on the test result and performing an iterative test until a test result of the iterative test indicates that a current group complies with the preset standard (The calculation unit 420 calculates a “first electric energy balance” of the battery cells 100 on the basis of voltages and currents, determines internal resistances of the battery cells 100 on the basis of temperatures, and calculates a “second electric energy balance” of the internal resistances on the basis of currents and the internal resistances. Thereby, the calculation unit 420 calculates an “accumulated electric energy balance” (electric energy E(t)) accumulated in the battery cells 100 on the basis of the first electric energy balance of the battery cells 100 and the second electric energy balance of the internal resistances. [Yoshida PP 0023], The calculation unit 420 compares the present electric energy E(t.sub.f) with the initial electric energy E.sub.0 used as a reference, and calculates a deterioration ratio 1 [Yoshida PP 0092], the calculation unit 420 corrects the total internal resistance R.sub.temp(t) using the deterioration ratio 1. In this case, the calculation unit 420 multiplies the immediately preceding total internal resistance R.sub.temp(t) by the reciprocal number of the deterioration ratio 1, and corrects the total internal resistance R.sub.temp(t) (S127). Specifically, the power variation .DELTA.E(t) is calculated using a value obtained by increasing the total internal resistance R.sub.temp(t) [Yoshida PP 0095]).
Therefore, It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to have modified the MBIST architecture disclosed by Gorti to incorporate Yoshida's teaching of iterative feedback-based adjustment, in order to improve test efficiency by dynamically adjusting test groupings based on test results until a preset standard is met (The calculation unit 420 calculates the "first electric energy balance" of the battery cells 100 on the basis of voltages and currents, determines the internal resistances of the battery cells 100 on the basis of temperatures, and calculates the "second electric energy balance" of the internal resistances on the basis of currents and the internal resistances. Thereby, the calculation unit 420 calculates the "accumulated electric energy balance" (electric energy E(t)) accumulated in the battery cells 100 [Yoshida PP 0081]). Applying these teachings would have been a predictable variation for someone of ordinary skill in the art to Gorti's invention.
As per claim 10, Gorti significantly teaches a non-transitory computer readable storage medium, wherein the computer readable storage medium stores a computer program, and the computer program, when being executed by a processor, implements the chip test method according to claim 1 (The MBIST architecture of the present invention provides many benefits. In some embodiments, the architecture is arranged in a master/slave relationship where a Master MBIST controller is connected to a plurality MBIST Slave controllers through two or more MBIST Data Path (MBISTDP) Interfaces (I/Fs) [Gorti PP 0009], the HDL code (e.g., register transfer level (RTL) code/data) may be used to generate GDS data, GDSII data and the like. GDSII data, for example, is a descriptive file format and may be used in different embodiments to represent a three-dimensional model of a semiconductor product or device. Such models may be used by semiconductor manufacturing facilities to create semiconductor products and/or devices. The GDSII data may be stored as a database or other program storage structure. This data may also be stored on a computer readable storage device (e.g., data storage units, RAMs, compact discs, DVDs, solid state storage and the like) [Gorti PP 0044]).
As per claim 13, Gorti significantly teaches wherein the test result comprises data including at least one of test power consumption, test time, and voltage drop (IR_Drop) (Power draw is an important consideration when designing portable, battery-powered devices like smart phones, tablet PCs, personal digital assistants (PDAs), pocket computers, and music players. These devices typically include one or more microprocessors that undergo MBIST testing upon power-up or during a wake-up cycle. When testing multiple memory arrays simultaneously (i.e., in parallel) more transistors are cycled at once than when the memory arrays are tested in serial. Testing each memory array in serial reduces overall power draw. [Gorti PP 0005], Testing each memory array in serial, however, increases the amount of time it takes for a device to complete power-up self-tests or recover from a sleep state. [Gorti PP 0006]).
As per claim 14, Gorti significantly teaches wherein the new group comprises at least one of the sub-controllers from the preset group or does not comprise any sub-controller from the preset group (The Master MBIST controller designates the order of testing based on a MacroID generated and sent to the Slave controllers over the ring. [Gorti PP 0011], As part of the test data, Master controller 100 generates a MacroID which is sent over MBIST_Bus [31:0]. Each Slave controller 120 A-D decodes the MacroID to determine whether a test is to be run by that Slave controller and which memory array is to be tested. [Gorti PP 0032]), MacroID [8:5] Controller ID ... 0000 Slave Controller 120A Test; 0001 Slave Controller 120B Test; 0010 Slave Controller 120C Test; 0011 Slave Controller 120D Test; 1000 All Slave Controllers (in parallel) [Gorti PP 0032]).
As per claim 15, Gorti significantly teaches configuring, by the test control circuit, the respective sub-controllers according to the new group (The Master MBIST controller designates the order of testing based on a MacroID generated and sent to the Slave controllers over the ring. [Gorti PP 0011], As part of the test data, Master controller 100 generates a MacroID which is sent over MBIST_Bus [31:0]. Each Slave controller 120 A-D decodes the MacroID to determine whether a test is to be run by that Slave controller and which memory array is to be tested [Gorti PP 0032]);
performing, by each sub-controller in the new group, the iteration test according to the test instruction (Each Slave controller 120 A-D may conduct MBIST testing in parallel or in serial with the other controllers. For example, a MacroID of ‘1000 0xx’ instructs all Slave controllers to conduct the next test on their respective Tag Array, whereas a MacroID of ‘0001 100’ instructs Slave controller 120 B alone to conduct the next test on its respective LRU array. [Gorti PP 0033]).
Gorti does not explicitly teach “wherein re-grouping the respective sub-controllers based on the test result and performing the iterative test comprises: automatically selecting sub-controllers of a new group based on an established set of rules;”
However, Yoshida, in an analogous art, teaches wherein re-grouping the respective sub-controllers based on the test result and performing the iterative test comprises: (The calculation unit 420 calculates a "first electric energy balance" of the battery cells 100 on the basis of voltages and currents, determines internal resistances of the battery cells 100 on the basis of temperatures, and calculates a "second electric energy balance" of the internal resistances on the basis of currents and the internal resistances. Thereby, the calculation unit 420 calculates an "accumulated electric energy balance" (electric energy E(t)) accumulated in the battery cells 100 on the basis of the first electric energy balance of the battery cells 100 and the second electric energy balance of the internal resistances. [Yoshida PP 0023])
automatically selecting sub-controllers of a new group based on an established set of rules ( The calculation unit 420 compares the present electric energy E(t.sub.f) with the initial electric energy E.sub.0 used as a reference, and calculates a deterioration ratio 1 [Yoshida PP 0092], the calculation unit 420 corrects the total internal resistance R.sub.temp(t) using the deterioration ratio 1. In this case, the calculation unit 420 multiplies the immediately preceding total internal resistance R.sub.temp(t) by the reciprocal number of the deterioration ratio 1, and corrects the total internal resistance R.sub.temp(t) [Yoshida PP 0095]);
Therefore, It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to have modified the MBIST architecture disclosed by Gorti to incorporate Yoshida's teaching of iterative feedback-based adjustment, in order to improve test efficiency by dynamically adjusting test groupings based on test results until a preset standard is met (The calculation unit 420 calculates the "first electric energy balance" of the battery cells 100 on the basis of voltages and currents, determines the internal resistances of the battery cells 100 on the basis of temperatures, and calculates the "second electric energy balance" of the internal resistances on the basis of currents and the internal resistances. Thereby, the calculation unit 420 calculates the "accumulated electric energy balance" (electric energy E(t)) accumulated in the battery cells 100 [Yoshida PP 0081]). Applying these teachings would have been a predictable variation for someone of ordinary skill in the art to Gorti's invention.
As per claim 19, Gorti significantly teaches wherein the test vector comprises a configuration part and a main part (some embodiments, the most significant eight bits of the MBIST_Bus may indicate the type of data being sent, such as test data or a command, and the other bits may contain the test or the command itself. [Gorti PP 0031]), wherein the main part of the test vector carries the test instruction, and the configuration part of the test vector is used for determining whether each sub-controller will be shielded (As part of the test data, Master controller 100 generates a MacroID which is sent over MBIST_Bus [31:0]. Each Slave controller 120 A-D decodes the MacroID to determine whether a test is to be run by that Slave controller and which memory array is to be tested. [Gorti PP 0032]).
As per claim 20, Gorti does not explicitly teach “wherein after re-grouping the respective sub-controllers based on the test result, the configuration part of the test vector is updated based on the re-grouping while the main part of the test vector remains unchanged.”
However, Yoshida, in an analogous art, teaches wherein after re-grouping the respective sub-controllers based on the test result, the configuration part of the test vector is updated based on the re-grouping while the main part of the test vector remains unchanged (The calculation unit 420 compares the present electric energy E(t.sub.f) with the initial electric energy E.sub.0 used as a reference, and calculates a deterioration ratio 1 [Yoshida PP 0092], the calculation unit 420 corrects the total internal resistance R.sub.temp(t) using the deterioration ratio 1. In this case, the calculation unit 420 multiplies the immediately preceding total internal resistance R.sub.temp(t) by the reciprocal number of the deterioration ratio 1, and corrects the total internal resistance R.sub.temp(t) [Yoshida PP 0095]).
Therefore, It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to have modified the MBIST architecture disclosed by Gorti to incorporate Yoshida's teaching of iterative feedback-based adjustment, in order to improve test efficiency by dynamically adjusting test groupings based on test results until a preset standard is met (The calculation unit 420 calculates the "first electric energy balance" of the battery cells 100 on the basis of voltages and currents, determines the internal resistances of the battery cells 100 on the basis of temperatures, and calculates the "second electric energy balance" of the internal resistances on the basis of currents and the internal resistances. Thereby, the calculation unit 420 calculates the "accumulated electric energy balance" (electric energy E(t)) accumulated in the battery cells 100 [Yoshida PP 0081]). Applying these teachings would have been a predictable variation for someone of ordinary skill in the art to Gorti's invention.
Claim(s) [ 4-5, 11-12, 16-18 ] are rejected under 35 U.S.C. 103 as being unpatentable over [ Gorti, in view of Yoshida, in further view of Kothiala et al. (US Pub No. 20170110204) ].
As per claim 4, Gorti significantly teaches wherein configuring, by the test control circuit, the respective sub-controllers according to the preset group comprises (The Master MBIST controller designates the order of testing based on a MacroID generated and sent to the Slave controllers over the ring [Gorti PP 0011], As part of the test data, Master controller 100 generates a MacroID which is sent over MBIST_Bus [31:0]. Each Slave controller 120 A-D decodes the MacroID to determine whether a test is to be run by that Slave controller and which memory array is to be tested [Gorti PP 0032])
Gorti in view of Yoshida do not explicitly teach “shielding, by the test control circuit, the test instruction sent by the main controller towards each sub-controller not belonging to the preset group.”
However, Kothiala, in an analogous art, teaches shielding, by the test control circuit, the test instruction sent by the main controller towards each sub-controller not belonging to the preset group (The IDMA logic 514 forwards 32 bits of data 616 to the de-featured memory 622 and also provides 8 bits of address 620 to the de-featured memory 622 . The de-featured memory 622 returns 32 bits of data 618 to IDMA logic 514 , which then passes the 32 bits of data 610 to the MBIST interface 502 . [Kothiala PP 0049], The glue logic contained in IDMA logic 514 modifies the 9 bit address 512 coming from the MBIST interface 502 to match the de-featured configuration of memory 622 and any associated RAM memories [Kothiala PP 0050]).
Therefore, It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to have modified the system of Gorti and Yoshida to incorporate Kothiala's teaching of shielding logic for selectively blocking test instructions to non-selected sub-controllers, in order to enable dynamic enabling and disabling of individual sub-controllers during iterative test grouping without regenerating test vectors (The glue logic contained in IDMA logic 514 modifies the 9 bit address 512 coming from the MBIST interface 502 to match the de-featured configuration of memory 622 and any associated RAM memories. This configuration requires that the UserIR bit used in WTAP 504 be set to 1. [Kothiala PP 0050]). Applying these teachings would have been a predictable variation for someone of ordinary skill in the art to Gorti and Yoshida's invention.
As per claim 5, Gorti significantly teaches wherein at least one set of shielding logic circuit is disposed between the main controller and each of the respective sub-controllers, and configuring, by the test control circuit, the respective sub-controllers according to the preset group comprises (The Master MBIST controller designates the order of testing based on a MacroID generated and sent to the Slave controllers over the ring. [Gorti PP 0011])
Gorti in view of Yoshida do not explicitly teach “turning off, by the test control circuit, the shielding logic circuit between the each sub-controller in the preset group and the main controller; and turning on, by the test control circuit, the shielding logic circuit between each sub-controller not belonging to the preset group and the main controller.”
However, Kothiala, in an analogous art, teaches turning off, by the test control circuit, the shielding logic circuit between the each sub-controller in the preset group and the main controller (IDMA logic 514 provides 32 bits of data 510 to MBIST interface 502 . In this example de-featuring 506 is off and the programmable UserIRbit is set to 0. [Kothiala PP 0048]); and
turning on, by the test control circuit, the shielding logic circuit between each sub-controller not belonging to the preset group and the main controller (The glue logic contained in IDMA logic 514 modifies the 9 bit address 512 coming from the MBIST interface 502 to match the de-featured configuration of memory 622 and any associated RAM memories. This configuration requires that the UserIR bit used in WTAP 504 be set to 1. [Kothiala PP 0050]).
Therefore, It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to have modified the system of Gorti and Yoshida to incorporate Kothiala's teaching of shielding logic for selectively blocking test instructions to non-selected sub-controllers, in order to enable dynamic enabling and disabling of individual sub-controllers during iterative test grouping without regenerating test vectors (The glue logic contained in IDMA logic 514 modifies the 9 bit address 512 coming from the MBIST interface 502 to match the de-featured configuration of memory 622 and any associated RAM memories. This configuration requires that the UserIR bit used in WTAP 504 be set to 1. [Kothiala PP 0050]). Applying these teachings would have been a predictable variation for someone of ordinary skill in the art to Gorti and Yoshida's invention.
As per claim 11, Gorti significantly teaches respective mask modules are connected to the test control circuit, and the test control circuit is able to control which sub-controllers among the respective sub-controllers are able to receive the test instruction sent by the main controller and which sub-controllers among the respective sub-controllers are not able to receive the test instruction sent by the main controller (As part of the test data, Master controller 100 generates a MacroID which is sent over MBIST_Bus [31:0]. Each Slave controller 120 A-D decodes the MacroID to determine whether a test is to be run by that Slave controller and which memory array is to be tested [Gorti PP 0032]).
Gorti in view of Yoshida do not explicitly teach “wherein there are mask modules that are able to be independently controlled on signal transmission paths between the main controller and the respective sub-controllers”
However, Kothiala, in an analogous art, teaches wherein there are mask modules that are able to be independently controlled on signal transmission paths between the main controller and the respective sub-controllers (IDMA logic 514 provides 32 bits of data 510 to MBIST interface 502 . In this example de-featuring 506 is off and the programmable UserIRbit is set to 0. [Kothiala PP 0048])
Therefore, It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to have modified the system of Gorti and Yoshida to incorporate Kothiala's teaching of shielding logic for selectively blocking test instructions to non-selected sub-controllers, in order to enable dynamic enabling and disabling of individual sub-controllers during iterative test grouping without regenerating test vectors (The glue logic contained in IDMA logic 514 modifies the 9 bit address 512 coming from the MBIST interface 502 to match the de-featured configuration of memory 622 and any associated RAM memories. This configuration requires that the UserIR bit used in WTAP 504 be set to 1. [Kothiala PP 0050]). Applying these teachings would have been a predictable variation for someone of ordinary skill in the art to Gorti and Yoshida's invention.
As per claim 12, Gorti significantly teaches wherein configuring, by the test control circuit, the respective sub-controllers according to the preset group comprises (The Master MBIST controller designates the order of testing based on a MacroID generated and sent to the Slave controllers over the ring. [Gorti PP 0011])
Gorti in view of Yoshida do not explicitly teach “setting, by the test control circuit, each mask module between the each sub-controller in the preset group and the main controller to a conductive state, enabling the each sub-controller in the preset group to receive the test instruction sent by the main controller; and setting, by the test control circuit, each mask module between each sub-controller not belonging to the preset group and the main controller to a cut-off state, preventing the each sub-controller not belonging the preset group from receiving the test instruction sent by the main controller.”
However, Kothiala, in an analogous art, teaches setting, by the test control circuit, each mask module between the each sub-controller in the preset group and the main controller to a conductive state, enabling the each sub-controller in the preset group to receive the test instruction sent by the main controller (IDMA logic 514 provides 32 bits of data 510 to MBIST interface 502 . In this example de-featuring 506 is off and the programmable UserIRbit is set to 0. [Kothiala PP 0048]); and
setting, by the test control circuit, each mask module between each sub-controller not belonging to the preset group and the main controller to a cut-off state, preventing the each sub-controller not belonging the preset group from receiving the test instruction sent by the main controller (The glue logic contained in IDMA logic 514 modifies the 9 bit address 512 coming from the MBIST interface 502 to match the de-featured configuration of memory 622 and any associated RAM memories. This configuration requires that the UserIR bit used in WTAP 504 be set to 1. [Kothiala PP 0050]).
Therefore, It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to have modified the system of Gorti and Yoshida to incorporate Kothiala's teaching of shielding logic for selectively blocking test instructions to non-selected sub-controllers, in order to enable dynamic enabling and disabling of individual sub-controllers during iterative test grouping without regenerating test vectors (The glue logic contained in IDMA logic 514 modifies the 9 bit address 512 coming from the MBIST interface 502 to match the de-featured configuration of memory 622 and any associated RAM memories. This configuration requires that the UserIR bit used in WTAP 504 be set to 1. [Kothiala PP 0050]). Applying these teachings would have been a predictable variation for someone of ordinary skill in the art to Gorti and Yoshida's invention.
As per claim 16, Gorti significantly teaches wherein configuring, by the test control circuit, the respective sub-controllers according to the preset group comprises (The Master MBIST controller designates the order of testing based on a MacroID generated and sent to the Slave controllers over the ring. [Gorti PP 0011])
Gorti in view of Yoshida do not explicitly teach “shielding, by signals from the test control circuit, a test clock of each sub-controller, a test enable signal sent by the main controller, and a test result feedback signal sent to the main controller.”
However, Kothiala, in an analogous art, teaches shielding, by signals from the test control circuit, a test clock of each sub-controller, a test enable signal sent by the main controller, and a test result feedback signal sent to the main controller (The glue logic contained in IDMA logic 514 modifies the 9 bit address 512 coming from the MBIST interface 502 to match the de-featured configuration of memory 622 and any associated RAM memories. This configuration requires that the UserIR bit used in WTAP 504 be set to 1. [Kothiala PP 0050]).
Therefore, It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to have modified the system of Gorti and Yoshida to incorporate Kothiala's teaching of shielding logic for selectively blocking test instructions to non-selected sub-controllers, in order to enable dynamic enabling and disabling of individual sub-controllers during iterative test grouping without regenerating test vectors (The glue logic contained in IDMA logic 514 modifies the 9 bit address 512 coming from the MBIST interface 502 to match the de-featured configuration of memory 622 and any associated RAM memories. This configuration requires that the UserIR bit used in WTAP 504 be set to 1. [Kothiala PP 0050]). Applying these teachings would have been a predictable variation for someone of ordinary skill in the art to Gorti and Yoshida's invention.
As per claim 17, Gorti significantly teaches wherein configuring, by the test control circuit, the respective sub-controllers according to the preset group comprises (The Master MBIST controller designates the order of testing based on a MacroID generated and sent to the Slave controllers over the ring. [Gorti PP 0011])
Gorti in view of Yoshida do not explicitly teach “shielding, by sending a shield signal or an interference signal, the test instruction sent by the main controller towards each sub-controller not belonging to the preset group.”
However, Kothiala, in an analogous art, teaches shielding, by sending a shield signal or an interference signal, the test instruction sent by the main controller towards each sub-controller not belonging to the preset group (The IDMA logic 514 forwards 32 bits of data 616 to the de-featured memory 622 and also provides 8 bits of address 620 to the de-featured memory 622 . The de-featured memory 622 returns 32 bits of data 618 to IDMA logic 514 , which then passes the 32 bits of data 610 to the MBIST interface 502 . [Kothiala PP 0049], The glue logic contained in IDMA logic 514 modifies the 9 bit address 512 coming from the MBIST interface 502 to match the de-featured configuration of memory 622 and any associated RAM memories. This configuration requires that the UserIR bit used in WTAP 504 be set to 1. [Kothiala PP 0050]).
Therefore, It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to have modified the system of Gorti and Yoshida to incorporate Kothiala's teaching of shielding logic for selectively blocking test instructions to non-selected sub-controllers, in order to enable dynamic enabling and disabling of individual sub-controllers during iterative test grouping without regenerating test vectors (The glue logic contained in IDMA logic 514 modifies the 9 bit address 512 coming from the MBIST interface 502 to match the de-featured configuration of memory 622 and any associated RAM memories. This configuration requires that the UserIR bit used in WTAP 504 be set to 1. [Kothiala PP 0050]). Applying these teachings would have been a predictable variation for someone of ordinary skill in the art to Gorti and Yoshida's invention.
As per claim 18, Gorti in view of Yoshida do not explicitly teach “wherein another set of shielding logic circuit is disposed on a signal transmission path by which each sub-controller feeds back signals to the main controller, and still another set of shielding logic circuit is disposed between a test clock signal supplied inside the chip and each corresponding memory.”
However, Kothiala, in an analogous art, teaches wherein another set of shielding logic circuit is disposed on a signal transmission path by which each sub-controller feeds back signals to the main controller (The IDMA logic 514 forwards 32 bits of data 616 to the de-featured memory 622 and also provides 8 bits of address 620 to the de-featured memory 622 . The de-featured memory 622 returns 32 bits of data 618 to IDMA logic 514 , which then passes the 32 bits of data 610 to the MBIST interface 502 . [Kothiala PP 0049]), and still another set of shielding logic circuit is disposed between a test clock signal supplied inside the chip and each corresponding memory (The glue logic contained in IDMA logic 514 modifies the 9 bit address 512 coming from the MBIST interface 502 to match the de-featured configuration of memory 622 and any associated RAM memories. This configuration requires that the UserIR bit used in WTAP 504 be set to 1. [Kothiala PP 0050]).
Therefore, It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to have modified the system of Gorti and Yoshida to incorporate Kothiala's teaching of shielding logic for selectively blocking test instructions to non-selected sub-controllers, in order to enable dynamic enabling and disabling of individual sub-controllers during iterative test grouping without regenerating test vectors (The glue logic contained in IDMA logic 514 modifies the 9 bit address 512 coming from the MBIST interface 502 to match the de-featured configuration of memory 622 and any associated RAM memories. This configuration requires that the UserIR bit used in WTAP 504 be set to 1. [Kothiala PP 0050]). Applying these teachings would have been a predictable variation for someone of ordinary skill in the art to Gorti and Yoshida's invention.
Conclusion
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/KAREEM FUAD ALHWAMDEH/Examiner, Art Unit 2112
/ALBERT DECADY/Supervisory Patent Examiner, Art Unit 2112
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