DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Priority
Acknowledgment is made of applicant’s claim for foreign priority under 35 U.S.C. 119 (a)-(d).
Information Disclosure Statement
The information disclosure statement (IDS) submitted on 03/21/2025 has been considered by the examiner.
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claims 1-4, 9, and 11-15 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Im (US Patent Publication No. 2017/0084220).
With reference to claim 1, Im discloses a pixel comprising:
a light emitting element (EL) and a first transistor (TD) coupled in series between a reference node (ELVDD) and a supply node (ELVSS) (see paragraphs 47-60; Fig. 1); and
a first circuit (150) comprising a first terminal coupled to the control terminal of the first transistor (TD), a second terminal coupled to the reference node (ELVDD) (see paragraphs 48-50; Fig. 1), the first circuit (150) being configured to generate a control voltage on the first terminal (in teaching initialization voltage; see paragraphs 48-50), the first circuit (150) comprising a variable voltage divider configured to provide the control voltage on the first terminal (in teaching capacitors (C1, C2) in series form a voltage divider at node N4 provided with varying scan voltages; see paragraphs 54-55, 63-65), the variable voltage divider comprising two capacitive branches (C1, C2), the proportion between the branches being variable the ratio of the capacitance values between the branches being variable terminal (in teaching capacitors (C1, C2) in series form a voltage divider at node N4 provided with varying scan voltages; see paragraphs 54-55, 63-65); and
a first switch (T2) coupled between the first terminal of the first circuit (150) and a conductive terminal of the first transistor (see paragraphs 51-53, 63-65; Fig. 1).
With reference to claim 2, Im discloses the pixel according to claim 1, and further discloses wherein the voltage divider comprises a first capacitor (C2) coupled between the first and second terminals of the first circuit (in teaching one terminal connected to reference node and the node (N1); see paragraphs 47-60; Fig. 1).
With reference to claim 3, Im discloses the pixel according to claim 1, and further discloses wherein the first circuit (150) comprises a third terminal coupled to a node of application of a data signal (in teaching receiving SL(n-1) and SCAN(n-1); see paragraphs 47-60; Fig. 1).
With reference to claim 4, Im discloses the pixel according to claim 3, and further discloses wherein the voltage divider comprises a second capacitor (120) coupled between the first terminal of the first circuit (106) and the third terminal (118) of the first circuit.
With reference to claim 9, Im discloses the pixel according to claim 1, and further discloses wherein the first transistor and the element are coupled in series with a fifth switch (T4) (see paragraphs 47-60; Fig. 1).
With reference to claim 11, Im discloses the pixel according to claim 1, and further discloses a display screen comprising a plurality of pixels (see paragraph 47; Fig. 4)
With reference to claim 12, Im discloses the pixel according to claim 11, and further discloses wherein the pixels are disposed in an array and the third terminal (118) of each first circuit (150) is configured to receive a voltage common to all the pixels of a same row (in teaching SCAN(n-1) applied to pixels in a row; see paragraphs 47-60; Figs 1-2, 4).
With reference to claim 13, Im discloses the pixel according to claim 1, and further discloses wherein the light emitting elements (EL) are coupled with a common cathode (see paragraph 47-49, 57; Fig. 1), the elements of each pixel being coupled between the first transistor (TD) of said pixel and the reference node (connection to the ELVSS signal line; see paragraphs 47-49; Fig. 1).
With reference to claim 14, Im discloses a method for controlling the pixel according to claim 1, and further discloses a first phase during which the first switch (T2) is closed and the capacitors of the voltage dividers coupled between the first and second terminals of the first circuit are charged (in teaching period P1, the SCAN signal is low, C1 and C2 are charged), and a second phase during which the first switch (120) is open (in teaching period P3 the SCAN signal is high, the first witch is open; see paragraphs 62-67; Fig. 2).
With reference to claim 15, Im discloses the method according to claim 14, and further discloses, comprising an alternance of first and second phases (see steps P1-P3; Fig. 2).
Allowable Subject Matter
Claims 5-8 and 10 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
Pertinent Prior Art
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure.
KITAZAWA et al. (US2007/0273619) discloses a circuit for driving an electro-optical element having a first, second, and third capacitive element for controlling voltages supplied to the electro-optical element (see paragraphs 45-82; Figs. 1-10).
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to ALECIA DIANE ENGLISH whose telephone number is (571)270-1595. The examiner can normally be reached Mon.-Fri. 7:00am-3:00am.
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/ADE/Examiner, Art Unit 2625
/WILLIAM BODDIE/Supervisory Patent Examiner, Art Unit 2625