DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Rejections - 35 USC § 112
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claims 1-13 are rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention.
Claim 1 recites the limitation "a control voltage" in lines 8 and 10. There is insufficient antecedent basis for this limitation in the claim. It is unclear if the control voltage in line 8 is the same control voltage in line 10 or not. Claims 2-11 are dependent on claim 1.
Claim 12 recites the limitation "a control voltage" in lines 8 and 10. There is insufficient antecedent basis for this limitation in the claim. It is unclear if the control voltage in line 8 is the same control voltage in line 10 or not. Claim 13 is dependent on claim 12.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
This application currently names joint inventors. In considering patentability of the claims the examiner presumes that the subject matter of the various claims was commonly owned as of the effective filing date of the claimed invention(s) absent any evidence to the contrary. Applicant is advised of the obligation under 37 CFR 1.56 to point out the inventor and effective filing dates of each claim that was not commonly owned as of the effective filing date of the later invention in order for the examiner to consider the applicability of 35 U.S.C. 102(b)(2)(C) for any potential 35 U.S.C. 102(a)(2) prior art against the later invention.
Claims 1-13 are rejected under 35 U.S.C. 103 as being unpatentable over U.S. Patent Pub. No. 2018/0182290 A1 to Yamamoto in view of U.S. Patent Pub. No. 2019/0347990 A1 to Knez et al.
As to claim 1, Yamamoto discloses Amended) a pixel comprising:
a transistor (Fig. 2, paragraph 0032, transistor (Tr1))
a light emitting element (Fig. 2, paragraph 0032, EL device (13));
a memory comprising a memory cell (Fig. 2, paragraph 0032, memory circuit (12A));
a control circuit configured to generate a control voltage (VGS) on a control terminal of the transistor, the control voltage being equal to:
a first voltage during a step of resetting at least one cell of the memory (Fig. 3, paragraphs 0049-0063, where the gate voltage (Vg) between time (T1-T3) is the first voltage);
a second voltage during a step of setting at least one cell of the memory (Fig. 3, paragraphs 0049-0063, where the gate voltage (Vg) between time (T13-T14) is the second voltage);
a third voltage during a step of driving the element (Fig. 3, paragraphs 0049-0063, where the gate voltage (Vg) between time (T9-T13) is the third voltage).
Yamamoto is deficient in disclosing a memory comprising at least one phase change non-volatile memory cell;
a first switch comprising a first output terminal coupled to the light emitting element, a second output terminal coupled to the non-volatile memory and an input terminal coupled to a supply node by the transistor, the first switch being configured to connect the input terminal, according to a control voltage, either to the first output terminal or to the second output terminal.
However, Knez discloses a memory comprising at least one phase change non-volatile memory cell (Fig. 8, paragraph 0069, memory (78));
a first switch comprising a first output terminal coupled to the light emitting element, a second output terminal coupled to the non-volatile memory and an input terminal coupled to a supply node by the transistor, the first switch being configured to connect the input terminal, according to a control voltage, either to the first output terminal or to the second output terminal (Fig. 8, paragraphs 0077-0086, where switch (104) couples LED (103) to memory (78) or common voltage (110), which supplies a common voltage).
At the time of filing, it would have been obvious to a person of ordinary skill in the art to have modified the pixel comprising a memory cell as taught by Yamamoto by including a switch to connect the LED to the memory or supply node as taught by Knez. The suggestion/motivation would have been in order to storage image data as well as drive the LED in response to the image data (Knez, Abstract).
As to claim 2, Yamamoto discloses pixel, wherein the first voltage is higher than the second voltage and the second voltage is higher than the third voltage (Fig. 3, paragraphs 0049-0063, where the gate voltage (Vg) varies during periods shown in the graph).
As to claim 3, Yamamoto is deficient in disclosing pixel, wherein the first switch is configured to connect the second output and the input of the first switch during the steps of setting and resetting of the memory cells, and to connect the first output and the input of the first switch during the step of driving the element.
However, Knez discloses pixel, wherein the first switch is configured to connect the second output and the input of the first switch during the steps of setting and resetting of the memory cells, and to connect the first output and the input of the first switch during the step of driving the element (Fig. 8, paragraphs 0077-0086, where switch (104) couples LED (103) to memory (78) or common voltage (110)). In addition, the same motivation is used as claim 1.
As to claim 4, Yamamoto is deficient in disclosing pixel, wherein, during a step of reading at least one memory cell of the memory, the control voltage is equal to the third voltage and the first switch is configured to connect the second output and the input of the first switch.
However, Knez discloses pixel, wherein, during a step of reading at least one memory cell of the memory, the control voltage is equal to the third voltage and the first switch is configured to connect the second output and the input of the first switch (Fig. 8, paragraphs 0077-0086, where switch (104) is connected to memory (78) to read the memory). In addition, the same motivation is used as claim 1.
As to claim 5, Yamamoto pixel according, wherein the transistor is coupled to the supply node by a second switch (Fig. 4 and 5, paragraphs 0052-0057, where transistor (Tr1) is coupled to signal lines (DTL) by switches (Tr2, Tr3)).
As to claim 6, Yamamoto discloses pixel, wherein the second switch is configured to be closed for a first duration during the step of setting, for a second duration during the step of resetting and a third duration during the step of driving the element (Fig. 4-6, paragraphs 0052-0057, where switches (Tr2-Tr4) are closed and opened during different durations).
As to claim 7, Yamamoto discloses pixel, wherein the first duration is longer than the second duration and the second duration is longer than the third duration (Fig. 3, paragraphs 0048-0049, where the durations have different lengths as shown in the figure).
As to claim 8, Yamamoto discloses pixel, wherein the memory comprises between 20 and 50 cells (Fig. 1 and 2, paragraphs 0029-0032, where display panel (10) has several pixels (11, 12), which each contain memory circuit (12A)).
As to claim 9, Yamamoto discloses pixel, wherein the memory comprises a third switch comprising an input coupled to the second input terminal and an output coupled to each memory cell (Fig. 4-6, paragraphs 0052-0057, where memory (12A) is connected to switches (Tr2-Tr4)).
As to claim 10, Yamamoto is deficient in disclosing pixel, wherein the light emitting element is a light emitting diode.
However, Knez discloses pixel, wherein the light emitting element is a light emitting diode (Fig. 8, paragraph 0077, where LED (103) is a light emitting diode). In addition, the same motivation is used as claim 1.
As to claim 11, Yamamoto discloses a display screen comprising a plurality of pixels (Fig. 1 and 2, paragraphs 0029-0032, where display panel (10) has several pixels (11, 12)).
As to claim 12, Yamamoto and Knez disclose limitations similar to claim 1. In addition, Yamamoto discloses a calibration method of the pixel, comprising:
reading data in the memory;
driving the element according to the data read in the memory;
measuring the brightness of the element;
comparing the brightness to a set value;
if the brightness differs from the set value, modifying the value of said data by steps of setting and resetting (Fig. 2 and 3, paragraphs 0030-0050, where the brightness of organic EL device (13) is controlled based on memory circuit (12A)). In addition, the same motivation is used as claim 1.
As to claim 13, Yamamoto is deficient in disclosing pixel, wherein the at least one non-volatile memory cell is a phase change memory cell.
However, Knez discloses pixel, wherein the at least one non-volatile memory cell is a phase change memory cell (Fig. 8, paragraph 0069, memory (78)). In addition, the same motivation is used as claim 1.
Response to Arguments
Applicant’s arguments, see page 5, filed 6/25/2026, with respect to the 35 U.S.C. 112(b) rejection of claim 12 has been fully considered and are persuasive. The 35 U.S.C. 112(b) rejection of claim 12 has been withdrawn.
Applicant's arguments filed 6/25/2026 have been fully considered but they are not persuasive.
Applicant argues, with respect to claim 1, on pages 5-7, Knez fails to disclose the “first switch”. Examiner disagrees as Knez discloses, “first switch” (Fig. 8, paragraphs 0077-0086, where switch (104) couples LED (103) to memory (78) or common voltage (110), which supplies a common voltage).
Applicant argues, with respect to claim 1, on page 7, Yamamoto fails to disclose a control voltage taking voltage levels (reset, set, and driving). Examiner disagrees as Yamamoto discloses a control voltage taking voltage levels (reset, set, and driving) (Fig. 3, paragraphs 0049-0063, where the gate voltage (Vg) between time (T1-T3) is the first voltage, where the gate voltage (Vg) between time (T13-T14) is the second voltage, where the gate voltage (Vg) between time (T9-T13) is the third voltage).
Applicant argues, on pages 7-10, the application is in condition for allowance. Examiner disagrees for the reasons stated above.
Conclusion
THIS ACTION IS MADE FINAL. Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to ANEETA YODICHKAS whose telephone number is (571)272-9773. The examiner can normally be reached Monday-Friday 9-5.
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If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Ke Xiao can be reached at 571-272-7776. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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ANEETA YODICHKAS
Primary Examiner
Art Unit 2627
/ANEETA YODICHKAS/Primary Examiner, Art Unit 2627
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