DETAILED ACTION
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Priority
Applicant’s claim for the benefit of a prior-filed application under 35 U.S.C. 119(e) or under 35 U.S.C. 120, 121, or 365(c) is acknowledged. In addition, acknowledgment is made of applicant’s claim for foreign priority under 35 U.S.C. 119 (a)-(d). The certified copy has been filed in parent Application No. 19/115,314, filed on March 26, 2025.
Oath/Declaration
Oath/Declaration as filed on March 26, 2025 is noted by the Examiner.
Claim Objections
Claim 1 is objected to because of the following informalities:
The claim recites limitation “among the plurality of grayscale voltages” in fifth and sixth lines of the claim, but the limitation is indefinite, because it is unclear as to whether the target grayscale voltage or the first operating voltage recited in fourth thru fifth lines of the claim is being referred to as among the plurality of grayscale voltages. Therefore, Examiner suggests the limitation should be amended, without adding new matter, in a manner that resolves the indefiniteness issue. Accordingly, any claims dependent on claim 1 are objected to based on same above reasoning.
Claim 7 is objected to because of the following informalities:
In particular, acronym “IC” recited in second line of the claim renders the claim indefinite, because the meaning of the acronym is not apparent. Examiner recommends applicant amend claim 7, without adding new matter, in a way that clarifies the acronym. See MPEP § 2173.05(a) Accordingly, any claim(s) dependent on claim 7 are objected to based on same above reasoning.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102 of this title, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1-2, and 4 are rejected under 35 U.S.C. 103 as being unpatentable over Fujiwara, U.S. Patent Application Publication 2010/0026679 A1 (hereinafter Fujiwara), in view of Heo et al., U.S. Patent Application Publication 2020/0098297 A1 (hereinafter Heo).
Regarding claim 1, Fujiwara teaches a display driving device (1 FIGS. 1-3, paragraph[0029] of Fujiwara teaches the TFT liquid crystal display device 1 additionally includes a gate driver 20 and a source driver 30 for driving the dot pixels 11; the gate driver 20 is integrated within a semiconductor chip (not illustrated) and is connected to the gate lines G1 to G320; and the source driver 30 is integrated within another semiconductor chip and is connected to the data lines S1 to S240, and See also at least paragraphs[0026]-[0028], and [0034]-[0048] of Fujiwara (i.e., Fujiwara teaches a liquid crystal display device)) comprising: a grayscale voltage generation circuit configured to generate a plurality of grayscale voltages using a first operating voltage and a ground voltage; (37, VDD2 FIGS. 1-3, paragraph[0035] of Fujiwara teaches the source driver 30 includes a shift register 31, a data register 32, a latch circuit 33, a level shifter 34, a digital-analog converter (DAC) 35, an amplifier circuit 36, a grayscale voltage generator circuit 37, and a booster circuit 40 (or power supply circuit 40); and the amplifier circuit 36 incorporates amplifiers AMP1 to AMP240 having outputs connected to data lines S1 to S240, respectively, and See also at least paragraphs[0026]-[0029], [0034], and [0036]-[0048] of Fujiwara (i.e., Fujiwara teaches a liquid crystal display device having a grayscale voltage generator circuit that generates a set of grayscale voltages, wherein the grayscale voltage generator uses an output boosted voltage and a ground line));
a level shifter configured to level-shift a voltage of input data (34 FIGS. 1-3, paragraph[0044] of Fujiwara teaches the data register 32 sequentially receives the display data DATA from the timing controller 2 in synchronization with the latch signals from the shift register 31; the data register 32 has a capacity for the display data DATA for one line (that is, the display data DATA for 240 dot pixels 11); the latch circuit 33 latches a complete set of the display data for one line at the same time from the data register 32, and transfers the latched display data to the level shifter 34; the level shifter 34 provides level conversion for the display data received from the latch circuit 33, respectively, and transfers the display data to the DAC 35; the DAC 35 performs digital/analog conversion by selecting an output grayscale voltage corresponding to each of the display data received from the level shifter 34 from among the set of grayscale voltages fed from the grayscale voltage generator circuit 37; and the DAC 35 feeds the 240 output grayscale voltages, each of which is subjected to digital/analog conversion, to the amplifier circuit 36, and See also at least paragraphs[0026]-[0029], [0034]-[0043], and [0045]-[0048] of Fujiwara (i.e., Fujiwara teaches a liquid crystal display device having a source driver that includes a level shifter, wherein the level shifter provides level conversion of display data received from a latch circuit and transfers the display data to a DAC for selecting an output grayscale voltage from the grayscale voltage generator circuit corresponding to the converted display data)); but does not expressly teach to a target voltage, which is lower than the first operating voltage among the plurality of grayscale voltages, using the target grayscale voltage; and a grayscale voltage transmission line configured to transmit the target grayscale voltage from the grayscale voltage generation circuit to the level shifter.
However, Heo teaches to a target voltage, which is lower than the first operating voltage among the plurality of grayscale voltages, using the target grayscale voltage; and a grayscale voltage transmission line configured to transmit the target grayscale voltage from the grayscale voltage generation circuit to the level shifter (VLOUT1 FIGS. 1-4A, paragraph[0072] of Heo teaches the at least one level shifter unit may convert the level of at least one control signal from the control signal supply unit 215 (FIG. 1) to a voltage range that is equal to or greater than the first voltage VLOUT1 and equal to or less than the second voltage VLOUT2, and the at least one level shifter unit may output a switch control signal having a converted (e.g., higher) voltage level; and this is because the voltage level of the control signals S1 to SK are generally too low to drive switches (e.g., switches 21-1 to 21-4 and 22-1 to 22-3 in FIG. 3) in the voltage generation circuit 120, which may be relatively large in comparison to a typical CMOS switch, and See also at least paragraphs[0060], [0069]-[0071], [0073]-[0100], and [0145]-[0106] of Heo (i.e., Heo teaches level shifters that each convert at least one control signal to a first voltage that is in a range less than a second voltage, wherein each of the level shifters use the first voltage output, which is provided on an output line of a voltage generation unit, to define a respective level-shifted voltage range)).
Furthermore, Fujiwara and Heo are considered to be analogous art because they are from the same field of endeavor with respect to a display device, and involve the same problem of forming the display device with a source driver for suitably driving a display panel. Therefore, before the effective filing date of the claimed invention it would have been obvious to one of ordinary skill in the art to modify the system of Fujiwara based on Heo and Kim I to have a target voltage, which is lower than the first operating voltage among the plurality of grayscale voltages, using the target grayscale voltage; and a grayscale voltage transmission line configured to transmit the target grayscale voltage from the grayscale voltage generation circuit to the level shifter. One reason for the modification as taught by Heo is provide a suitable display driver integrated circuit (DDI) for a display apparatus (ABSTRACT and paragraphs[0002] and [0009] of Heo). The same motivation and rationale to combine for claim 1 mentioned above, in light of corresponding statement of grounds of rejection, applies to each respective dependent claim mentioned in the corresponding statement of grounds of rejection.
Regarding claim 2, Fujiwara and Heo teach the display driving device of claim 1, wherein the grayscale voltage transmission line includes: a first grayscale voltage transmission line configured to transmit a first grayscale voltage as the target grayscale voltage; and a second grayscale voltage transmission line configured to transmit, as the target grayscale voltage, a second grayscale voltage lower than the first grayscale voltage (VLOUT1 FIGS. 1-4A, paragraph[0072] of Heo teaches the at least one level shifter unit may convert the level of at least one control signal from the control signal supply unit 215 (FIG. 1) to a voltage range that is equal to or greater than the first voltage VLOUT1 and equal to or less than the second voltage VLOUT2, and the at least one level shifter unit may output a switch control signal having a converted (e.g., higher) voltage level; and this is because the voltage level of the control signals S1 to SK are generally too low to drive switches (e.g., switches 21-1 to 21-4 and 22-1 to 22-3 in FIG. 3) in the voltage generation circuit 120, which may be relatively large in comparison to a typical CMOS switch, and See also at least paragraphs[0060], [0069]-[0071], [0073]-[0100], and [0145]-[0106] of Heo (i.e., Heo teaches level shifters that each convert at least one control signal to a first voltage that is in a range less than a second voltage, wherein each of the level shifters use the first voltage output, which is provided on an output line of a voltage generation unit, to define a respective level-shifted voltage range)), and
wherein the level shifter includes: a first level shifter connected between the first grayscale voltage transmission line and a ground that supplies the ground voltage, and configured to level-shift a voltage of first input data among the input data to the first grayscale voltage; and a second level shifter connected between the second grayscale voltage transmission line and the ground, and configured to level-shift a voltage of second input data among the input data to the second grayscale voltage (110-1 to 110-K, GND FIGS. 1-4A, paragraphs[0074]-[0076] of Heo teach for example, each of the plurality of level shifter units 110-1 to 110-K (K>1, K being a natural number) may convert a level (e.g., a voltage level) of a corresponding control signal S1 to SK (K>1, K being a natural number) and may output a corresponding switch control signal SW1 to SWK (K>1, K being a natural number) at the converted level (e.g., the converted voltage level); for example, a first level shifter unit (e.g., the level shifter unit 110-1) may convert the first control signal in the first voltage range into the first switch control signal SW1 in the second voltage range that is different from (e.g., higher than) the first voltage range; for example, the second voltage range may be equal to or greater than the first voltage VLOUT1 and equal to or less than the second voltage VLOUT2; and the voltage generation circuit 120 may receive a plurality of reference voltages AVDD1 to AVDDn and a base voltage (e.g., a ground voltage GND) and may generate at least one voltage (e.g., the first voltage VLOUT1 and/or the second voltage VLOUT2) based on or in response to the plurality of reference voltages AVDD1 to AVDDn, the base voltage GND, and at least one switch control signal., and See also at least paragraphs[0060], [0069]-[0071]-[0073], [0077]-[0100], and [0145]-[0106] of Heo (i.e., Heo teaches separate level shifters that each convert at least one control signal to a first voltage that is in a range less than a second voltage, wherein each of the level shifters use the first voltage output, which is provided on an output line of a voltage generation unit, to define a respective level-shifted voltage range, and wherein each of the level shifters is interposed between the output line of the voltage generation unit and a line that provides a ground voltage)).
Regarding claim 4, Fujiwara and Heo teach the display driving device of claim 2, wherein the first level shifter and the second level shifter operate independently of each other (FIGS. 1-4A, paragraphs[0074]-[0076] of Heo teach for example, each of the plurality of level shifter units 110-1 to 110-K (K>1, K being a natural number) may convert a level (e.g., a voltage level) of a corresponding control signal S1 to SK (K>1, K being a natural number) and may output a corresponding switch control signal SW1 to SWK (K>1, K being a natural number) at the converted level (e.g., the converted voltage level); for example, a first level shifter unit (e.g., the level shifter unit 110-1) may convert the first control signal in the first voltage range into the first switch control signal SW1 in the second voltage range that is different from (e.g., higher than) the first voltage range; for example, the second voltage range may be equal to or greater than the first voltage VLOUT1 and equal to or less than the second voltage VLOUT2; and the voltage generation circuit 120 may receive a plurality of reference voltages AVDD1 to AVDDn and a base voltage (e.g., a ground voltage GND) and may generate at least one voltage (e.g., the first voltage VLOUT1 and/or the second voltage VLOUT2) based on or in response to the plurality of reference voltages AVDD1 to AVDDn, the base voltage GND, and at least one switch control signal., and See also at least paragraphs[0060], [0069]-[0071]-[0073], [0077]-[0100], and [0145]-[0106] of Heo (i.e., Heo teaches separate level shifters that each convert at least one control signal to a first voltage that is in a range less than a second voltage, wherein each of the level shifters use the first voltage output, which is provided on an output line of a voltage generation unit, to define a respective level-shifted voltage range, and wherein each of the level shifters is interposed between the output line of the voltage generation unit and a line that provides a ground voltage)).
Claim 7 is rejected under 35 U.S.C. 103 as being unpatentable over Fujiwara, in view Heo, and Kim, U.S. Patent Application Publication 2017/0272093 A1 (hereinafter Kim I).
Regarding claim 7, Fujiwara teaches a display device comprising: a source driver IC configured to drive data lines included in a display panel (1, 30, S1 to S240 FIGS. 1-3, paragraph[0029] of Fujiwara teaches the TFT liquid crystal display device 1 additionally includes a gate driver 20 and a source driver 30 for driving the dot pixels 11; the gate driver 20 is integrated within a semiconductor chip (not illustrated) and is connected to the gate lines G1 to G320; and the source driver 30 is integrated within another semiconductor chip and is connected to the data lines S1 to S240, and See also at least paragraphs[0026]-[0028], [0030], and [0034]-[0048] of Fujiwara (i.e., Fujiwara teaches a liquid crystal display device that includes a source driver, which is connected to data lines, for driving pixels and that is integrated with a semiconductor chip)); and a timing controller configured to transmit input data to be displayed through the display panel to the source driver IC and control an operation of the source driver IC, wherein the source driver IC includes: (2 FIGS. 1-3, paragraphs[0032]-[0033] of Fujiwara teaches the timing controller 2 outputs a frame switch signal FS for indicating the switching of the image frames; the frame switch signal FS is activated when the current frame data for the current image frame displayed on the liquid crystal display panel 10 is switched to next frame data for the next image frame; the frame data include the display data DATA for the complete set of the lines; in this embodiment, the gate clock signal GCLK, the horizontal synchronization signal HSYNC, and the frame switch signal FS, which are fed from the timing controller 2 to the gate driver 20, are activated after the gate driver 20 selects the gate line G320; in this case, the gate driver 20 then selects the gate line Gl in response to the gate clock signal GCLK, the horizontal synchronization signal HSYNC, and the frame switch signal FS; the timing controller 2 sequentially feeds the display data DATA for the respective lines to the source driver 30; in addition, the timing controller 2 feeds a clock signal CLK, a boosting clock signal VCLK, and a shift pulse signal STH to the source driver 30; and it should be noted that details of the configuration and operation of the source driver 30 will be described later, and See also at least paragraphs[0026]-[0029], [0030], [0032], and [0034]-[0048] of Fujiwara (i.e., Fujiwara teaches a liquid crystal display device that includes the source driver for driving pixels and that is integrated with the semiconductor chip, and timing controller that controls the feeding and receipt of data by the source driver, via a respective line for a current image frame displayed on display panel, and in even feeds clock signals for controlling output selection signals of a gate driver)) a grayscale voltage generation circuit configured to generate a first group of grayscale voltages using a first operating voltage and a second operating voltage, and generate a second group of grayscale voltages using the second operating voltage and a ground voltage (37, VDD2 FIGS. 1-3, paragraph[0035] of Fujiwara teaches the source driver 30 includes a shift register 31, a data register 32, a latch circuit 33, a level shifter 34, a digital-analog converter (DAC) 35, an amplifier circuit 36, a grayscale voltage generator circuit 37, and a booster circuit 40 (or power supply circuit 40); and the amplifier circuit 36 incorporates amplifiers AMP1 to AMP240 having outputs connected to data lines S1 to S240, respectively, and See also at least paragraphs[0026]-[0029], [0034], and [0036]-[0048] of Fujiwara (i.e., Fujiwara teaches a liquid crystal display device having a grayscale voltage generator circuit that is capable of generating sets of grayscale voltages, wherein the grayscale voltage generator uses output boosted voltage, which can be increased, and a ground line)); but does not expressly teach a first grayscale voltage transmission line configured to transmit a first grayscale voltage among the first group of grayscale voltages; a second grayscale voltage transmission line configured to transmit a second grayscale voltage among the second group of grayscale voltages; first level shifters, each connected between the first grayscale voltage transmission line and a ground that supplies the ground voltage, and configured to level-shift a voltage of each bit included in first parallel data among the input data to the first grayscale voltage; and second level shifters, each connected between the second grayscale voltage transmission line and the ground, and configured to level-shift a voltage of each bit included in second parallel data among the input data to the second grayscale voltage.
However, Heo teaches a first grayscale voltage transmission line configured to transmit a first grayscale voltage among the first group of grayscale voltages; a second grayscale voltage transmission line configured to transmit a second grayscale voltage among the second group of grayscale voltages (VLOUT1 FIGS. 1-4A, paragraph[0072] of Heo teaches the at least one level shifter unit may convert the level of at least one control signal from the control signal supply unit 215 (FIG. 1) to a voltage range that is equal to or greater than the first voltage VLOUT1 and equal to or less than the second voltage VLOUT2, and the at least one level shifter unit may output a switch control signal having a converted (e.g., higher) voltage level; and this is because the voltage level of the control signals S1 to SK are generally too low to drive switches (e.g., switches 21-1 to 21-4 and 22-1 to 22-3 in FIG. 3) in the voltage generation circuit 120, which may be relatively large in comparison to a typical CMOS switch, and See also at least paragraphs[0060], [0069]-[0071], [0073]-[0100], and [0145]-[0106] of Heo (i.e., Heo teaches level shifters that each convert at least one control signal to a first voltage that is in a range less than a second voltage, wherein each of the level shifters use the first voltage output, which is provided on an output line of a voltage generation unit, to define a respective level-shifted voltage range));
first level shifters, each connected between the first grayscale voltage transmission line and a ground that supplies the ground voltage, and configured to level-shift a voltage of; included in first parallel data among the input data to the first grayscale voltage; and second level shifters, each connected between the second grayscale voltage transmission line and the ground, and configured to level-shift a voltage of; included in second parallel data among the input data to the second grayscale voltage (110-1 to 110-K, GND FIGS. 1-4A, paragraphs[0074]-[0076] of Heo teach for example, each of the plurality of level shifter units 110-1 to 110-K (K>1, K being a natural number) may convert a level (e.g., a voltage level) of a corresponding control signal S1 to SK (K>1, K being a natural number) and may output a corresponding switch control signal SW1 to SWK (K>1, K being a natural number) at the converted level (e.g., the converted voltage level); for example, a first level shifter unit (e.g., the level shifter unit 110-1) may convert the first control signal in the first voltage range into the first switch control signal SW1 in the second voltage range that is different from (e.g., higher than) the first voltage range; for example, the second voltage range may be equal to or greater than the first voltage VLOUT1 and equal to or less than the second voltage VLOUT2; and the voltage generation circuit 120 may receive a plurality of reference voltages AVDD1 to AVDDn and a base voltage (e.g., a ground voltage GND) and may generate at least one voltage (e.g., the first voltage VLOUT1 and/or the second voltage VLOUT2) based on or in response to the plurality of reference voltages AVDD1 to AVDDn, the base voltage GND, and at least one switch control signal., and See also at least paragraphs[0060], [0069]-[0071]-[0073], [0077]-[0100], and [0145]-[0106] of Heo (i.e., Heo teaches separate level shifters that each convert at least one control signal to a first voltage that is in a range less than a second voltage, wherein each of the level shifters use the first voltage output, which is provided on an output line of a voltage generation unit, to define a respective level-shifted voltage range, and wherein each of the level shifters is interposed between the output line of the voltage generation unit and a line that provides a ground voltage)); but the combination of Fujiwara and Heo still do not expressly teach each bit; each bit.
However, Kim I teaches each bit; each bit (FIGS. 1-2, 4, and 10, paragraph[0091] of Kim I teach FIG. 10 is a schematic diagram illustrating an electronic device 1 including the source driver 10 according to an embodiment of the present invention; hereinafter, for convenience of explanation, the same content as the embodiments described above will be omitted; and referring to FIG. 10, the electronic device 1 according to an embodiment of the present invention may include the source driver 10 including the level shifter 100 which receives digital bits and provides a level-shifted output signal, the DAC 200 including a resistor string that provides a plurality of gradation voltages formed by receiving an upper limit voltage and a lower limit voltage respectively through one end and the other end, and a plurality of switches which are controlled by output signals and output a gradation voltage corresponding to the output signals, and the buffer amplifier 300 which amplifies the signal provided from the DAC 200, wherein the plurality of switches including NMOS switches in which a voltage is provided to body electrodes thereof, and a display panel driven by the source driver 10., and See also at least ABSTRACT, paragraphs[0013]-[0014], and [0037] of Kim I (i.e., Kim I teaches source drivers each having a respective level shifter that receives digital bits, wherein the level shifter provides a level shifter output signal)).
Furthermore, Fujiwara, Heo, and Kim I are considered to be analogous art because they are from the same field of endeavor with respect to a display device, and involve the same problem of forming the display device with a source driver for suitably driving a display panel. Therefore, before the effective filing date of the claimed invention it would have been obvious to one of ordinary skill in the art to modify the system of Fujiwara based on Heo and Kim I to have a first grayscale voltage transmission line configured to transmit a first grayscale voltage among the first group of grayscale voltages; a second grayscale voltage transmission line configured to transmit a second grayscale voltage among the second group of grayscale voltages; first level shifters, each connected between the first grayscale voltage transmission line and a ground that supplies the ground voltage, and configured to level-shift a voltage of each bit included in first parallel data among the input data to the first grayscale voltage; and second level shifters, each connected between the second grayscale voltage transmission line and the ground, and configured to level-shift a voltage of each bit included in second parallel data among the input data to the second grayscale voltage. One reason for the modification as taught by Heo is provide a suitable display driver integrated circuit (DDI) for a display apparatus (ABSTRACT and paragraphs[0002] and [0009] of Heo). Another reason for the modification as taught by Kim I is provide a display panel driving by a source drive that includes a level shifter which receives digital bits and provides a suitable level-shifted output signal (ABSTRACT and paragraphs[0002] and [0009] of Kim I).
Potentially Allowable Subject Matter
Claims 3, 5-6, and 8-10 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten to overcome applicable objection(s) indicated above, and if rewritten in independent form including all of the limitations of the base claim and any intervening claims, because for each of claims 3, 5-6, and 8-10 the prior art references of record do not teach the combination of all element limitations as presently claimed.
The prior art made of record and not relied upon is considered pertinent to applicant’s disclosure and include the following:
Nishina et al., U.S. Patent Application Publication 2006/0071893 A1 (hereinafter Nishina) teaches a source driver that drives a source line of a liquid crystal panel of a display device.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to ABDUL-SAMAD A ADEDIRAN whose telephone number is (571)272-3128. The examiner can normally be reached Monday through Thursday, 8:00 am to 5:00 pm.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Amr Awad can be reached at 571-272-7764. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/ABDUL-SAMAD A ADEDIRAN/Primary Examiner, Art Unit 2621