DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
Priority
Receipt is acknowledged of papers submitted under 35 U.S.C. 119(a)-(d), which papers have been placed of record in the file.
Information Disclosure Statement
The information disclosure statement (IDS) submitted on 03/262025 has been considered by the examiner. The submission is in compliance with the provisions of 37 CFR 1.97.
Specification
The title of the invention is not descriptive. A new title is required that is clearly indicative of the invention to which the claims are directed.
Claim Rejections - 35 USC § 112
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claims 6 and 9 are rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention.
Claims 6 and 9 recite the limitation "the recharge circuitry". There is insufficient antecedent basis for this limitation in the claim.
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale or otherwise available to the public before the effective filing date of the claimed invention.
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
Claims 1 – 4, 8 – 10, and 13 – 17 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Ikedo (US PgPub No. 2021/0168323).
Regarding claim 1, Ikedo teaches a light detecting device (figures 2A – 2B item 201, also figures 7A – 7B items 901 and 904 respectively) comprising: a first photodiode (figures 7A and 7B item 301); pixel readout circuitry coupled to the first photodiode, the pixel readout circuitry including a recharging circuit coupled to the photodiode (figures 7A and 7B item 302) and count rate control circuitry coupled between a node and a fixed voltage (figure 7B items 905 and 906 coupled between floating diffusion and ground; also figure 7A item 903 coupled between a node and a fixed voltage), the count rate control circuitry including a switch (figure 7B item 906); and counter circuitry coupled to an output of the pixel readout circuitry (figure 7B item 304), wherein the switch is configured to switch a first counting mode and a second counting mode (paragraphs 0068, 0102 and figure 3; TdL and TdS short and long pulse, counting modes).
Regarding claim 2, as mentioned above in the discussion of claim 1, Ikedo teaches all of the limitations of the parent claim. Additionally, Ikedo teaches wherein the first counting mode is a low-illuminance counting mode, and the second counting mode is a high-illuminance counting mode (paragraphs 0068, 0102 and figures 3 and 15; TdL and TdS short and long pulse, counting modes).
Regarding claim 3, as mentioned above in the discussion of claim 2, Ikedo teaches all of the limitations of the parent claim. Additionally, Ikedo teaches wherein a counting rate of the counter in the low-illuminance mode is higher than a counting rate of the counter in the high-luminance mode (figure 3; TdL with lower count rate VS TdS with higher count rate).
Regarding claim 4, as mentioned above in the discussion of claim 2, Ikedo teaches all of the limitations of the parent claim. Additionally, Ikedo teaches wherein a charge cycle of the first photodiode in a low-illuminance mode is longer than a charge cycle in the high-illuminance mode (figure 3; TdL with lower count rate VS TdS with higher count rate), in the low-illuminance mode, the counter circuitry increments a photon count value for each detected photon, in the high-illuminance mode, the counter circuitry increases the photon count value for each of a predetermined plurality of detected photons (figure 3; TdL with lower count rate with shorter pulse width VS TdS with higher count rate with longer pulse width).
Regarding claim 8, as mentioned above in the discussion of claim 1, Ikedo teaches all of the limitations of the parent claim. Additionally, Ikedo teaches wherein the pixel readout circuitry includes a first transistor coupled between the first photodiode and the node (figures 7A – 7B item 903 and 906 respectively).
Regarding claim 9, as mentioned above in the discussion of claim 8, Ikedo teaches all of the limitations of the parent claim. Additionally, Ikedo teaches wherein the recharge circuitry includes a second transistor connected between a voltage source and the first transistor (figures 7A – 7B item 302).
Regarding claim 10, as mentioned above in the discussion of claim 9, Ikedo teaches all of the limitations of the parent claim. Additionally, Ikedo teaches wherein the second transistor is configured to receive an external control signal that causes the second transistor to recharge the first photodiode (figures 7A – 7B item 302 controlled via Vbias to control item 301).
Regarding claim 13, as mentioned above in the discussion of claim 1, Ikedo teaches all of the limitations of the parent claim. Additionally, Ikedo teaches wherein the switch is configured to receive an external control signal that causes the switch to switch between the first counting mode and the second counting mode (figure 78B item 906 receives signal from Vcont to switch modes).
Regarding claim 14, Ikedo teaches an electronic apparatus (figures 1 and 14) comprising: a first photodiode (figures 7A and 7B item 301); pixel readout circuitry coupled to the first photodiode, the pixel readout circuitry including a recharging circuit coupled to the photodiode (figures 7A and 7B item 302) and count rate control circuitry coupled between a node and a fixed voltage (figure 7B items 905 and 906 coupled between floating diffusion and ground; also figure 7A item 903 coupled between a node and a fixed voltage), the count rate control circuitry including a switch (figure 7B item 906); and counter circuitry coupled to an output of the pixel readout circuitry (figure 7B item 304), wherein the switch is configured to switch between a first counting mode and a second counting mode (paragraphs 0068, 0102 and figure 3; TdL and TdS short and long pulse, counting modes).
Regarding claim 15, as mentioned above in the discussion of claim 14, Ikedo teaches all of the limitations of the parent claim. Additionally, Ikedo teaches wherein the first counting mode is a low-illuminance counting mode, and the second counting mode is a high-illuminance counting mode (paragraphs 0068, 0102 and figures 3 and 15; TdL and TdS short and long pulse, counting modes).
Regarding claim 16, as mentioned above in the discussion of claim 15, Ikedo teaches all of the limitations of the parent claim. Additionally, Ikedo teaches wherein a counting rate of the counter in the low-illuminance mode is higher than a counting rate of the counter in the high-luminance mode (figure 3; TdL with lower count rate VS TdS with higher count rate).
Regarding claim 17, as mentioned above in the discussion of claim 15, Ikedo teaches all of the limitations of the parent claim. Additionally, Ikedo teaches wherein a charge cycle of the first photodiode in a low-illuminance mode is longer than a charge cycle in the high-illuminance mode (figure 3; TdL with lower count rate VS TdS with higher count rate), in the low-illuminance mode, the counter circuitry increments a photon count value for each detected photon, in the high-illuminance mode, the counter circuitry increases the photon count value for each of a predetermined plurality of detected photons (figure 3; TdL with lower count rate with shorter pulse width VS TdS with higher count rate with longer pulse width).
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 5 – 7 and 18 – 20 are rejected under 35 U.S.C. 103 as being unpatentable over Ikedo (US PgPub No. 2021/0168323) in view of Inaoka (US PgPub No. 2020/0382726).
Regarding claim 5, as mentioned above in the discussion of claim 1, Ikedo teaches all of the limitations of the parent claim.
However, Ikedo fails to clearly teach wherein the pixel readout circuitry includes a resistor coupled between the first photodiode and the node. Inaoka, on the other hand teaches wherein the pixel readout circuitry includes a resistor coupled between the first photodiode and the node.
More specifically, Inaoka teaches wherein the pixel readout circuitry includes a resistor coupled between the first photodiode and the node (figure 5 item 223).
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention (AIA ) to incorporate the teachings of Inaoka with the teachings of Ikedo because in at least paragraphs 0055, 0097 – 0098, 0163, 0180 Inaoka teaches that using the invention results in reduce power consumption in a solid-state image sensor that detects weak light, thereby improving the system of Ikedo.
Regarding claim 6, as mentioned above in the discussion of claim 5, Ikedo in view of Inaoka teach all of the limitations of the parent claim.
Additionally, Additionally, Ikedo teaches wherein the recharge circuitry includes a transistor connected between a voltage source and the resistor (figure 5 item 272).
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention (AIA ) to incorporate the teachings of Inaoka with the teachings of Ikedo because in at least paragraphs 0055, 0097 – 0098, 0163, 0180 Inaoka teaches that using the invention results in reduce power consumption in a solid-state image sensor that detects weak light, thereby improving the system of Ikedo.
Regarding claim 7, as mentioned above in the discussion of claim 6, Ikedo in view of Inaoka teach all of the limitations of the parent claim.
Additionally, Additionally, Ikedo teaches wherein the transistor is configured to receive an external control signal that causes the transistor to recharge the first photodiode (figure 5 item 272).
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention (AIA ) to incorporate the teachings of Inaoka with the teachings of Ikedo because in at least paragraphs 0055, 0097 – 0098, 0163, 0180 Inaoka teaches that using the invention results in reduce power consumption in a solid-state image sensor that detects weak light, thereby improving the system of Ikedo.
Regarding claim 18, as mentioned above in the discussion of claim 14, Ikedo teaches all of the limitations of the parent claim.
However, Ikedo fails to clearly teach wherein the pixel readout circuitry includes a resistor coupled between the first photodiode and the node. Inaoka, on the other hand teaches wherein the pixel readout circuitry includes a resistor coupled between the first photodiode and the node.
More specifically, Inaoka teaches wherein the pixel readout circuitry includes a resistor coupled between the first photodiode and the node (figure 5 item 223).
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention (AIA ) to incorporate the teachings of Inaoka with the teachings of Ikedo because in at least paragraphs 0055, 0097 – 0098, 0163, 0180 Inaoka teaches that using the invention results in reduce power consumption in a solid-state image sensor that detects weak light, thereby improving the system of Ikedo.
Regarding claim 19, as mentioned above in the discussion of claim 18, Ikedo in view of Inaoka teach all of the limitations of the parent claim.
Additionally, Additionally, Ikedo teaches wherein the recharge circuitry includes a transistor connected between a voltage source and the resistor (figure 5 item 272).
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention (AIA ) to incorporate the teachings of Inaoka with the teachings of Ikedo because in at least paragraphs 0055, 0097 – 0098, 0163, 0180 Inaoka teaches that using the invention results in reduce power consumption in a solid-state image sensor that detects weak light, thereby improving the system of Ikedo.
Regarding claim 20, as mentioned above in the discussion of claim 19, Ikedo in view of Inaoka teach all of the limitations of the parent claim.
Additionally, Additionally, Ikedo teaches wherein the transistor is configured to receive an external control signal that causes the transistor to recharge the first photodiode (figure 5 item 272).
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention (AIA ) to incorporate the teachings of Inaoka with the teachings of Ikedo because in at least paragraphs 0055, 0097 – 0098, 0163, 0180 Inaoka teaches that using the invention results in reduce power consumption in a solid-state image sensor that detects weak light, thereby improving the system of Ikedo.
Claims 11 – 12 are rejected under 35 U.S.C. 103 as being unpatentable over Ikedo (US PgPub No. 2021/0168323) in view of Lee (US Patent No. 6,867,806).
Regarding claim 11, as mentioned above in the discussion of claim 1, Ikedo teaches all of the limitations of the parent claim.
However, Ikedo fails to clearly teach a second photodiode coupled to the pixel readout circuitry, wherein the first photodiode is connected in parallel with the second photodiode. Lee, on the other hand teaches a second photodiode coupled to the pixel readout circuitry, wherein the first photodiode is connected in parallel with the second photodiode.
More specifically, Lee teaches a second photodiode coupled to the pixel readout circuitry, wherein the first photodiode is connected in parallel with the second photodiode (abstract and figures 2A, 2B, 4A, 4B).
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention (AIA ) to incorporate the teachings of Lee with the teachings of Ikedo because in at least column 3 lines 6 – 10 and lines 52 - 54 Lee teaches that using the invention results in increase pixel sensitivity and improve the overall image quality through a special pixel design arrangement, thereby improving the system of Ikedo.
Regarding claim 12, as mentioned above in the discussion of claim 11, Ikedo in view of Lee teach all of the limitations of the parent claim.
Additionally, Additionally, Lee teaches wherein the pixel readout circuitry further includes: a first capacitor coupled between the first photodiode and a reference voltage (figures 2A, 2B, 4A, 4B; item ND next to item Pd1), a second capacitor coupled between the second photodiode and the reference voltage (figures 2A, 2B, 4A, 4B; item ND next to item Pd2), a first transistor coupled between the first photodiode and the node (figures 2A, 2B, 4A, 4B; item To next to item Pd1), and a second transistor coupled between the second photodiode and the node (figures 2A, 2B, 4A, 4B; item Te next to item Pd2).
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure.
Yuki (US patent No. 20060077270) teaches an image sensing apparatus is provided, which is provided with a plurality of image sensing elements each including a plurality of photoelectric conversion sections and an adding circuit adapted to add signals from the plurality of photoelectric conversion sections to obtain a one-pixel signal, wherein the adding circuit adds the signals such that the one-pixel signals obtained by the addition are arranged at equal intervals in an area extending over the plurality of image sensing elements.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to Usman A Khan whose telephone number is (571)270-1131. The examiner can normally be reached on M - Th 5:30 AM - 2 PM, F 5:30 AM - Noon.
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If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Sinh Tran can be reached on (571)272-7564. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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Usman Khan
/USMAN A KHAN/Primary Examiner, Art Unit 2637
10/06/2026
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