Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claims 1 – 13, 21 – 27 are pending.
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claim 1 is rejected under 35 U.S.C. 102a1 as being anticipated by Gao (cn115586964A).
As to claim 1, Gao discloses an input/output (1/O) expansion architecture, characterized by comprising: at least one IO expansion unit (Fig. 3), wherein the at least one 10 expansion unit comprises an expansion baseboard (Fig.3, and I/O fabric module), the expansion baseboard is provided with at least two peripheral component interface express (plurality of PCIe devices coupled together with soc switches) switch chips, a first preset quantity of internal connectors, and a second preset quantity of external connectors (Fig. 4, and para. 0004, where the external configuration is for 40 ports, and a pre-configured inter switch connections illustrated between switches); wherein one end of each of the internal connectors is connected to any one of the at least two PCIe Switch chips on the expansion baseboard, and a second end of the each of internal connectors is configured for interconnection between the at least two PCIe Switch chips (Fig. 4, and para. 004 where the two switches to the left illustrates the interconnection between switches); and one end of each of the external connectors is connected to any one of the at least two PCIe Switch chips on the expansion baseboard, and a second end of each of the external connectors is configured for being connected to a PCIe device, to achieve the interconnection between a plurality of PCIe devices (Fig. 3, and para. 0002, where the I/O fabric module is coupled between the compute module and the storage pool module).
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 2, 10, and 13 are rejected under 35 U.S.C. 103 as being unpatentable over Gao in view of LI (cn116032746a).
As to claim 2, Gao discloses an input/output (1/O) expansion architecture, comprising: at least one IO expansion unit (Fig. 3), wherein the at least one 10 expansion unit comprises an expansion baseboard (Fig.3, and I/O fabric module), the expansion baseboard is provided with at least two peripheral component interface express (plurality of PCIe devices coupled together with soc switches) switch chips , a first preset quantity of internal connectors, and a second preset quantity of external connectors (Fig. 4, and para. 0004, where the external configuration is for 40 ports, and a pre-configured inter switch connections illustrated between switches); wherein one end of each of the internal connectors is connected to any one of the at least two PCIe Switch chips on the expansion baseboard, and a second end of the each of internal connectors is configured for interconnection between the at least two PCIe Switch chips (Fig. 4, and para. 004 where the two switches to the left illustrates the interconnection between switches); and one end of each of the external connectors is connected to any one of the at least two PCIe Switch chips on the expansion baseboard, and a second end of each of the external connectors is configured for being connected to a PCIe device, to achieve the interconnection between a plurality of PCIe devices (Fig. 3, and para. 0002, where the I/O fabric module is coupled between the compute module and the storage pool module).
Gao does not explicitly disclose wherein the ID management unit is configured to: acquire ID signals of all the internal connectors and all the external connectors in the IO expansion architecture, and transmit the ID signals to the control module; and wherein the control module is configured to manage all of the at least two PCIe Switch chips in the IO expansion architecture based on all the ID signals.
Liu teaches wherein the ID management unit/control unit is configured to: acquire ID signals of all the internal connectors and all the external connectors in the IO expansion architecture, and transmit the ID signals to the control module; and wherein the control module is configured to manage all of the at least two PCIe Switch chips in the IO expansion architecture based on all the ID signals (Fig. 3, and page 5, paras. 0003 - 0005, where an id scheme to manage the i/o fabric resource is applied). One of ordinary skill in the art before the effective filing date of the claimed invention would have been motivated to use the control system of Liu in the system of Gao to manage the distributed system resource. (Page 2, and para. 0003).
As to claim 10, Gao discloses The IO switchboard, further comprising: a heat dissipation unit, configured to perform heat dissipation on the IO switchboard (Fig. 1, and page 4, and para. 0015, teaching a centralized heat management unit).
As to claim 13, Gao discloses the IO switchboard, characterized in that wherein the first preset quantity of the internal connectors are distributed on a first side of the corresponding expansion baseboard, and the second preset quantity of the external connectors are distributed on a second side of the corresponding expansion baseboard (Fig. 3 with I/O fabric comprising a plurality of pcie switches with internal connections as detailed in Fig. 4,page 5, para. 003); and the first side and the second side are opposite sides (Fig. 3, and page 5, para. 002 where the I/O fabric is coupled between the compute module and the NVme pool module).
Allowable Subject Matter
Claims 3 – 9, 11, 12, 21 – 26 are objected to as being dependent upon a rejected base claim but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure. US10585833, US10521376, and US11055252, among other teach a flexible topology of pcie switches networks in a computing system.
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/C.A.D/Examiner, Art Unit 2184
/HENRY TSAI/Supervisory Patent Examiner, Art Unit 2184
