DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
This Office Action is made in response to applicant’s preliminary amendment filed on 03/27/2025. Claims 1-9, 11, 12, 14-16, 18, 20, 22 and 24-26 are currently pending in the application. An action follows below:
Notice to Applicant(s)
Examiner notes that the specification is not the measure of invention. Therefore, limitations contained therein can’t be read into the claims for the purpose of avoiding the prior art. See In re Sporck, 55 CCPA 743, 386 F.2d 924, 155 USPQ 687 (1968).
Further, the names/ terms of the features/elements used in the pending application or pending claims may be different from the names/terms of the matching features/ elements of the prior arts; however, the matching features/ elements of the prior arts contain all characteristics/ functions of the features/elements DEFINED by the pending claims.
Note that in order to avoid confusion, the below citations in the below rejection(s) are mere one or more places in the reference to disclose the "claimed" limitation(s) and/or are directed to one or more of embodiments disclosed by the cited reference(s). In other words, the “claimed” features/limitations may be read in other places in the reference or other embodiments of the reference. In order to better understand how the claimed limitations are taught by the reference(s), a review of the entire reference(s) is suggested by the examiner. Applicant is reminded a prior art reference must be considered in its entirety, i.e., as a whole, including portions that would lead away from the claimed invention as not all relevant paragraphs may have been cited in the rejection. W.L. Gore & Associates, Inc. v. Garlock, Inc., 721 F.2d 1540, 220 USPQ 303 (Fed. Cir. 1983), cert. denied, 469 U.S. 851 (1984).
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102 of this title, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
FIRST SET OF REJECTIONS:
Claims 1-9, 11, 12, 14-16, 18, 20, 22 and 24-26 are rejected under 35 U.S.C. 103 as being unpatentable over Han et al. (WO 2022/204977 A1 cited in IDS; see the corresponding US 2024/0306441 A1 for the following citations; hereinafter Han) in view of Gu (CN 103886826 A; see the English translation cited in the attached PTO-892, for the following citations.)
As per claims 1 and 26, Han discloses a display device comprising a display panel (see at least ¶ 25,) wherein the display panel comprises:
a base substrate [0; see at least any of Figs. 3, 12, 20;)
at least one pixel driving circuit row group, wherein one of the at least one pixel driving circuit row group comprises two pixel driving circuit rows which are adjacent in a column direction, and one of the two pixel driving circuit rows comprises a plurality of pixel driving circuits distributed in a row direction (see at least Fig. 21, disclosing a plurality of pixel driving circuit row group, each pixel driving circuit row group comprising two pixel driving circuit rows which are adjacent in a column/vertical direction, and each pixel driving circuit rows comprises a plurality of pixel driving circuits 10 distributed in a row/horizontal direction;)
light-emitting units [OLEDs], wherein one of the pixel driving circuits is used to drive a corresponding light-emitting unit in the light-emitting units (see at least Figs. 1 and 21, disclosing a plurality of OLEDs, each associated with a corresponding pixel driving circuit 10,) the one of pixel driving circuits (see at least Fig. 1) comprises a seventh transistor [T7], a first electrode of the seventh transistor is connected to a second initialization signal line [Vinit2], a second electrode of the seventh transistor is connected to a first/anode electrode of the corresponding light-emitting unit [OLED], a gate of the seventh transistor is formed by a partial structure of a second reset signal line [Re2], and an orthographic projection of the second reset signal line on the base substrate extends along the row/X direction (see at least Fig. 4;)
wherein orthographic projections of two pixel driving circuit rows which are adjacent in a same pixel driving circuit row group on the base substrate are see at least Fig. 21 and Fig. 4/13.)
Accordingly, Han discloses all limitations of these claims except for a first symmetry axis and limitations associated with the first symmetry axis, as claimed.
However, in the same field of endeavor, Gu discloses a related display device comprising a display panel (see at least Figs. 4, 9; Abstract,) wherein orthographic projections of two pixel driving circuit rows [e.g., 901, 902; Fig. 9] which are adjacent in a same pixel driving circuit row group [each macro-pixel unit, as a group, comprising two rows (901, 902); Fig. 9; ¶ 90] on the base substrate [41; Fig. 4] are at least partially arranged in mirror symmetry with respect to a first symmetry axis being a signal line [44/ 906; Fig. 4, 9], the first symmetry axis extends along the row direction, and the two pixel driving circuit rows which are adjacent in the same pixel driving circuit row group share a same signal line [44/ 906], thereby reducing a number of wirings and saving wiring space (see at least Figs. 4, 9; ¶ 90.)
Han, discussed above, discloses the two pixel driving circuit rows, which are adjacent in the same pixel driving circuit row group, sharing the same second initialization signal line [Vinit2] disposed/ extending along the column direction. Han further teaches that the second initialization signal line [Vinit2] can be disposed/ extend along the row direction as the first initialization signal line [Vinit1] (see at least Fig. 7 disclosing the first initialization signal line [Vinit1] disposed/ extending along the row direction; ¶ 57 “… the orthographic projections of the first initial signal line Vinit1 and the second initial signal line Vinit2 on the base substrate may extend in the same direction as well …”.)
Furthermore, a change in location is generally recognized as being within the level of ordinary skill in the art, see In re Japikse, 86 USPQ 70 (CCPA 1950).
Therefore, it would have been obvious to one of ordinary skill in the art at the time before the effective filing date of invention of the pending application to modify the display panel of Gu to have the share signal line disposed/ extending along the row direction such that the orthographic projections of two pixel driving circuit rows, which are adjacent in the same pixel driving circuit row group, on the base substrate are at least partially arranged in mirror symmetry with respect to a first symmetry axis extending along the row direction and being the shared signal line, as the second initialization signal line [Vinit2] taught by the Gu reference, in view of the teaching in the Han reference, to improve the above modified display panel and display device of the Gu reference for the predictable result of reducing a number of wirings and saving wiring space. Accordingly, the above modified Gu in view of Han obviously renders all limitations of these claims.
As per claim 2, the above modified Gu obviously renders: wherein the second initialization signal line forms the first symmetry axis, and the orthographic projections of the two pixel driving circuit rows which are adjacent in the same pixel driving circuit row group on the base substrate are at least partially arranged in mirror symmetry with respect to the second initialization signal line (see the rejection of claim 1.)
As per claim 3, the above modified Gu obviously renders: wherein the one of the pixel driving circuits (see at least Fig. 1) further comprises a driving transistor [T3] and a fifth transistor [T5], a first electrode of the fifth transistor is connected to a first power supply line [VDD], and a second electrode of the fifth transistor is connected to a first electrode of the driving transistor (see Gu at least Fig. 1;) wherein the display panel further comprises:
a first conductive portion [13], wherein the first conductive portion is used to form a gate of the driving transistor [T3] (see Gu at least Fig. 6; ¶ 62:23-25;)
an enable signal line [EM], wherein an orthographic projection of the enable signal line on the base substrate extends along the row/X direction, and a partial structure of the enable signal line is used to form a gate of the fifth transistor [T5] (see Gu at least Fig. 6; ¶ 62:18-20;)
wherein in a same pixel driving circuit, an orthographic projection of the second reset signal line [Re2] on the base substrate is located at a side of the orthographic projection of the enable signal line [EM] on the base substrate away from an orthographic projection of the first conductive portion [13] on the base substrate (see Gu at least Fig. 6;)
wherein the orthographic projection of the second initialization signal line [Vinit2] on the base substrate is at least partially located between two adjacent second reset signal lines [Re2] in a same pixel driving circuit row group (the above modified Gu in view of Han obviously renders both the second initialization signal line [Vinit2] and the first initialization signal line [Vinit1] extending along the row direction so that the modified Figs. 4/13, 21 of Gu in view of Han obviously renders the orthographic projection of the second initialization signal line [Vinit2] on the base substrate being at least partially located between two adjacent second reset signal lines [Re2] in a same pixel driving circuit row group.)
As per claim 4, the above modified Gu obviously renders: wherein the second initialization signal line [Vinit2] comprises:
a first main body portion, wherein an orthographic projection of the first main body portion on the base substrate extends along the row direction (see Gu at least Fig. 3/4 modified by Han to dispose and extend the second initialization signal line [Vinit2] in the row/ X direction;)
a first protrusion (see Gu at least Fig. 3/4 modified by Han to dispose and extend the second initialization signal line [Vinit2] in the row/ X direction;) and
a second protrusion, wherein the first protrusion and the second protrusion are connected to two sides of the first main body portion in the column direction, respectively (see Gu at least Fig. 3/4 modified by Han to dispose and extend the second initialization signal line [Vinit2] in the row/ X direction;);
wherein in two pixel driving circuit rows which share a same second initialization signal line [Vinit2], the first main body portion is connected to the two pixel driving circuit rows through the first protrusion and the second protrusion, respectively (see the rejection of claim 1 for two pixel driving circuit rows sharing a same second initialization signal line [Vinit2]; further Gu at least Fig. 3/4 modified by Han to dispose and extend the second initialization signal line [Vinit2] in the row/ X direction.)
As per claim 5, the above modified Gu obviously renders: wherein the one of the pixel driving circuits (see Gu at least Fig. 1) further comprises a driving transistor [T3] and a second transistor [T2], a first electrode of the second transistor is connected to a gate of the driving transistor, and a second electrode of the second transistor is connected to a second electrode of the driving transistor (see Gu at least Fig. 1); wherein the display panel further comprises:
an active layer [shown in Gu Fig. 5] located at a side of the base substrate, wherein the active layer comprises a third active portion, and the third active portion is used to form a channel region of the driving transistor [T3] and wherein the active layer comprises a second active portion, and the second active portion is used to form a channel region of the second transistor [T2] (see Gu Fig. 5; ¶ 61 “… a part of structure of the active layer is configured to form channel regions of the transistors in the pixel-driving circuit …”);
a first conductive layer [shown in Gu Fig. 6] located at a side of the first active layer away from the base substrate, wherein the first conductive layer comprises a first conductive portion, an orthographic projection of the first conductive portion on the base substrate covers an orthographic projection of the third active portion on the base substrate, and the first conductive portion is used to form the gate of the driving transistor [T3] (see Gu at least Fig. 6; ¶ 62,) wherein the first conductive layer comprises a first gate line [Gate], an orthographic projection of the first gate line on the base substrate extends along the row/ X direction and covers an orthographic projection of the second active portion on the base substrate, and a partial structure of the first gate line is used to form a top gate of the second transistor [T2] (see Gu at least Figs. 4, 6; ¶ 62;)
a third conductive layer [shown in Gu Fig. 8] located at a side of the see Gu at least Fig. 8),
wherein the third conductive layer further comprises the second initialization signal line [Vinit2] (see Gu at least Fig. 8; ¶ 64:1-4.)
Accordingly, Gu teaches all limitations of this claim except that Gu teaches to use the active layer to form both the channel region of the driving transistor and the channel region of the second transistor [T2], instead of to use two separate active layers, a first active layer forming the channel region of the driving transistor and a second active layer forming the channel region of the second transistor [T2], as claimed. However, a modification which would have involved a mere change in the separation of one element into two or more elements was judicially recognized as being within the level of ordinary skill in the art, In Nerwin v. Erlichman, 168 USPQ 177, 179 (PTO Bd. of Int. 1969) and a modification which would have involved a mere change in location is generally recognized as being within the level of ordinary skill in the art, see In re Japikse, 86 USPQ 70 (CCPA 1950). Therefore, it would have been obvious to a person of ordinary skill in the art to separate the Gu active layer into the first and second active layers and to locate components, as desired as claimed, since a such modification would have involved a mere change in the separation of one layer into two separate layers and a mere change in location(s) of the component(s) is generally recognized as being within the level of ordinary skill in the art.
Further, Gu, discussed above, discloses the first gate line [Gate] in the first conductive layer, instead of the third conductive layer, as claimed. However, a modification which would have involved a mere change in location is generally recognized as being within the level of ordinary skill in the art, see In re Japikse, 86 USPQ 70 (CCPA 1950). Therefore, it would have been obvious to a person of ordinary skill in the art to locate the first gate line [Gate] in the third conductive layer, as desired as claimed, since a such modification would have involved a mere change in the locations of component(s) is generally recognized as being within the level of ordinary skill in the art. Therefore, it would have been obvious to a person of ordinary skill in this art to further modify the Gu reference to obtain the invention as specified in this claim.
As per claim 6, the above modified Gu obviously renders: wherein the one of the pixel driving circuits (see Gu Fig. 1) further comprises a driving transistor [T3] and a first transistor [T1], a first electrode of the first transistor is connected to a first initialization signal line [Vinit1], and a second electrode of the first transistor is connected to a second electrode of the driving transistor [T3] (see Gu Fig. 1;)
wherein at least one pixel driving circuit row group comprises a plurality of pixel driving circuit row groups, the plurality of pixel driving circuit row groups are distributed in the column direction (see the rejection of claim 1), and two pixel driving circuit rows are located in different pixel driving circuit row groups and are adjacent (see the rejection of claim 1.)
Accordingly, the above modified Gu obviously renders all limitations of this claim, but is silent to the two pixel driving circuit rows, which are located in different pixel driving circuit row groups and are adjacent, share a same first initialization signal line [Vinit1], as claimed.
However, since Gu further teaches the two pixel driving circuit rows, which are adjacent in the same pixel driving circuit row group, connecting to receive the same initialization signal [Vinit1] (see at least Fig. 21) and Han, as discussed in the rejection of claim 1, discloses that the two pixel driving circuit rows, which are adjacent in the same pixel driving circuit row group, share a same signal line [44/ 906] to receive the same signal, thereby reducing a number of wirings and saving wiring space (see at least Figs. 4, 9; ¶ 90,) it would have been obvious to one of ordinary skill in the art at the time before the effective filing date of invention of the pending application to further apply the above technique of having the two pixel driving circuit rows, which are adjacent in the same pixel driving circuit row group, sharing the same signal line such as the first initialization signal line to receive the same first initialization signal, in view of the teaching in the Han reference, to improve the above modified display panel and display device of the Gu reference for the predictable result of further reducing a number of wirings of the first initialization signal lines and saving wiring space. Accordingly, the above modified Gu in view of Han obviously renders all limitations of this claim.
As per claim 7, the above modified Gu obviously renders: the display panel further comprising:
a first conductive portion [13], wherein the first conductive portion is used to form a gate of the driving transistor [T3] (see Gu at least Fig. 6; ¶ 62:23-25;)
a first reset signal line [Re1], wherein an orthographic projection of the first reset signal line [Re1] on the base substrate extends along the row/ X direction, and a partial structure of the first reset signal line is used to form a gate of the first transistor [T1] (see Gu at least Figs. 9, 10; ¶ 62;)
wherein the orthographic projection of the first reset signal line [Re1] on the base substrate is located at a side of an orthographic projection of the first conductive portion [13] on the base substrate away from the orthographic projection of the second reset signal line [Re2] on the base substrate (see Gu at least Figs. 4, 6; also see Figs. 9, 10 and ¶ 62, if necessary;)
wherein in two adjacent pixel driving circuit rows which share a same first initialization signal line, an orthographic projection of the first initialization signal line on the base substrate is at least partially located between orthographic projections of first reset signal lines in the two adjacent pixel driving circuit rows on the base substrate (see the rejection of claim 6 for two adjacent pixel driving circuit rows which share a same first initialization signal line; further see Gu at least Figs. 4/13, 21, disclosing an orthographic projection of the first initialization signal line [Vinit1] on the base substrate at least partially located between orthographic projections of first reset signal lines [Re1] in the two adjacent pixel driving circuit rows on the base substrate.)
As per claim 8, the above modified Gu obviously renders: the display panel further comprising:
a first active layer [shown in Gu Fig. 5] located at a side of the base substrate, wherein the first active layer comprising a first active portion and a ninth active portion, the first active portion is used to form a channel region of the first transistor [T1], and in the two adjacent pixel driving circuit rows which share the same first initialization signal line [Vinit1], the ninth active portion is connected between two first active portions in the two adjacent pixel driving circuit rows (see the rejection of claim 6 for the two adjacent pixel driving circuit rows which share the same first initialization signal line [Vinit1]; further see Gu at least Fig. 5; ¶ 61);
wherein the first initialization signal line [Vinit1] is connected to the ninth active portion through a via hole (see Gu at least Figs. 4-5; ¶ 64.)
As per claim 9, the above modified Gu obviously renders: wherein the one of the pixel driving circuits (see Gu at least Fig. 1) further comprises a second transistor [T2], a first electrode of the second transistor is connected to a gate of the driving transistor [T3], and a second electrode of the second transistor is connected to the second electrode of the driving transistor (see Gu at least Fig. 1);
wherein the display panel further comprises:
an active layer [shown in Gu Fig. 5] located at a side of the base substrate, wherein at least a partial structure of the active layer is used to form a channel region of the driving transistor [T3] and at least a partial structure of the active layer is used to form a channel region of the second transistor [T2] (see Gu Fig. 5; ¶ 61 “… a part of structure of the active layer is configured to form channel regions of the transistors in the pixel-driving circuit …”);
a first conductive layer [shown in Gu Fig. 6] located at a side of the first active layer away from the base substrate, wherein at least a partial structure of the first conductive layer is used to form the gate of the driving transistor [T3] and at least a partial structure of the first conductive layer is used to form a top gate of the second transistor [T2] (see Gu at least Fig. 6; ¶ 62:23-25;)
a fourth conductive layer [a second conductive layer shown in Gu Fig. 7] see Gu Fig. 7.)
Accordingly, Gu teaches all limitations of this claim except that Gu teaches to use the first active layer to form both the channel region of the driving transistor and the channel region of the second transistor [T2], instead of to use two separate active layers, the first active layer forming the channel region of the driving transistor and the second active layer forming the channel region of the second transistor [T2], as claimed, and Gu further teaches to use the first conductive layer to form both the gate of the driving transistor [T3] and the top gate of the second transistor [T2], instead of to use two separate conductive layers, the first conductive layer forming the gate of the driving transistor [T3] and the third conductive layer forming the top gate of the second transistor [T2], as claimed.
However, a modification which would have involved a mere change in the separation of one element into two or more elements was judicially recognized as being within the level of ordinary skill in the art, In Nerwin v. Erlichman, 168 USPQ 177, 179 (PTO Bd. of Int. 1969); and a change in location(s) of component(s) is generally recognized as being within the level of ordinary skill in the art, see In re Japikse, 86 USPQ 70 (CCPA 1950). Therefore, it would have been obvious to a person of ordinary skill in the art to separate the Gu active layer into the first and second active layers and the Gu first conductive layer into the first and third conductive layers and to locate these layers, as desired as claimed, since a such modification would have involved a mere change in the separation of one layer into two separate layers and a mere change in the locations of components are generally recognized as being within the level of ordinary skill in the art. Therefore, it would have been obvious to a person of ordinary skill in this art to further modify the Gu reference to obtain the invention as specified in this claim.
In the alternative of claim 9, the above modified Gu, as discussed in the rejection of claim 6, obvious renders: wherein the one of the pixel driving circuits (see Gu Fig. 1) further comprises a driving transistor [T3] see at least Fig. 21.)
However, since Gu further teaches the two pixel driving circuit rows, which are adjacent in the same pixel driving circuit row group, connecting to receive the same third initialization signal [Vinit3] (see at least Fig. 21) and Han, as discussed in the rejection of claim 1, discloses that the two pixel driving circuit rows, which are adjacent in the same pixel driving circuit row group, share a same signal line [44/ 906] to receive the same signal, thereby reducing a number of wirings and saving wiring space (see at least Figs. 4, 9; ¶ 90,) it would have been obvious to one of ordinary skill in the art at the time before the effective filing date of invention of the pending application to further apply the above technique of having the two pixel driving circuit rows, which are adjacent in the same pixel driving circuit row group, sharing the same signal line such as the third initialization signal line to receive the same first initialization signal, in view of the teaching in the Han reference, to improve the above modified display panel and display device of the Gu reference for the predictable result of further reducing a number of wirings of the third initialization signal lines and saving wiring space.
Accordingly, the above modified Gu in view of Han obviously renders all limitations of this claim, but is silent to an eighth transistor, as claimed. Official Notice is taken that both the concept and the advantages of providing an [[eighth]] transistor comprising a first electrode connected to a third initialization signal line and a second electrode connected to a first electrode of the driving transistor, in a pixel driving circuit in the display panel to obtain the gate-source difference being the same, and thus eliminating the threshold drift of the driving transistor by hysteresis are well-known and expected in the art. Therefore, it would have been obvious to a person of ordinary skill in the art before the effective filing date of invention of the pending application to include the [[eighth]] transistor in the Gu pixel driving circuit, as this [[eighth]] transistor to eliminate the threshold drift of the driving transistor by hysteresis. Accordingly, the above modified Gu in view of Han obviously renders all limitations of this claim.
Note that before challenging the Office action on the eight transistor in this claim, the Applicant should review the Zhu reference (WO 2023/159503A; cited in the second set of rejections below), specifically the element T9 in Fig. 4B with the benefit at ¶ 85.
As per claim 11, the above modified Gu obviously renders: wherein the third initialization signal line [Vinit3] (see Gu at least Figs. 13, 16, 19) comprises:
a second main body portion, wherein an orthographic projection of the second main body portion on the base substrate extends along the row/X direction (see Gu at least Figs. 13, 16, 19; ¶ 78);
a third protrusion (see Gu at least Figs. 13, 16, 19; ¶ 78); and
a fourth protrusion (see Gu at least Figs. 13, 16, 19), wherein the third protrusion and the fourth protrusion are connected to two sides of the second main body portion in the column/ Y direction, respectively (see Gu at least Figs. 13, 16, 19; ¶ 78);
wherein in two pixel driving circuit rows that share the same third initialization signal line (see the rejection of claim 9,) the second main body portion is connected to the two pixel driving circuit rows through the third protrusion and the fourth protrusion, respectively (see Gu at least Figs. 13, 16, 19; ¶ 78.)
As per claim 12, the above modified Gu obviously renders: wherein an orthographic projection of the third initialization signal line on the base substrate at least partially overlaps with an orthographic projection of the second initialization signal line on the base substrate (see Gu at least Fig. 20; ¶ 78: “the respective second initial signal lines Vinit2 may be connected to the respective third initial signal lines Vinit3 through via holes respectively. In the display panel, the third initial signal line Vinit3 and the second initial signal line Vinit2 may form a grid structure, thereby further reducing the voltage drop of the second initial signal. In other exemplary embodiments, it may connect only a part of the third initial signal lines to at least a part of the second initial signal lines through via holes in the display panel …”.)
In the alternative of claim 12, see the rejection of claim 5 for similar limitations. Gu further discloses the third conductive layer comprising the third initialization signal line [Vinit3] (see Gu at least Fig. 16/19, disclosing the first initialization signal line [Vinit1] and the third initialization signal line [Vinit3] on the same conductive layer; further see ¶ 57 “… both the first initial signal line Vinit1 and the second initial signal line Vinit2 may be located in the third conductive layer …”; therefore, a person of ordinary skill in the art before the effective filing date of invention of the pending application would have obviously realized the third conductive layer comprising the third initialization signal line [Vinit3].)
As per claim 14, see the rejection of claim 5 for similar limitations. Gu further discloses: wherein the third conductive layer further comprises a first bridging portion, and the first bridging portion is connected to the gate of the driving transistor [T2] and the first electrode of the second transistor [T2] through via holes (see Gu at least Figs. 1, 4; ¶ 64 “… The connecting part 32 may be connected to the third conductive part 13 and the second active part 42 respectively through the via holes, so as to connect the first end of the second transistor T2 to the gate end of the driving transistor T3 …”.)
As per claim 15, the above modified Gu obviously renders: wherein the one of the pixel driving circuits (see Gu Fig. 1) further comprises a capacitor [C], a first electrode of the capacitor is connected to the gate of the driving transistor [T3], and a second electrode of the capacitor is connected to the first power supply line [VDD] (see Gu at least Fig. 1; ¶ 52);
wherein the first conductive layer [Gu Fig. 6] comprises a first conductive portion, and the first conductive portion is used to form the gate of the driving transistor [T3], and the first conductive portion is reused as the first electrode of the capacitor [C] (see at least Fig. 6; ¶ 62,)
wherein the display panel further comprises:
a second conductive layer between the third conductive layer and the first conductive layer, wherein the second conductive layer comprises a second conductive portion, an orthographic projection of the second conductive portion on the base substrate at least partially overlaps with an orthographic projection of the first conductive portion on the base substrate, and the second conductive portion is used to form the second electrode of the capacitor [C] (see at least Figs. 4-10; ¶¶ 62-64;)
wherein the first bridging portion comprises a main body portion and an extension portion, the main body portion is connected to the gate of the driving transistor [T3] and the first electrode of the second transistor through via holes, and an orthographic projection of the extension portion on the base substrate at least partially overlaps with the orthographic projection of the second conductive portion on the base substrate (see Gu at least Figs. 1, 4; ¶ 64 “As shown in FIGS. 4, 5 and 8 … as shown in The connecting part 32 may be connected to the third conductive part 13 and the second active part 42 respectively through the via holes, so as to connect the first end of the second transistor T2 to the gate end of the driving transistor T3 …”), wherein the main body portion comprises a first side, the extension comprises a second side, the first side is connected to the second side, and an angle between an orthographic projection of the first side on the base substrate and an orthographic projection of the second side on the base substrate is less than 180 (see Gu at least ¶ 74 “In this exemplary embodiment, as shown in FIGS. 4 and 8 … an angle between an orthographic projection of the first side 351 on the base substrate and an orthographic projection of the second side 352 on the base substrate may be less than 180° …)
As per claim 16, see the rejection of claim 5 or 14 for similar limitations. Gu further discloses: wherein the third conductive layer further comprises a second bridging portion, and the second bridging portion is connected to the second electrode of the second transistor [T2] and the second electrode of the driving transistor [T3] through via holes (see Gu at least Figs. 1, 4; ¶ 64 “… The connecting part 32 may be connected to the third conductive part 13 and the second active part 42 respectively through the via holes, so as to connect the first end of the second transistor T2 to the gate end of the driving transistor T3 …”.)
In the alternative of claim 16, see the rejection of claims 9 and 12 for similar limitations. The above modified Gu obviously renders the first electrode of the driving transistor [T3], the second electrode of the fifth transistor [T5], and the second electrode of the eighth transistor (see the rejection of claim 9 for the eighth transistor and its connections; further see Gu Fig. 1 disclosing the first electrode of the driving transistor [T3] connected to the second electrode of the fifth transistor [T5]; the above modified obviously rendering the first electrode of the driving transistor [T3], the second electrode of the fifth transistor [T5], and the second electrode of the eighth transistor connected to each other.) Accordingly, the above modified Gu obviously renders all limitations of this claim except for a third bridging portion, as claimed. Official Notice is taken that both the concept and the advantages of providing a third bridging portion in the third conductive layer and connected to the first electrode of the driving transistor, the second electrode of the fifth transistor, and the second electrode of the eighth transistor through via holes, respectively, in the display panel are well-known and expected in the art. Therefore, it would have been obvious to a person of ordinary skill in the art before the effective filing date of invention of the pending application to further modify the above modified display panel of Gu to include a third bridging portion in the third conductive layer and connected to the first electrode of the driving transistor, the second electrode of the fifth transistor, and the second electrode of the eighth transistor through via holes, respectively, to obtain the same predictable result.
As per claim 18, see the rejection of claim 5 for similar limitations. Gu further discloses: a fourth conductive layer located at a side of the third conductive layer away from the base substrate, wherein the fourth conductive layer comprises a first gate connection line, an orthographic projection of the first gate connection line on the base substrate extends along the row direction, and the first gate connection line is connected to the first gate line [Gate] through one or more via hole (see at least Figs. 4, 6, 9, 10; ¶ 62.)
In the alternative of claim 18, the above modified Gu obviously renders: wherein the one of the pixel driving circuits (see Fig. 1) further comprises a driving transistor [T3], a second transistor [T2] and a fourth transistor [T4], a first electrode of the second transistor [T2] is connected to a gate of the driving transistor [T3], a second electrode of the second transistor [T2] is connected to a second electrode of the driving transistor [T3], a first electrode of the fourth transistor [T4] is connected to a data line [Da], and a second electrode of the fourth transistor [T4] is connected to a first electrode of the driving transistor [T3] (see Fig. 1;)
wherein the display panel further comprises:
an active layer [shown in Gu Fig. 5] located at a side of the base substrate, wherein the active layer comprises a fourth active region used to form a channel region of the fourth transistor [T4] and at least a partial structure of the active layer is used to form a channel region of the second transistor [T2] (see Gu Fig. 5; ¶ 61 “… a part of structure of the active layer is configured to form channel regions of the transistors in the pixel-driving circuit …”);
a first conductive layer [shown in Gu Fig. 6] located at a side of the first active layer away from the base substrate, wherein the first conductive layer comprises a second gate line, an orthographic projection of the second gate line on the base substrate covers an orthographic projection of the fourth active portion on the base substrate, and a partial structure of the second gate line is used to form a gate of the fourth transistor and at least a partial structure of the first conductive layer is used to form a top gate of the second transistor [T2] (see Gu at least Fig. 6; ¶ 62:23-25;)
a fourth conductive layer [a second conductive layer shown in Gu Fig. 7] see Gu Figs. 4, 7.)
Accordingly, Gu teaches all limitations of this claim except that Gu teaches to use the first active layer to form both the channel region of the fourth transistor and the channel region of the second transistor [T2], instead of to use two separate active layers, the first active layer forming the channel region of the fourth transistor [T4] and the second active layer forming the channel region of the second transistor [T2], as claimed, and Gu further teaches to use the first conductive layer to form both the gate of the fourth transistor [T4] and the top gate of the second transistor [T2], instead of to use two separate conductive layers, the first conductive layer forming the gate of the fourth transistor [T4] and the third conductive layer forming the top gate of the second transistor [T2], as claimed.
However, a modification which would have involved a mere change in the separation of one element into two or more elements was judicially recognized as being within the level of ordinary skill in the art, In Nerwin v. Erlichman, 168 USPQ 177, 179 (PTO Bd. of Int. 1969); and a change in location(s) of component(s) is generally recognized as being within the level of ordinary skill in the art, see In re Japikse, 86 USPQ 70 (CCPA 1950). Therefore, it would have been obvious to a person of ordinary skill in the art to separate the Gu active layer into the first and second active layers and the Gu first conductive layer into the first and third conductive layers and to locate these layers, as desired as claimed, since a such modification would have involved a mere change in the separation of one layer into two separate layers and a mere change in the locations of components are generally recognized as being within the level of ordinary skill in the art. Therefore, it would have been obvious to a person of ordinary skill in this art to further modify the Gu reference to obtain the invention as specified in this claim.
As per claim 20, the above modified Gu obviously renders: wherein the one of the pixel driving circuits (see Gu at least Fig. 1) further comprises a driving transistor [T3] and a second transistor [T2], a first electrode of the second transistor is connected to a gate of the driving transistor, and a second electrode of the second transistor is connected to a second electrode of the driving transistor (see Gu at least Fig. 1);
wherein the display panel further comprises:
an active layer [shown in Gu Fig. 5] located at a side of the base substrate, wherein at least a partial structure of the first active layer is used to form a channel region of the driving transistor (see Gu Fig. 5; ¶ 61 “… a part of structure of the active layer is configured to form channel regions of the transistors in the pixel-driving circuit …”); wherein the active layer comprises a second active portion, and a twentieth active portion and a twenty-first active portion connected to two ends of the second active portion in the row/ X direction, the second active portion is used to form a channel region of the second transistor (see Gu Fig. 5; ¶ 61 “… a part of structure of the active layer is configured to form channel regions of the transistors in the pixel-driving circuit …”), the twentieth active portion is used to form the first electrode of the second transistor, and the twenty-first active portion is used to form the second electrode of the second transistor (see Gu Fig. 5; ¶ 61); and
a first conductive layer [shown in Gu Fig. 6] located at a side of the first active layer away from the base substrate, wherein at least a partial structure of the first conductive layer is used to form the gate of the driving transistor [T3] (see Gu at least Fig. 4, 6; ¶ 62), and wherein the first conductive layer comprises a first gate line [Gate], the first gate line comprises a third main body portion and a fifth protrusion connected to a side of the third main body portion in the column/Y direction (see Gu at least Fig. 4, 6; ¶ 62), an orthographic projection of the third main body portion on the base substrate extends along the row/X direction, and an orthographic projection of the fifth protrusion on the base substrate covers an orthographic projection of the second active portion on the base substrate (see Gu at least Fig. 4, 6; ¶ 62);
a third conductive layer [shown in Gu Fig. 8] located at a side of the see Gu at least Fig. 8)
Accordingly, Gu teaches all limitations of this claim except that Gu teaches to use the active layer to form both (i) the channel region of the driving transistor and (ii) a second active portion, and a twentieth active portion and a twenty-first active portion connected to two ends of the second active portion in the row/ X direction, the second active portion is used to form a channel region of the second transistor [T2], instead of to use two separate active layers, a first active layer forming the channel region of the driving transistor and a second active layer including a second active portion, and a twentieth active portion and a twenty-first active portion connected to two ends of the second active portion in the row/ X direction, the second active portion is used to form a channel region of the second transistor [T2], as claimed. However, a modification which would have involved a mere change in the separation of one element into two or more elements was judicially recognized as being within the level of ordinary skill in the art, In Nerwin v. Erlichman, 168 USPQ 177, 179 (PTO Bd. of Int. 1969) and a mere change in location(s) of element(s) is generally recognized as being within the level of ordinary skill in the art, see In re Japikse, 86 USPQ 70 (CCPA 1950). Therefore, it would have been obvious to a person of ordinary skill in the art to separate the Gu active layer into the first and second active layers, as desired as claimed, since a such modification would have involved a mere change in the separation of one layer into two separate layers and a mere change in location(s) of element(s) is generally recognized as being within the level of ordinary skill in the art.
Further, Gu, discussed above, discloses the first gate line [Gate] in the first conductive layer, instead of the third conductive layer, as claimed. However, a modification which would have involved a mere change in location is generally recognized as being within the level of ordinary skill in the art, see In re Japikse, 86 USPQ 70 (CCPA 1950). Therefore, it would have been obvious to a person of ordinary skill in the art to locate the first gate line [Gate] in the third conductive layer, as desired as claimed, since a such modification would have involved a mere change in the locations of component(s) is generally recognized as being within the level of ordinary skill in the art. Therefore, it would have been obvious to a person of ordinary skill in this art to further modify the Gu reference to obtain the invention as specified in this claim.
In the alternative of claim 20, the above modified Gu obviously renders: wherein the one of the pixel driving circuits (see Fig. 1) further comprises a driving transistor [T3], a fourth transistor [T4] and a fifth transistor [T5], a first electrode of the fifth transistor is connected to the first power supply line [VDD], a second electrode of the fifth transistor is connected to a first electrode of the driving transistor, a first electrode of the fourth transistor is connected to a data line [Da], and a second electrode of the fourth transistor [T4] is connected to the first electrode of the driving transistor [T3] (see Fig. 1);
wherein the display panel further comprises:
a first active layer [shown in Gu Fig. 5] comprising a third active portion, a fourth active portion and a fifth active portion, wherein the third active portion is used to form a channel region of the driving transistor [T3], the fourth active portion is used to form a channel region of the fourth transistor [T4], and the fifth active portion is used to form a channel region of the fifth transistor [T5] (see Gu Fig. 5; ¶ 61 “… a part of structure of the active layer is configured to form channel regions of the transistors in the pixel-driving circuit …”; further see ¶¶ 64-65 if necessary);
a first conductive layer [shown in Gu Fig. 6] located at a side of the first active layer away from the base substrate, wherein the first conductive layer comprises a first conductive portion, a second gate line [Gate] and an enable signal line [EM], an orthographic projection of the second gate line on the base substrate extends along the row/X direction and covers an orthographic projection of the fourth active portion on the base substrate, a partial structure of the second gate line is used to form a gate of the fourth transistor [T4], an orthographic projection of the enable signal line on the base substrate extends along the row direction and covers an orthographic projection of the fifth active portion on the base substrate, and a partial structure of the enable signal line is used to form a gate of the fifth transistor [T5] (see Gu at least Fig. 4, 6; ¶ 62);
wherein in a same pixel driving circuit, an orthographic projection of the second gate line on the base substrate is located between an orthographic projection of the first conductive portion on the base substrate and the orthographic projection of the enable signal line [EM] on the base substrate (see at least Fig. 6; ¶ 62, 70.)
As per claim 22, the above modified Gu obviously renders: wherein the one of the pixel driving circuits (see Gu Fig. 1) further comprises a driving transistor [T3] and a first transistor [T1], a first electrode of the first transistor is connected to the first initialization signal line[Vinit1], and a second electrode of the first transistor is connected to a second electrode of the driving transistor (see Gu Fig. 1);
wherein the display panel further comprises:
a first active layer [shown in Gu Fig. 5] located at a side of the base substrate, wherein the first active layer comprises a third active portion and a first active portion, the third active portion is used to form a channel region of the driving transistor [T3], and the first active portion is used to form a channel region of the first transistor [T1] (see Gu at least Figs. 5, 11 and the corresponding description at least ¶ 61;)
wherein in a same pixel driving circuit, the first active portion and the third active portion are connected in a same layer (see Gu at least Fig. 5 and the corresponding description at least ¶ 61.)
In the alternative of claim 22, the above modified Gu obviously renders: wherein orthographic projections of two adjacent pixel driving circuits in a same pixel driving circuit row on the base substrate are at least partially arranged in mirror symmetry with respect to a second symmetry axis [Vinit2], and the second symmetry axis extends along the column direction (see at least Fig. 21.)
As per claim 24, the above modified Gu obviously renders: wherein the one of the pixel driving circuits (see Gu Fig. 1) further comprises:
a driving transistor [T3];
a first transistor [T1], wherein a first electrode of the first transistor [T1] is connected to a first initialization signal line [Vinit1], and a second electrode of the first transistor is connected to a second electrode of the driving transistor [T3] (see Gu Fig. 1);
a second transistor [T2], wherein a first electrode of the second transistor is connected to a gate of the driving transistor [T3], and a second electrode of the second transistor is connected to a second electrode of the driving transistor (see Gu Fig. 1);
a fourth transistor [T4], wherein a first electrode of the fourth transistor is connected to a data line [Da], and a second electrode of the fourth transistor is connected to a first electrode of the driving transistor (see Gu Fig. 1);
a fifth transistor [T5], wherein a first electrode of the fifth transistor is connected to the first power supply line, and a second electrode of the fifth transistor is connected to the first electrode of the driving transistor (see Gu Fig. 1);
a sixth transistor [T6], wherein a first electrode of the sixth transistor is connected to the second electrode of the driving transistor, and a second electrode of the sixth transistor is connected to a first electrode of the corresponding light-emitting unit [OLED] (see Gu Fig. 1);
a capacitor [C], wherein a first electrode of the capacitor is connected to the gate of the driving transistor, and a second electrode of the capacitor is connected to the first power supply line [VDD] (see Gu Fig. 1);
wherein the first transistor, the driving transistor, the fourth transistor, the fifth transistor, the sixth transistor, the seventh transistor see Fig. 1, disclosing all transistor being P-type transistors.)
Accordingly, the above modified Gu in view of Han obviously renders all limitations of this claim, but does not explicitly disclose an eighth transistor and the second transistor being N-type transistor, as claimed
Regarding to the eighth transistor, Official Notice is taken that both the concept and the advantages of providing an [[eighth]] transistor, wherein a first electrode of the eighth transistor is connected to an [[third]] initialization signal line, a second electrode of the [[eighth]] transistor is connected to the first electrode of the driving transistor, and the [[eighth]] transistor, in a pixel driving circuit in the display panel to obtain the gate-source difference being the same, and thus eliminating the threshold drift of the driving transistor by hysteresis are well-known and expected in the art. Therefore, it would have been obvious to a person of ordinary skill in the art before the effective filing date of invention of the pending application to include the [[eighth]] transistor in the Gu pixel driving circuit, as this [[eighth]] transistor to eliminate the threshold drift of the driving transistor by hysteresis.
Regarding to the second transistor being N-type transistor, Official Notice is taken that both the concept and the advantages of using the transistor being N-type transistor to improve the leakage current problem as the N-type transistor has a smaller turn-off leakage current as compared with the P-type transistor are well-known and expected in the art. Therefore, it would have been obvious to a person of ordinary skill in the art before the effective filing date of invention of the pending application to use the N-type transistor for the second transistor of Gu pixel circuit, as the N-type transistor has a smaller turn-off leakage current as compared with the P-type transistor, thereby improving the leakage current problem in the pixel circuit.
Accordingly, the above modified Gu obviously renders all limitations of this claim.
Note that before challenging the Office action on the eight transistor in this claim, the Applicant should review the Zhu reference (WO 2023/159503A; cited in the second set of rejections below), specifically the element [T9] in Fig. 4B with the benefit at ¶ 85.
As per claim 25, the above modified Gu obviously renders: the display panel further comprising:
an active layer [shown in Gu Fig. 5] located at a side of the base substrate, wherein at least a partial structure of the first active layer is used to form channel regions of the first transistor [T1], the second transistor [T2], the driving transistor [T3], the fourth transistor [T4], the fifth transistor [T5], the sixth transistor [T6], the seventh transistor [T7], and the eighth transistor [assumed T8, as modified in the rejection of claim 24] (see Gu Fig. 5; ¶ 61 “… a part of structure of the active layer is configured to form channel regions of the transistors in the pixel-driving circuit …”, thereby obviously rendering all channel regions of all transistors including the first through eighth transistors formed by the active layer);
a first conductive layer [shown in Gu Fig. 6] located at a side of the first active layer away from the base substrate, wherein at least a partial structure of the first conductive layer is used to form gates of the first transistor [T1], the second transistor [T2], the driving transistor [T3], the fourth transistor [T4], the fifth transistor [T5], the sixth transistor [T6], the seventh transistor [T7], and the eighth transistor [assumed T8, as modified in the rejection of claim 24] (see Gu at least Fig. 4, 6; ¶ 62, disclosing at least a partial structure of the first conductive layer used to form gates of all transistors including the first through eighth transistors);
a third conductive layer located at a side of the second active layer away from the base substrate
Accordingly, Gu teaches all limitations of this claim except that Gu teaches to use the active layer to form channel regions of the first transistor [T1], the second transistor [T2], the driving transistor [T3], the fourth transistor [T4], the fifth transistor [T5], the sixth transistor [T6], the seventh transistor [T7], and the eighth transistor, instead of to use two separate active layers, a first active layer forming the channel regions of the first transistor [T1], the driving transistor [T3], the fourth transistor [T4], the fifth transistor [T5], the sixth transistor [T6], the seventh transistor [T7], and the eighth transistor, and the second active layer to form the channel region of the second transistor [T2], as claimed. However, a modification which would have involved a mere change in the separation of one element into two or more elements was judicially recognized as being within the level of ordinary skill in the art, In Nerwin v. Erlichman, 168 USPQ 177, 179 (PTO Bd. of Int. 1969) and a mere change in location(s) of element(s) is generally recognized as being within the level of ordinary skill in the art, see In re Japikse, 86 USPQ 70 (CCPA 1950). Therefore, it would have been obvious to a person of ordinary skill in the art to separate the Gu active layer into the first and second active layers, as desired as claimed, since a such modification would have involved a mere change in the separation of one layer into two separate layers and a mere change in location(s) of element(s) is generally recognized as being within the level of ordinary skill in the art.
Further, Gu, discussed above, discloses the top gate of the second transistor formed in the first conductive layer, instead of the third conductive layer, as claimed. However, a modification which would have involved a mere change in location is generally recognized as being within the level of ordinary skill in the art, see In re Japikse, 86 USPQ 70 (CCPA 1950). Therefore, it would have been obvious to a person of ordinary skill in the art to locate the top gate of the second transistor in the third conductive layer, as desired as claimed, since a such modification would have involved a mere change in the locations of component(s) is generally recognized as being within the level of ordinary skill in the art. Therefore, it would have been obvious to a person of ordinary skill in this art to further modify the Gu reference to obtain the invention as specified in this claim.
SECOND SET OF REJECTIONS:
Note that since this application contains claims, which are similar to the claims of PCT application PCT/CN2023/132632, and the claims of the PCT application were examined by China National Intellectual Property Administration (ISA/CN), it is respectfully assumed that the examination by ISA/CN is proper, in order to respect the examination by ISA/CN. Therefore, this set of rejections is following the Written Opinion Form PCT/ISA/237 cited in the information disclosure statement (IDS) filed 09/19/2025.
Claims 1-4, 22 and 26 are rejected under 35 U.S.C. 103 as being unpatentable over Zhu (WO 2023/159503 A1; cited in IDS) in view of Wang et al. (CN 109860259 A; cited in IDS; hereinafter Wang.)
As per claims 1 and 26, in light of the Written Opinion Form PCT/ISA/237 cited in the IDS, Zhu (as D1 in the Written Opinion) discloses a display panel and a display device including the display panel. and discloses (paragraphs [0073]-[0106] of the specification, Figures 4a and 6): a substrate; a plurality of pixel circuits (i.e., pixel drive circuit LOW groups), as shown in Figure 6, having two adjacent LOWS of pixel circuits in the column direction, with a plurality of pixel circuits distributed in the row direction, the pixel circuits being used to drive the light-emitting units to emit light, as shown in Figure 1a, a seventh transistor I/ IS included, a first electrode of which is connected to a second initial signal line, a second electrode of which is connected to a first electrode of the light-emitting unit, and a gato formed by a partial structure of a second reset signal line, the orthographic projection of the second reset signal line on the substrate extending along a first direction, which is the row direction; a fifth transistor T5 having a first electrode connected to a first power supply line VDD, and a second electrode connected to a first electrode of a drive transistor T3; a first conductive portion 11 which can be used to form the gate of the drive transistor; an orthographic projection of an enable signal line on the substrate extending along the first direction, and a partial structure of the enable signal line being used to form the gate of the fifth transistor.
Claims 1 and 26 differ from Zhu in that: The orthographic projections of two adjacent pixel driving circuit rows in the same pixel driving circuit row group on the substrate are at least partially mirror-symmetrical about a first axis of symmetry, extending along the row direction; and the two adjacent pixel driving circuit rows in the same pixel driving circuit row group share the same second initial signal line. Based on this difference, the technical problem actually solved by Claims 1 and 26 is to improve integration and reduce the number of wiring and vias.
However, in the same field of endeavor, Wang (as D2 in the Written Opinion) discloses an OLED array substrate and discloses (paragraphs [0018]-[0019] of the specification): comprising a plurality of sub-pixels, wherein the driving circuits of two adjacent columns of sub-pixels adopt a mirror-symmetrical structure, providing space for improving PPI and facilitating the design of a high- PPI panel; the driving circuits of two sub-pixels in the same row of two adjacent columns of sub-pixels share a reset signal line and a first via (reset via), and the improved pixel structure layout can save about half of the reset signal line routing and vias, thereby providing space for improving PPI. Wang provides the inspiration for using mirror-symmetrical distribution of adjacent pixels to improve integration and sharing wiring to reduce wiring and vias. When Wang is applied to Zhu, the proper selection of the arrangement positions of mirror-symmetrical adjacent pixels, i.e., the proper selection of the axis of symmetry and the type of shared wiring, is a conventional approach in the art. Thus, it would have been obvious to one of ordinary skill in the art at the time before the effective filing date of invention of the pending application to apply the same aforementioned technique of providing the inspiration for using mirror-symmetrical distribution of adjacent pixels and sharing wiring, in the Zhu display panel, in view of the teaching in the Wang reference, to improve the above modified panel of the Zhu reference for the predictable result of improving integration and reducing the number of wiring and vias.
As per claims 2, 4, and 22, in light of the Written Opinion Form PCT/ISA/237, the additional technical features of these claims are conventional.
As per claim 3, in light of the Written Opinion Form PCT/ISA/237, some of the additional technical features of claim 3 are already disclosed in Zhu and the rest are conventional.
Claims 5-9, 11, 12, 14-16, 18 and 20 are rejected under 35 U.S.C. 103 as being unpatentable over Zhu in view of Wang, and further in view of Han et al. (WO 2022/204977 A1; cited in IDS; hereinafter Han.)
As per claims 5-9, 11, 12, 14-16, 18 and 20, in light of the Written Opinion Form PCT/ISA/237, Han (as D3 in the Written Opinion) discloses a display panel and discloses (paragraphs [0052]-[0080] of the specification, Figure 1): a seventh transistor T7, whose first electrode is connected to the second initial signal line, the second electrode is connected to the first electrode of the light emitting unit, and the gate is formed by a partial structure of the second reset signal line; the first conductive portion 11 can be used to form the gate of the driving transistor; the first electrode of the second transistor T2 is connected to the gate of the driving transistor T3, and the second electrode of the second transistor is connected to the second electrode of the driving transistor; the first electrode of the first transistor T1 is connected to the first initial signal line Vinit1, and the second electrode of the first transistor is connected to the second electrode of the driving transistor; it also includes a capacitor C, the first electrode of the capacitor IS connected to the gate of the driving transistor, and the second electrode of the capacitor is connected to the first power line VDD; the first electrode of the fourth transistor T4 is connected to the data line Da, and the second electrode of the fourth transistor is connected to the first electrode of the driving transistor. Accordingly, some of the additional technical features of these claims are already disclosed in Han and the rest are conventional.
Conclusion
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/Jimmy H Nguyen/
Primary Examiner, Art Unit 2626
