Prosecution Insights
Last updated: August 06, 2026
Application No. 19/116,217

MULTILAYERED COMMON MODE FILTER

Non-Final OA §102§112
Filed
Apr 01, 2025
Priority
Sep 27, 2022 — RE 10-2022-0122185 +1 more
Examiner
YALDO, ABIGAIL AMIR
Art Unit
2843
Tech Center
2800 — Semiconductors & Electrical Systems
Assignee
Amotech Co., Ltd.
OA Round
1 (Non-Final)
93%
Grant Probability
Favorable
1-2
OA Rounds
11m
Est. Remaining
99%
With Interview

Examiner Intelligence

Grants 93% — above average
93%
Career Allowance Rate
55 granted / 59 resolved
+25.2% vs TC avg
Strong +18% interview lift
Without
With
+18.2%
Interview Lift
resolved cases with interview
Typical timeline
2y 3m
Avg Prosecution
21 currently pending
Career history
75
Total Applications
across all art units

Statute-Specific Performance

§103
15.3%
-24.7% vs TC avg
§102
35.5%
-4.5% vs TC avg
§112
40.7%
+0.7% vs TC avg
Black line = Tech Center average estimate • Based on career data from 59 resolved cases

Office Action

§102 §112
DETAILED ACTION Notice of Pre-AIA or AIA Status The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA . Claim Rejections - 35 USC § 112 The following is a quotation of 35 U.S.C. 112(b): (b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention. The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph: The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention. Claims 1-18 are rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention. Claims 3-13 and 18 depend upon rejected claim 1 and inherit the deficiency thereby. Claim 1, Lines 4, 7 and 11, “a stacked body” is unclear to one of ordinary skill in the art as to whether this is referring to the “a stacked body”, as previously defined in Line 2 of claim 1, or a differing, new “stacked body” completely, thereby leaving the boundaries of the claim unclear. Claim 1, Lines 11-12, “a capacitor pattern” is unclear to one of ordinary skill in the art as to whether this is referring to the “a capacitor pattern”, as previously defined in Line 7 of claim 1, or a differing, new “capacitor pattern” completely, thereby leaving the boundaries of the claim unclear. Claim 1, Line 12, “a ground pattern” is unclear to one of ordinary skill in the art as to whether this is referring to the “a ground pattern”, as previously defined in Line 8 of claim 1, or a differing, new “ground pattern” completely, thereby leaving the boundaries of the claim unclear. Claim 1, Lines 13-14, “an additional capacitance” is unclear to one of ordinary skill in the art as to whether this is referring to the “an additional capacitance”, as previously defined in Line 9 of claim 1, or a differing, new “additional capacitance” completely, thereby leaving the boundaries of the claim unclear. Claim 2, Line 2; and Claim 14, Line 8, “an electrode stack” is unclear to one of ordinary skill in the art as to whether this limitation is in reference to the “stacked body” as defined in claim 1, from which this claim depends, or to a separate and differing “electrode stack”, thereby leaving the boundaries of the claim unclear. Claim 14, Lines 1-3, “the first capacitor layer and the second capacitor layer each comprise: a ninth sheet” is unclear to one of ordinary skill in the art as to what the “first capacitor layer” is in reference to and as to what numerical sheet designation this recitation is intended to reference, as the “first capacitor layer” and “second capacitor layer” have differing locations, as per claim 1 from which this claim depends, thereby leaving the boundaries of the claim unclear. Claim 14, Line 7, “a coil pattern” is unclear to one of ordinary skill in the art as to which of the first through sixth “coil patterns” as defined in claim 1, from which this claim depends, this “coil pattern” is referring to or whether to a differing, new “coil pattern” completely, thereby leaving the boundaries of the claim unclear. Claim 14, Line 9, “an additional capacitance” is unclear to one of ordinary skill in the art as to whether this is referring to the “an additional capacitance”, as previously defined in claim 1, from which this claim depends, or a differing, new “additional capacitance” completely, thereby leaving the boundaries of the claim unclear. Claim 15, Line 1, “the ground pattern” is unclear to one of ordinary skill in the art as to what “ground pattern” this recitation is in reference to, as defined in lines 8 and 12 of claim 1, from which this claim depends, thereby leaving the boundaries of the claim unclear. Claim 15, Lines 3-4, “a first surface of the ninth sheet” is unclear to one of ordinary skill in the art as to whether this is referring to the “a ninth sheet having a first surface”, as previously defined in Line 3 of claim 14 , or a differing, new “first surface” completely, thereby leaving the boundaries of the claim unclear. Claim 16, Line 1, “the capacitor pattern” is unclear to one of ordinary skill in the art as to what “capacitor pattern” this recitation is in reference to, as defined in lines 7 and 11-12 of claim 1, from which this claim depends, thereby leaving the boundaries of the claim unclear. Claim 17, Line 1, “the capacitor layer” is unclear to one of ordinary skill in the art whether this “capacitor layer” is referring to the “first capacitor layer” or “the second capacitor layer” as previously defined in claim 1 from which this claim depends, or defining a new, differing, “capacitor layer”, thereby leaving the boundaries of the claim unclear. Claim 17, Line 2, “a plurality of ground patterns” is unclear to one of ordinary skill in the art as to the relationship between “a plurality of ground patterns” and the previously recited “ground pattern” as defined in claims 1 and 14, from which this claim depends, thereby leaving the boundaries of the claim unclear. Claim 17, Line 2, “a plurality of capacitor patterns” is unclear to one of ordinary skill in the art as to the relationship between “a plurality of capacitor patterns” and the previously recited “capacitor pattern” as defined in claims 1 and 14, from which this claim depends, thereby leaving the boundaries of the claim unclear. Appropriate correction is required. Claim Rejections - 35 USC § 102 In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status. The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action: A person shall be entitled to a patent unless – (a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention. Claims 1, 3 and 14 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Taniguchi (US 8816796). As per Claim 1: Taniguchi discloses in Figure 18: A multilayered common mode filter (“multilayer filter”, 10F, as shown in related Figure 17) with a stacked upper electrode layer (“dielectric layers” 104T-107T, hereinafter referred to as U1) including a first (“coil electrode”, 501Fa), second (“coil electrode”, 601Fa), and third coil pattern (“coil electrode”, 701Fa), a stacked lower electrode layer (“dielectric layers” 109T-111T, hereinafter referred to as L1) including a fourth (“coil electrode”, 901Fa), fifth (“coil electrode”, 1001Fa), and sixth coil pattern (“coil electrode”, 1101Fa) on a bottom of the upper electrode layer (L1 is disposed below U1, as is evident by Figure 18), a stacked first capacitor layer (“dielectric layers” 101T and 102T, hereinafter referred to as C1) including a capacitor pattern (“plate electrode”, 201Fa, 201Fa and “dielectric layer” 102T constitute the first balanced-side capacitor, [Col. 28, Lines 50-52]) and a ground pattern (“GND” on “dielectric layer” 101T is inherently a ground pattern, as is known to one of ordinary skill in the art) on a top of the upper electrode layer (U1) and overlapping the first through sixth coil patterns to form an additional capacitance (C1 is located on the top of U1 and overlapping with 501Fa-1101Fa, as is evident by Figure 18 and by overlapping inherently forms an additional capacitance, as is known to one of ordinary skill in the art), and a stacked second capacitor layer (“dielectric layers” 112T and 113T, hereinafter referred to as C2) including a capacitor pattern (“plate electrode”, 1301Fa, 1301Fa and “dielectric layer” 113T constitute the second balanced-side capacitor, [Col. 33, Lines 10-12]) and a ground pattern (“plate electrode”, 1201Fc on “dielectric layer” 112T, 1201Fc is connected to the ground terminal and is inherently a ground pattern, [Col. 32, Lines 11-13]) on a bottom of the lower electrode layer (L1) and overlapping the first through sixth coil pattern to form an additional capacitance (C2 is located on the bottom of L1 and overlapping with 501Fa-1101Fa, as is evident by Figure 18 and by overlapping inherently forms an additional capacitance, as is known to one of ordinary skill in the art). As per Claims 3 and 14: Taniguchi discloses in Figure 18: The multilayer common mode filter (“multilayer filter”, 10F, as shown in related Figure 17) having the upper electrode layer (as per Claim 3, “dielectric layers” 104T-107T, U1) comprising a first sheet (“dielectric layer”, 104T) with a first surface (the top surface containing “plate electrodes” 401Fa and 401Fb) where a first (“first balanced terminal”, Pba1, Plate electrode 401Fa is connected to Pba1 “in the second lateral surface”, [Col. 28, Lines 45-49], therefore sheet 104T inherently contains the first balanced terminal Pba1) and second terminal pattern (“first balanced terminal”, Pbb1, Plate electrode 401Fb is connected to Pbb1 “in the second lateral surface”, [Col. 28, Lines 53-57], therefore sheet 104T also inherently contains the first balanced terminal Pbb1) are spaced apart from each other (as is evident by Figure 18), a second sheet (“dielectric layer”, 105T) on a bottom of the first sheet (105T is below 104T, as is evident by Figure 18) and having a first surface with the first coil pattern (the top surface containing “coil electrode”, 501Fa) and first via hole (“via electrode”, VH56a), a third sheet (“dielectric layer”, 106T) on a bottom of the second sheet (106T is below 105T, as is evident by Figure 18) and having a first surface with the second coil pattern (the top surface containing “coil electrode”, 601Fa), and a fourth sheet (“dielectric layer”, 107T) on a bottom of the third sheet (107T is below 106T, as is evident by Figure 18) having a first surface with the third coil pattern (the top surface containing “coil electrode”, 701Fa), and the first (as per Claim 14, “dielectric layers” 101T and 102T, C1) and second capacitor layer (“dielectric layers” 112T and 113T, C2) each comprise a ninth sheet (“dielectric layers”, 101T and 112T) on a bottom of the lower electrode layer (112T is below L1, as is evident by Figure 18) having a first surface with the ground pattern (the top surface containing “plate electrode”, 1201Fc and the side surface containing “GND”), a tenth sheet (“dielectric layers”, 102T and 113T) on a bottom of the ninth sheet (102T is on a bottom of 101T and 113T is on a bottom of 112T, as is evident by Figure 18) having a first surface with the capacitor pattern (the top surface containing the “plate electrode” 1301Fa and “dielectric layer” 113T which constitute the second balanced-side capacitor, [Col. 33, Lines 10-12], and the top surface containing the “plate electrode” 201Fa and “dielectric layer” 102T which constitute the first balanced-side capacitor, [Col. 28, Lines 50-52]), and the capacitor pattern (201Fa, 102T and 1301Fa, 113T) overlaps a coil pattern (“coil electrode”, 501Fa-1101Fa) included in an electrode stack in which the upper (U1) and lower electrode layer (L1) are stacked, to form an additional capacitance (201Fa, 102T and 1301Fa, 113T overlap with coil electrodes 501Fa-1101Fa, U1, and L1, as is evident by Figure 18 and by overlapping inherently form an additional capacitance, as is known to one of ordinary skill in the art). Conclusion Any inquiry concerning this communication or earlier communications from the examiner should be directed to ABIGAIL YALDO whose telephone number is (703)756-1784. The examiner can normally be reached Monday - Friday 7 AM - 4 PM. Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice. If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Andrea Lindgren Baltzell can be reached at (571) 272-5918. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300. Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000. /ABIGAIL AMIR YALDO/ Examiner, Art Unit 2843 /ANDREA LINDGREN BALTZELL/ Supervisory Patent Examiner, Art Unit 2843
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Prosecution Timeline

Apr 01, 2025
Application Filed
Jun 23, 2026
Non-Final Rejection mailed — §102, §112 (current)

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Study what changed to get past this examiner. Based on 5 most recent grants.

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Prosecution Projections

1-2
Expected OA Rounds
93%
Grant Probability
99%
With Interview (+18.2%)
2y 3m (~11m remaining)
Median Time to Grant
Low
PTA Risk
Based on 59 resolved cases by this examiner. Grant probability derived from career allowance rate.

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