Prosecution Insights
Last updated: October 26, 2026
Application No. 19/116,791

MEMORY DATA MIGRATION METHOD AND APPARATUS, ELECTRONIC DEVICE, AND STORAGE MEDIUM

Non-Final OA §102§103§112
Filed
Mar 28, 2025
Priority
Aug 04, 2023 — CN 202310975510.X +1 more
Examiner
WONG, NANCI N
Art Unit
2137
Tech Center
2100 — Computer Architecture & Software
Assignee
Suzhou Metabrain Intelligent Technology Co., Ltd.
OA Round
1 (Non-Final)
87%
Grant Probability
Favorable
1-2
OA Rounds
11m
Est. Remaining
99%
With Interview

Examiner Intelligence

Grants 87% — above average
87%
Career Allowance Rate
410 granted / 470 resolved
+32.2% vs TC avg
Strong +22% interview lift
Without
With
+22.5%
Interview Lift
resolved cases with interview
Typical timeline
2y 6m
Avg Prosecution
15 currently pending
Career history
500
Total Applications
across all art units

Statute-Specific Performance

§101
5.1%
-34.9% vs TC avg
§103
70.1%
+30.1% vs TC avg
§102
5.1%
-34.9% vs TC avg
§112
14.6%
-25.4% vs TC avg
Black line = Tech Center average estimate • Based on career data from 470 resolved cases

Office Action

§102 §103 §112
DETAILED ACTION Notice of Pre-AIA or AIA Status The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA . The present Office Action is in response to amended claims filed on 03/28/2025. Claims 15, 18, 21 and 22 have been amended. Claims 19-20 have been cancelled. Claims 1-18 and 21-22 are pending in the application. Priority Acknowledgment is made of applicant’s claim for foreign priority under 35 U.S.C. 119 (a)-(d). The certified copy has been filed in parent Application No.CN202310975510.X, filed on 08/04/2023. Claim Objections Claims 1, 21, and 22 are objected to because of the following informalities: Data migration in the art generally refers to copying data from one location and store the copied data to another location. However, claim 1, for example, recites “migrating the target memory page to the idle page”. Thus, the recitation is technically imprecise because it is unclear whether the claim requires migration of the data stored in the target memory page or remapping of the memory page itself. Claims 21 and 22 are objected for the similar reason. Appropriate correction is required. Claim Rejections - 35 USC § 112 The following is a quotation of 35 U.S.C. 112(b): (b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention. The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph: The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention. Claim 3 is rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention. Regarding claim 3, the limitation recite “the second memory node being not overwritten” is ambiguous. It is unclear what it meant by a memory node being not overwritten. The limitation can be interpreted as 1) no data on the second memory node has ever been overwritten – all original data, 2) a target page on the second memory node is free – not being written, 3) the second node is not having any write operation being performed at the moment – not busy, or 4) a target page on the second memory node is not being overwritten at the moment. For examination purpose, the Examiner has interpreted claim 3 as outlined in 2). Claim Rejections - 35 USC § 102 In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status. (a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention. Claim(s) 1,5, 9-12, and 21-22 is/are rejected under 35 U.S.C. 102(a)(2) as being anticipated by Zhu et al. (US2024/0231669), hereinafter Zhu. Regarding claims 1, 21, and 22, taking claim 1 as exemplary, Zhu teaches a memory data migration method, applied to a hierarchical memory system, wherein the hierarchical memory system comprises a plurality of memory nodes corresponding to different hierarchies (Zhu, [0074]; [0091]), and the method comprises: determining a target memory page to be migrated to a target memory node (Zhu, [0093], data of all hot pages is migrated to a free page of the DRAM; [0103]); determining an idle page in the target memory node (DRAM), and migrating the target memory page to the idle page (Zhu, [0093], data of all hot pages is migrated to a free page of the DRAM); and when it is detected that the number of remaining idle pages (free pages) in the target memory node is less than a preset threshold, continuously migrating an inactive memory page (cold page) in the target memory node to other memory nodes with a hierarchy lower than the target memory node until it is determined that the number of the idle pages is not less than the preset threshold (Zhu, [0096], when the quantity of free pages in the memory medium of DRAM type is less than or equal to the quantity of hot pages in the memory medium of an SCM type, data of all cold pages is migrated to a free page of the SCM). Claims 21 and 22 have similar limitations as claim 1 and they are rejected for the similar reasons. Regarding claim 5, Zhu teaches all the features with respect to claim 1 as outlined above. Zhu further teaches the memory data migration method according to claim 1, wherein migrating the inactive memory page in the target memory node to other memory nodes with the hierarchy lower than the target memory node comprises: acquiring a preset corresponding relationship between an inactivity degree of a memory page and a hierarchy of a memory node (Zhu, [0070]; [0079]; [0081]); and migrating, according to the preset corresponding relationship and the inactivity degree of the inactive memory page, the inactive memory page to other memory nodes of corresponding hierarchies (Zhu, [0084]; [0088]; [0096]). Regarding claim 9, Zhu teaches all the features with respect to claim 1 as outlined above. Zhu further teaches the memory data migration method according to claim 1, wherein before determining the target memory page to be migrated to a target memory node, the memory data migration method further comprises: setting, according to a target central processing unit where an application program thread is located and an association relationship between the target central processing unit and the memory nodes, hierarchies corresponding to the memory nodes (Zhu, [0069]; [0072]; [0074]). Regarding claim 10, Zhu teaches all the features with respect to claim 9 as outlined above. Zhu further teaches the method memory data migration method according to claim 9, wherein setting, according to the target central processing unit where an application program thread is located and the association relationship between the target central processing unit and the memory nodes, hierarchies corresponding to the memory nodes comprises: setting, according to the target central processing unit where the application program thread is located and a mounting relationship between the target central processing unit and the memory nodes, the hierarchies corresponding to the memory nodes (Zhu, [0074]; Fig.3; Fig.4). Regarding claim 11, Zhu teaches all the features with respect to claim 9 as outlined above. Zhu further teaches the memory data migration method according to claim 9, wherein setting, according to the target central processing unit where the application program thread is located and the association relationship between the target central processing unit and the memory nodes, hierarchies corresponding to the memory nodes comprises: setting, according to the target central processing unit where the application program thread is located and a speed of the target central processing unit to read and write the memory nodes, the hierarchies corresponding to the memory nodes (Zhu, [0069], latency; [0071]; [0072]). Regarding claim 12, Zhu teaches all the features with respect to claim 9 as outlined above. Zhu further teaches the method memory data migration method according to claim 9, wherein after setting the hierarchies corresponding to the memory nodes, the memory data migration method further comprises: setting a memory node with a highest hierarchy as the target memory node (Zhu, [0022]; [0071], a latency of the DRAM is lower than a latency of the SCM; [0091], a memory medium of a DRAM type belongs to a first level). Claim Rejections - 35 USC § 103 In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status. The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action: A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made. Claim(s) 2 is/are rejected under 35 U.S.C. 103 as being unpatentable over Zhu as applied to claim 1 above, and further in view of Kim et al. (US2017/0371777), hereinafter Kim. Regarding claim 2, Zhu teaches all the features with respect to claim 1 as outlined above. Zhu does not explicitly teach the memory data migration method according to claim 1, wherein continuously migrating the inactive memory page in the target memory node to other memory nodes with the hierarchy lower than the target memory node comprises: determining a first memory node with a slowest local access speed and a second memory node with a slowest remote access speed from the other memory nodes; and continuously migrating the inactive memory page in the target memory node to the first memory node or the second memory node, as claimed. However, Zhu in view of Kim teaches the memory data migration method according to claim 1, wherein continuously migrating the inactive memory page in the target memory node to other memory nodes with the hierarchy lower than the target memory node comprises: determining a first memory node with a slowest local access speed and a second memory node with a slowest remote access speed from the other memory nodes; and continuously migrating the inactive memory page in the target memory node to the first memory node or the second memory node (Kim, [0016]; [0022]; [0025]; Zhu, [0096]). It would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention to have modified Zhu to incorporate teachings of Kim to include a first memory node with a slowest local access speed and a second memory node with a slowest remote access speed from other memory node. A person of ordinary skill in the art would have been motivated to combine the teachings of Zhu with Kim because it improves efficiency of the storage system disclosed in Zhu by collecting access latency metrics on memory nodes in order to allow the storage system to select appropriate source/destination node for data migration. Claim(s) 3 is/are rejected under 35 U.S.C. 103 as being unpatentable over the combination of Zhu and Kim as applied to claim 2 above, and further in view of Klein et al. (US2018/0262567), hereinafter Klein. Regarding claim 3, the combination of Zhu teaches all the features with respect to claim 2 as outlined above. The combination of Zhu does not explicitly teach the memory data migration method according to claim 2, wherein continuously migrating the inactive memory page in the target memory node to the first memory node or the second memory node comprises: determining a target inactive memory page to be migrated currently, and determining whether the second memory node is overwritten; migrating, in response to the second memory node being not overwritten, the target inactive memory page to the second memory node; determining, in response to the second memory node being overwritten, whether the first memory node is overwritten; migrating, in response to the first memory node being not overwritten, the target inactive memory page to the first memory node; and proceeding to, in response to the first memory node being overwritten, the step of determining whether the second memory node is overwritten, as claimed. However, the combination of Zhu in view of Klien teaches the memory data migration method according to claim 2, wherein continuously migrating the inactive memory page in the target memory node to the first memory node or the second memory node comprises: determining a target inactive memory page to be migrated currently, and determining whether the second memory node is overwritten; migrating, in response to the second memory node being not overwritten, the target inactive memory page to the second memory node; determining, in response to the second memory node being overwritten, whether the first memory node is overwritten; migrating, in response to the first memory node being not overwritten, the target inactive memory page to the first memory node; and proceeding to, in response to the first memory node being overwritten, the step of determining whether the second memory node is overwritten (Klein, [0055], If the identified pages are not sufficient to satisfy the allocation request, the method steps proceed to step 611 and metadata server 351 identifies free blocks with the smallest erase count on free block list 531 (e.g., free block 509 identified by “PTR1”) of different devices or different nodes). It would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention to have modified the combination of Zhu to incorporate teachings of Klein to select a page from either a first node or a second node based on whether the page satisfies allocation policies as a destination page for a migration operation. A person of ordinary skill in the art would have been motivated to combine the teachings of the combination of Zhu with Klein because it improves efficiency and integrity of the storage system disclosed in the combination of Zhu by selecting appropriate memory pages as data migration destination. Claim(s) 4 is/are rejected under 35 U.S.C. 103 as being unpatentable over the combination of Zhu and Kim as applied to claim 2 above, and further in view of Wu et al. (US2024/0303195), hereinafter Wu. Regarding claim 4, the combination of Zhu teaches all the features with respect to claim 2 as outlined above. The combination of Zhu does not explicitly teach the memory data migration method according to claim 2, wherein migrating the inactive memory page in the target memory node to the second memory node comprises: migrating, on the basis of an ultra path interconnect protocol, the inactive memory page in the target memory node to the second memory node, as claimed. However, the combination of Zhu in view of Wu teaches the memory data migration method according to claim 2, wherein migrating the inactive memory page in the target memory node to the second memory node comprises: migrating, on the basis of an ultra path interconnect protocol, the inactive memory page in the target memory node to the second memory node (Wu, [0020], Hardware-based approaches are typically implemented in the interconnection technologies of computer processors (e.g., … and Ultra Path Interconnect (UPI); [0078]-[0090; Fig.5). It would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention to have modified the combination of Zhu to incorporate teachings of Wu to migrate data to a node with the slowest remote access based on Ultra Path Interconnect (UPI). A person of ordinary skill in the art would have been motivated to combine the teachings of the combination of Zhu with Wu because it improves availability of the storage system disclosed in the combination of Zhu by providing data from a different NUMA node if data is unavailable at a home node. Claim(s) 6 and 7 is/are rejected under 35 U.S.C. 103 as being unpatentable over Zhu as applied to claim 1 above, and further in view of Shin et al. (US2025/0021227), hereinafter Shin. Regarding claim 6, Zhu teaches all the features with respect to claim 1 as outlined above. Zhu further teaches the memory data migration method according to claim 1, wherein continuously migrating the inactive memory page in the target memory node to other memory nodes with the hierarchy lower than the target memory node comprises: setting a memory page with a least access amount within a recent preset time period as the inactive memory page (Zhu, [0079]; [0084]); migrating the inactive memory page to the other memory nodes, and updating the number of the idle pages (Zhu, [0096]; [0104]; [0114]); and when it is determined that the updated number of the idle pages is less than the preset threshold, proceeding to the step of setting a memory page with a least access amount within a recent preset time period as the inactive memory page (Zhu, [0104]). Zhu teaches setting a memory page whose quantity of times of access is less than a threshold, nevertheless, Zhu does not explicitly teach setting a memory page with a least access amount within a recent preset time period as the inactive memory page, as claimed. However, Zhu in view of Shin teaches setting a memory page with a least access amount within a recent preset time period as the inactive memory page (Shin, [0144], A page with the lowest access frequency (e.g., a cold page) ). It would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention to have modified Zhu to incorporate teachings of Shin to identify a code page as a memory page with the lowest access frequency. A person of ordinary skill in the art would have been motivated to combine the teachings of Zhu with Shin because it improves efficiency of the storage system disclosed in Zhu by migrating the coldest page to a lower performance storage medium first. Regarding claim 7, the combination of Zhu teaches all the features with respect to claim 6 as outlined above. The combination of Zhu further teaches the memory data migration method according to claim 6, wherein setting the memory page with the least access amount within the recent preset time period as the inactive memory page comprises: setting, using an inactive least recently used linked list, the memory page with the least access amount within the recent preset time period as the inactive memory page (Zhu, [0079], The other LRU linked list is used to record an inactive list, and the inactive list includes information about a memory page on which cold data in the memory medium is located). Claim(s) 8 is/are rejected under 35 U.S.C. 103 as being unpatentable over the combination of Zhu and Shin as applied to claim 7 above, and further in view of Gupta et al. (US2021/0224199), hereinafter Gupta and Han et al. (US2024/0054079), hereinafter Han. Regarding claim 8, the combination of Zhu teaches all the features with respect to claim 7 as outlined above. The combination of Zhu does not explicitly teach the memory data migration method according to claim 7, wherein setting, using the inactive least recently used linked list, the memory page with the least access amount within the recent preset time period as the inactive memory page comprises: when it is determined that an inactive file page least recently used linked list is not empty, setting a memory page at a tail of the inactive file page least recently used linked list as the inactive memory page; and when it is determined that the inactive file page least recently used linked list is empty, setting a memory page at a tail of an inactive anonymous page least recently used linked list as the inactive memory page, as claimed. However, the combination of Zhu in view of Gupta teaches the memory data migration method according to claim 7, wherein setting, using the inactive least recently used linked list, the memory page with the least access amount within the recent preset time period as the inactive memory page comprises: when it is determined that an inactive file page least recently used linked list is not empty, setting a memory page at a tail of the inactive file page least recently used linked list as the inactive memory page; and when it is determined that the inactive file page least recently used linked list is empty, setting a memory page at a tail of an inactive anonymous page least recently used linked list as the inactive memory page (Gupta, claim 1). It would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention to have modified the combination of Zhu to incorporate teachings of Gupta to select a page from the tail of a favored LRU list if the favored LRU list is not empty, otherwise, select a page from a non-favored LRU list. A person of ordinary skill in the art would have been motivated to combine the teachings of the combination of Zhu with Gupta because it improves efficiency of the storage system disclosed in the combination of Zhu by providing a backup LRU list for the storage system to select/obtain a page. The combination of Zhu does not explicitly teach a file page LRU list and an anonymous page LRU list, as claimed. However, the combination of Zhu in view of Han teaches when it is determined that an inactive file page least recently used linked list is not empty, setting a memory page at a tail of the inactive file page least recently used linked list as the inactive memory page; and when it is determined that the inactive file page least recently used linked list is empty, setting a memory page at a tail of an inactive anonymous page least recently used linked list as the inactive memory page (Han, [0005]; [0406], an anonymous page obtained by the application through application is added to an LRU linked list … and a file page obtained by the application through application is added to a global LRU linked list; Gupta, [0058]-[0060]; Fig.6). It would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention to have modified the combination of Zhu to incorporate teachings of Han to create a first LRU list of file pages and a second LRU list of anonymous pages. As such, a page can be selected/obtained from the LRU list of file pages if the file page LRU list is not empty, otherwise, a page can be selected/obtained from the LRU list of anonymous pages. A person of ordinary skill in the art would have been motivated to combine the teachings of the combination of Zhu with Han because it improves efficiency of the storage system disclosed in the combination of Zhu by providing a backup LRU list for the storage system to select/obtain a page. Claim(s) 13 and 14 is/are rejected under 35 U.S.C. 103 as being unpatentable over Zhu as applied to claim 9 above, and further in view of Wu et al. (US2024/0303195), hereinafter Wu. Regarding claim 13, Zhu teaches all the features with respect to claim 9 as outlined above. Zhu does not explicitly teach the memory data migration method according to claim 9, wherein determining the target memory page to be migrated to the target memory node comprises: when it is determined that a memory page requested to be accessed by the application program thread is not saved in the target memory node, setting the memory page requested to be accessed by the application program thread as the target memory page, as claimed. However, Zhu in view of Wu teaches the memory data migration method according to claim 9, wherein determining the target memory page to be migrated to the target memory node comprises: when it is determined that a memory page requested to be accessed by the application program thread is not saved in the target memory node, setting the memory page requested to be accessed by the application program thread as the target memory page (Wu, [0080]; [0082]; Fig.5). It would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention to have modified Zhu to incorporate teachings of Wu to determine if a requested page is located in a NUMA node, and if the page is not found/saved in the node, then a page with requested data is to be transmitted to the node. A person of ordinary skill in the art would have been motivated to combine the teachings of Zhu with Wu because it improves availability of the storage system disclosed in Zhu by providing requested data from a different NUMA node if the requested data is unavailable at a home node. Regarding claim 14, Zhu teaches all the features with respect to claim 12 as outlined above. Zhu does not explicitly teach the method memory data migration method according to claim 12, after migrating the target memory page to the idle page, the memory data migration method further comprises: returning data in the target memory page to the application program thread, as claimed. However, Zhu in view of Wu teaches the method memory data migration method according to claim 12, after migrating the target memory page to the idle page, the memory data migration method further comprises: returning data in the target memory page to the application program thread (Wu, [0089]; [0092]; Fig.5). It would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention to have modified Zhu to incorporate teachings of Wu to determine if a requested page is located in a NUMA node, and if the page is not found/saved in the node, then a page with requested data is to be transmitted to the node. A person of ordinary skill in the art would have been motivated to combine the teachings of Zhu with Wu because it improves availability of the storage system disclosed in Zhu by providing data from a different NUMA node if data is unavailable at a home node. Claim(s) 15 and 16 is/are rejected under 35 U.S.C. 103 as being unpatentable over Zhu as applied to claim 1 above, and further in view of Gim et al. (US2023/0342045), hereinafter Gim. Regarding claim 15, Zhu teaches all the features with respect to claim 1 as outlined above. Zhu further teaches the memory data migration method according to claim 1, wherein a storage space of the target memory node comprises a general space (Zhu, [0084], migration data set) and a reserved space (Zhu, [0077], memory pool), wherein the general space is maintained by an automatic non-uniform memory access framework (Zhu, [0085], the scheduler 4311 may periodically send a scanning request to the kernel of the operating system running on the processor, to obtain a more accurate result that reflects a cold and hot degree of the memory medium;); and determining the idle page in the target memory node, and migrating the target memory page to the idle page comprises: migrating, using the automatic non-uniform memory access framework, the target memory page to the general space (Zhu, [0093]; [0107]-[0110]), and determining whether the automatic non-uniform memory access framework outputs page fault information; and determining, in response to the automatic non-uniform memory access framework having output the page fault information, an idle page in the reserved space, and migrating the target memory page to the idle page in the reserved space; and accordingly, when it is detected that the number of remaining idle pages in the target memory node is less than a preset threshold, continuously migrating an inactive memory page in the target memory node to other memory nodes with a hierarchy lower than the target memory node until it is determined that the number of the idle pages is not less than the preset threshold comprises: when it is detected that the number of remaining idle pages in the reserved space is less than the preset threshold, continuously migrating the inactive memory page in the target memory node to the other memory nodes with the hierarchy lower than the target memory node (Zhu, [0096]), and replenishing a reclaimed idle page to the reserved space until it is determined that the number of the idle pages in the reserved space is not less than the preset threshold (Note – when cold data is migrated to a SCM, the cold pages of DRAM are freed). Zhu does not explicitly teach determining whether the automatic non-uniform memory access framework outputs page fault information; and determining, in response to the automatic non-uniform memory access framework having output the page fault information, an idle page in the reserved space, and migrating the target memory page to the idle page in the reserved space, as claimed. However, Zhu in view of Gim teaches determining whether the automatic non-uniform memory access framework outputs page fault information (Gim, [0037], A NUMA balancing scan 302 may be performed (e.g., automatically) … The NUMA balancing scan 302 may mark the individual pages such as page 308 for a page fault); and determining, in response to the automatic non-uniform memory access framework having output the page fault information, an idle page in the reserved space, and migrating the target memory page to the idle page in the reserved space (Gim, [0037], Upon detection of a page fault in page 308, a sync migration 310 may transfer content of page 308 on the second-tier of memory 306 to page 312 on the first-tier of memory 304.) It would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention to have modified Zhu to incorporate teachings of Gim to detect page fault in memory pages and migrate data from the page having the page fault to a free page. A person of ordinary skill in the art would have been motivated to combine the teachings of Zhu with Gim because it improves efficiency of the storage system disclosed in Zhu by migrating data from a page having page fault to maintain data integrity. Regarding claim 16, the combination of Zhu teaches all the features with respect to claim 15 as outlined above. The combination of Zhu further teaches the memory data migration method according to claim 15, wherein migrating the target memory page to the idle page in the reserved space comprises: determining, according to the page fault information, a location of the target memory page; and migrating, according to the location, the target memory page to the idle page in the reserved space (Gim, [0037], The NUMA balancing scan 302 may mark the individual pages such as page 308 for a page fault; Fig. 3). It would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention to have modified the combination of Zhu to incorporate teachings of Gim to detect page fault in memory pages and migrate data from the page having the page fault to a free page. A person of ordinary skill in the art would have been motivated to combine the teachings of Zhu with Gim because it improves efficiency of the storage system disclosed in Zhu by migrating data from a page having page fault to maintain data integrity. Claim(s) 17 and 18 is/are rejected under 35 U.S.C. 103 as being unpatentable over the combination of Zhu and Gim as applied to claim 15 above, and further in view of Kuehne (US2011/0055458), hereinafter Kuehne. Regarding claim 17, the combination of Zhu teaches all the features with respect to claim 15 as outlined above. The combination of Zhu further teaches the memory data migration method according to claim 15, wherein determining the idle page in the reserved space, and migrating the target memory page to the idle page in the reserved space comprises: determining, using a first preset thread, the idle page in the reserved space, and migrating the target memory page to the idle page in the reserved space (Zhu, [0096]); and accordingly, continuously migrating the inactive memory page in the target memory node to the other memory nodes with the hierarchy lower than the target memory node, and replenishing a reclaimed idle page to the reserved space comprises: continuously migrating, using a second preset thread, the inactive memory page in the target memory node to the other memory nodes, and replenishing the reclaimed idle page to the reserved space. The combination of Zhu does not explicitly teach continuously migrating, using a second preset thread, as claimed. However, the combination of Zhu in view of Kuehne teaches continuously migrating, using a second preset thread, the inactive memory page in the target memory node to the other memory nodes, and replenishing the reclaimed idle page to the reserved space (Kuehne, [0065], If the number of free page buffers 350 becomes too low, there is a message to the eviction thread to start running and generating new free page buffers 350; [0119]). It would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention to have modified the combination of Zhu to incorporate teachings of Kuehne include a second thread which can be activated if the number of free pages is too low. A person of ordinary skill in the art would have been motivated to combine the combination of Zhu with Kuehne because it improves efficiency of the storage system disclosed in the combination of Zhu by deactivating one or more threads when they are not required which saves resources (Kuehne, [0117]). Regarding claim 18, the combination of Zhu teaches all the features with respect to claim 17 as outlined above. The combination of Zhu further teaches the memory data migration method according to claim 17, further comprising: when the first preset thread determines that the number of the remaining idle pages in the reserved space is less than the preset threshold, waking up, using the first preset thread, the second preset thread; further comprising: when it is determined that the number of the idle pages in the reserved space is not less than the preset threshold, hibernating the second preset thread (Kuehne, [0107]; [0119]; [0126]). It would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention to have modified the combination of Zhu to incorporate teachings of Kuehne to include a second thread which can be activated if the number of free pages is too low. A person of ordinary skill in the art would have been motivated to combine the combination of Zhu with Kuehne because it improves efficiency of the storage system disclosed in the combination of Zhu by deactivating one or more threads when they are not required which saves resources (Kuehne, [0117]). Conclusion The prior art made of record and not relied upon is considered pertinent to applicant's disclosure. Prohofsky (US10,176,212) teaches migrating data to different memory medium based on access frequency (i.e. hot data or cold data). Any inquiry concerning this communication or earlier communications from the examiner should be directed to NANCI N WONG whose telephone number is (571)272-4117. The examiner can normally be reached Monday-Friday 9am -6pm. Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice. If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Arpan Savla can be reached at 571-272-1077. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300. Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000. /NANCI N WONG/Primary Examiner, Art Unit 2137
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Prosecution Timeline

Mar 28, 2025
Application Filed
Sep 02, 2026
Non-Final Rejection mailed — §102, §103, §112 (current)

Precedent Cases

Applications granted by this same examiner with similar technology

Patent 12762048
PREDICTIVE CENTER ALLOCATION DATA STRUCTURE
2y 7m to grant Granted Oct 13, 2026
Patent 12754682
SYSTEMS AND METHODS FOR ADAPTIVE DATA PARTITIONING WITHIN CLUSTER SYSTEMS
2y 0m to grant Granted Oct 06, 2026
Patent 12710883
STORAGE DEVICE FOR REDUCING RELIABILITY DEGRADATION OF OS DATA THROUGH STAGE CHANGE BEFORE SMT PROCESS AND METHOD FOR OPERATING THE SAME
3y 0m to grant Granted Aug 18, 2026
Patent 12711057
SOLVING SUBMISSION QUEUE ENTRY OVERFLOW USING METADATA OR DATA POINTERS
3y 0m to grant Granted Aug 18, 2026
Patent 12711078
DOWNGRADING A PERMISSION ASSOCIATED WITH DATA STORED IN A CACHE
1y 8m to grant Granted Aug 18, 2026
Study what changed to get past this examiner. Based on 5 most recent grants.

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Prosecution Projections

1-2
Expected OA Rounds
87%
Grant Probability
99%
With Interview (+22.5%)
2y 6m (~11m remaining)
Median Time to Grant
Low
PTA Risk
Based on 470 resolved cases by this examiner. Grant probability derived from career allowance rate.

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