DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Interpretation
Claim(s) 1-20 do not use “means for “(or “step for”) language, or generic placeholders for “means” coupled with functional language without recitation of sufficient structure for carrying out the claimed functions and therefore do not invoke 35 U.S.C. 112(f) (pre-AIA 35 U.S.C. 112, sixth paragraph).
Claim Rejections - 35 USC § 112
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claim 5 is rejected under 35 U.S.C. 112(b) or 35 U.S.C. (pre-AIA ), second paragraph, as being indefinite for failing to particularly pint out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention.
[Claim 5]
Regarding claim 5, claim recites “each of the normal accumulation period and the virtual light-shielding accumulation period includes a timing of reading the charge accumulated in the photoelectric conversion unit with a different conversion efficiency.” Claim 5 fails to clearly state what the conversion efficiency is different from a specific value. It only mentioned different conversion efficiency. Based on the specification (page 32, paragraphs 0073-0074) the efficiency appears to be selected as low-efficiency or high-efficiency. Hence, for further prosecution, the different efficiency will be considered as either a low-efficiency which is different from a high-efficiency or a high-efficiency which is different from a low-efficiency.
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
Claim(s) 1-3, 7-9, 12 and 14 are rejected under 35 U.S.C. 102(a)(1) or 102(a)(2) as being anticipated by Mabuchi, Keiji (US-2022/0141406-A1).
[Claim 1]
Regarding claim 1, Mabuchi teaches an imaging device (Mabuchi, Figure 1, an imaging system 100) comprising:
a pixel (Mabuchi, Figure 1 , a pixel array 102 including unit image sensor pixel 103) provided with a lateral overflow integration capacitor (Mabuchi, Figure 2, a lateral overflow integration capacitor (LOFIC) 215,), accumulates charge overflowing from a photoelectric conversion unit (Mabuchi, further teaches in response to high intensity illumination, a photodiode PD 211 may generate more charge than the floating diffusion FD1 213 can store. The extra charges (overflow charges) may be stored by the LOFIC 215, paragraph 0034) ; and
a signal processing unit (Mabuchi, in Figure 5, includes a processor 410) that performs correction processing of a pixel signal read from the pixel (Mabuchi, further teaches The processor 410 may be further configured to subtract the dark current level associated with each pixel from the signal level of each corresponding pixel in an image frame captured after the capture of DC frame yield image frame without contribution of dark current associated with floating diffusion regions, paragraph 0039) on a basis of a virtual light-shielding signal read from the lateral overflow integration capacitor in a state where the charge photoelectrically converted by the photoelectric conversion unit is not accumulated in the lateral overflow integration capacitor (Mabuchi teaches an estimate of a dark current (DC) pixel frame may be obtained by acquiring the value of dark current in the pixels of an entire pixel frame, separate from acquiring signal values of the pixels in the frame. This DC frame may then be used as a representative of the intensity of the dark current for the subsequently-acquired frames for as long as the conditions that determine intensity of the dark current remain reasonably unchanged (e.g., relatively short time has elapsed, no significant temperature differences from frame to frame, etc.). The pixel values from the DC frame may be subtracted from the corresponding pixel signal values of the normal frames to account for the dark current. This subtraction may also be referred to as calibration or adjustment. In some embodiments, the DC frame may be every Nth frame in a sequence of frames in a video stream. In other embodiments, new DC frame may be taken at a predetermined change of temperature or after a predetermined time, paragraph 0023, Figure 6).
[Claim 2]
Regarding claim 2, Mabuchi teaches all the limitations of claim 1, further comprising a flow control unit (Mabuchi, Figure 3A, overflow OF transistor 230) that discharges the charge generated by the photodiode PD 211, during exposure period as shown in Figure 3B timing diagram when the OF is turned on. During acquisition of a DC frame, the OF is turned on (e.g., an overflow control signal with high signal level is applied to the gate of the overflow transistor 230), therefore draining the photogenerated charges (i.e. charge photoelectrically converted by the photoelectric conversion unit) at the PD 211 to the AVDD voltage, so as to disable the PD 211 and to limit the charge accumulation at the FD1 and FD2 to correspond to dark current only or at least to dark current predominantly, paragraph 0037. During this time the charges generated by the photoelectric conversion unit is not stored in the lateral overflow integration capacitor (i.e. LOFIC 215 in Figure 3A).
[Claim 3]
Regarding claim 3, Mabuchi teaches all the limitations of claim 1, , further comprising:
a normal accumulation period in which charge is accumulated in the photoelectric conversion unit in a state where the charge accumulated in the photoelectric conversion unit can overflow to the lateral overflow integration capacitor, (Mabuchi in Figure 3A and 3B teaches a lateral overflow integration capacitor LOFIC 215 coupled to the first floating diffusion node FD1 via a dual floating diffusion (DFD) transistor 216. Mabuchi further teaches that the combination of FD1 213 and FDC 219 may also be collectively referred to as a floating diffusion, paragraph 0031. Therefore, during a normal accumulation period, as depicted in the timing diagram 3B during the period when OF is low, and exposure mode, the charges photoelectrically converted by the photodiode PD211, are accumulated in the floating diffusion node FD1 and FD2. Mabuchi further teaches In operation, the TX transistor 212 receives gate signal to enable charge transfer from the PD 211 to the floating diffusion FD1 213. In general, the amount of charge transfer depends on the light exposure of the PD 211 and operation of the pixel 203, paragraph 0033); and
a virtual light-shielding accumulation period (Mabuchi, in Figure 6, teaches a flow chart of a method for dark current frame subtraction in accordance with an embodiment of the present disclosure. FIG. 6 may be a flow chart illustrating dark current calibration method for an image sensor with LOFIC pixels as illustrated in FIG. 3. In different embodiments, the method may include additional steps or may omit some steps illustrated in the flow chart. The method starts in block 605. In block 610, an image frame is designated as a DC frame to represent charges accumulated at the floating diffusions of each pixel in absence of light, paragraph 0040) in which charge based on a dark current is accumulated in the lateral overflow integration capacitor in a state where the charge photoelectrically converted by the photoelectric conversion unit is not accumulated in the lateral overflow integration capacitor,(Mabuchi further teaches charge accumulation at the FD1 and FD2 is driven by the dark current. A subsequent readout of charges at the FD1 and FD2 that is executed in block 620 therefore represents an accumulation of the dark current at the floating diffusions associated with pixels, paragraph 0041. The charge accumulation at the FD2 includes the lateral overflow integration capacitor 215 and in the absence of light, the photoelectric conversion unit does not provide any charges to the floating diffusion nodes FD1 and FD2.)
[Claim 7]
Regarding claim 7, Mabuchi teaches all the limitations of claim 4, wherein the normal accumulation period and the virtual light-shielding accumulation period are set in separate frames, Mabuchi teaches in some embodiments, an estimate of a dark current (DC) pixel frame may be obtained by acquiring the value of dark current in the pixels of an entire pixel frame, separate from acquiring signal values of the pixels in the frame. This DC frame may then be used as a representative of the intensity of the dark current for the subsequently-acquired frames for as long as the conditions that determine intensity of the dark current remain reasonably unchanged (e.g., relatively short time has elapsed, no significant temperature differences from frame to frame, etc.), paragraph 0023.
[Claim 8]
Regarding claim 8, Mabuchi teaches all the limitations of claim 3, wherein the signal processing unit (Mabuchi, Figure 5, a processor 410) performs correction processing (Mabuchi, the processor 410 may be further configured to subtract the dark current level associated with each pixel from the signal level of each corresponding pixel in an image frame captured after the capture of DC frame yield image frame without contribution of dark current associated with floating diffusion regions. The processor 410 may receive one or more control inputs 440 related to the frequency of acquisition of the DC frame (e.g., time, temperature, brightness, etc.). Based on these control inputs, the processor 410 executes subtraction operations, that is, accessing the frame memory 430 for DC frame with DC data for pixels and subtracting the frame memory 430 from the signal data for the normal image frames (e.g., captured image data for pixels), paragraph 0039) of the pixel signal on one normal image generated on a basis of charge accumulated in the normal accumulation period by using one virtual light-shielded image generated on a basis of charge accumulated in the virtual light-shielding accumulation period, (Mabuchi teaches the capture of the normal image and a dark current image are based on the charge accumulated in the floating diffusion.
[Claim 9]
Regarding claim 9, Mabuchi teaches all the limitations of claim 3, wherein
the signal processing unit performs correction processing of the pixel signal on a plurality of normal images generated on a basis of charge accumulated in mutually different normal accumulation periods by using one virtual light-shielded image generated on a basis of charge accumulated in the virtual light-shielding accumulation period. Mabuchi teaches in Figure 4, a timing diagram where plurality of normal frames 301 are captured and a dark current frame 302 is taken. The processor described in Figure 5, makes a correction on plurality of normal frames using one dark current frame 302. The plurality of normal or regular frames 301 as shown in Figure 4 are mutually exclusive as they are shown in a timing diagram.
[Claim 12]
Regarding claim 12, Mabuchi teaches all the limitations of claim 3, wherein the signal processing unit performs AD conversion of a signal level on a basis of the same reset level for each of a normal image generated on a basis of charge accumulated in the normal accumulation period and a virtual light-shielded image generated on a basis of charge accumulated in the virtual light-shielding accumulation period.
Mabuchi in Figure 1 teaches that a readout circuitry 106 includes analog-to-digital converters (ADCs), which convert analog image data received from the pixel array 102 into a digital representation. The digital representation of the image data may be provided to the function logic 110. In some embodiments, the data transmission circuitry 108 may receive the digital representations of the image data from the ADCs in parallel and may provide the image data to the function logic 110 in series, paragraph 0028. The reset level taught by Mabuchi is same as the supply connected to the AVDD.
[Claim 14]
Regarding claim 14, Mabuchi teaches all the limitations of claim 1, wherein
the pixel (Mabuchi, (Mabuchi, Figure 1 , a pixel array 102 including unit image sensor pixel 103) includes:
a photodiode (Mabuchi, Figure 3A, photodiode PD 211 used as the photoelectric conversion unit;
a transfer transistor (Mabuchi, Figure 3A, a transfer (TX) transistor 212,) that transfers charge accumulated in the photodiode to a floating diffusion;
a pass transistor (Mabuchi, Figure 3A, a dual floating diffusion (DFD) transistor 216) that sets a path through which the charge accumulated in the lateral overflow integration capacitor is transferred to the floating diffusion (Mabuchi, Figure 3A , a floating diffusion (FD1) 213 connected to a capacitor (FDC) 219, a transfer transistor 212, a dual floating diffusion (DFD) transistor 216, paragraph 0031);
a reset transistor (Mabuchi, Figure 3A, a reset (RST) transistor 214) that resets the floating diffusion;
an amplification transistor (Mabuchi, Figure 3A, source follower (SF) transistor 220) that outputs a signal according to a potential of the floating diffusion; and
a selection transistor (Mabuchi, Figure 3A, a row select (RS) transistor 221) that selects an output of the amplification transistor (Mabuchi, Figure 3A, the row select (RS) transistor 221 to read out dark current level associated with each pixel 203, paragraph 0036) .
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
Claim 4 is rejected under 35 U.S.C. 103 as being unpatentable over Mabuchi, Keiji (US-2022/0141406-A1) in view of Okura et al. (US-2022/0408047-A1).
[Claim 4]
Regarding claim 4, Mabuchi teaches all the limitations of claim 3.
Mabuchi does not teach wherein each of the normal accumulation period and the virtual light-shielding accumulation period includes a timing of reading the charge accumulated in the photoelectric conversion unit as a single unit, and a timing of collectively reading the charge accumulated in the photoelectric conversion unit and the charge accumulated in the lateral overflow integration capacitor.
Okura teaches a similar imaging device (Okura, Figure 1, solid-state imaging system 10) that includes a lateral overflow capacitor (Okura, Figure 2, CS11). Okura further in Figure 5 teaches during a virtual light-shielding (Okura, Figure 5, period when SG (i.e. storage transistor) and TG (i.e. transfer transistor) goes high a reading of virtual light shielding of the charge accumulated in the photelectric conversion unit as a single unit (I.e. with TG high, the photoelectric conversion unit is connected as a single unit) and when TG goes low, and SG remains high, the charge accumulated in the overflow capacitor CS11 is being read.
Okura further teaches in Figure 5, a reading of normal accumulation period, where the photoelectric conversion unit is read as a single unit (via TG signal high and SG signal high. When the TG signal goes low, the charge accumulated in the lateral overflow capacitor (i.e. CS11) is being read with SG remaining high.
Okura teaches an embodiment, where signals produced with different conversion gains and having different signal directions can be read. According to the present invention, signals produced with different conversion gains and having different signal directions can be read, but also an increase in power consumption and circuit area can be prevented, a high dynamic range can be provided, and high image quality is thus achieved, paragraph 0022.
Therefore, it would have been obvious to a person having ordinary skill in the art before the effective filing date of the claimed invention to modify Mabuchi with Okura with the motivation to reduce power consumption and increase circuit area can be prevented, a high dynamic range can be provided, and high image quality is thus achieved, paragraph 0022.
Claims 5, 15, 17 and 18 are rejected under 35 U.S.C. 103 as being unpatentable over Mabuchi, Keiji (US-2022/0141406-A1) in view of Miyauchi et al. (US-2022/0385852-A1).
[Claim 5]
Regarding claim 5, Mabuchi teaches all the limitations of claim 4.
Mabuchi does not teach wherein each of the normal accumulation period and the virtual light-shielding accumulation period includes a timing of reading the charge accumulated in the photoelectric conversion unit with a different conversion efficiency.
Miyachi further teaches a switching transistor (Miyauchi, Figure 2, a first switching transistor LG11_Tr). This transistor when in conduction adds capacitor CS11 in the floating diffusion node FD11. The addition of the capacitor changes the conversion efficiency of the pixel circuit.
Miyauchi teaches in Figure 2, a similar solid-state imaging device 10 that includes a pixel 200 that have two types of conversion gains and the conversion gain based on the capacitances of the floating diffusion FD11, the first capacitor CS11, and the second capacitor CS12 are set as follows (see also FIG. 3B). The capacitance CFD of the floating diffusion FD11 is very small for achieving a high gain and a low noise. The capacitance CS1 of the first capacitor CS11 is greater than the capacitance of the high-capacitance photodiode PD11 or a middle capacitance for the purpose of minimizing degradation of the SNR. The capacitance CS2 of the second capacitor CS12 is very large (electrostatic capacitance) for achieving a high full well capacity (FWC). The capacitance CS2 of the second capacitor CS12 is greater than the capacitance CS1 of the first capacitor CS11 and the capacitance CFD of the floating diffusion FD11. The capacitance CS1 of the first capacitor CS11 is mainly used for achieving the middle conversion gain, and the capacitance CS2 of the second capacitor CS12 is additionally used for achieving the low conversion gain, paragraph 0058.
Miyauchi teaches a conversion gain read-out mode with high conversion gain (HCG) signal and the low conversion gain (LCG). As a result, it minimizes the degradation of the SNR is to use triple-conversion-gain read-out involving dual-conversion-gain read-out, the LOFIC architecture,, paragraph 0014.
Therefore, it would have been obvious to a person having ordinary skill in the art before the effective filing date of the claimed invention to modify Mabuchi with Miyauchi with the motivation to minimize the degradation of SNR, paragraph 0014.
[Claim 15]
Regarding claim 15, Mabuchi teaches all the limitations of claim 14.
Mabuchi does not teach wherein
the pixel further includes a switching transistor that switches conversion efficiency in the amplification transistor.
Miyachi further teaches a switching transistor (Miyauchi, Figure 2, a first switching transistor LG11_Tr). This transistor when in conduction adds capacitor CS11 in the floating diffusion node FD11. The addition of the capacitor changes the conversion efficiency of the pixel circuit.
Miyauchi teaches in Figure 2, a similar solid-state imaging device 10 that includes a pixel 200 that have two types of conversion gains and the conversion gain based on the capacitances of the floating diffusion FD11, the first capacitor CS11, and the second capacitor CS12 are set as follows (see also FIG. 3B). The capacitance CFD of the floating diffusion FD11 is very small for achieving a high gain and a low noise. The capacitance CS1 of the first capacitor CS11 is greater than the capacitance of the high-capacitance photodiode PD11 or a middle capacitance for the purpose of minimizing degradation of the SNR. The capacitance CS2 of the second capacitor CS12 is very large (electrostatic capacitance) for achieving a high full well capacity (FWC). The capacitance CS2 of the second capacitor CS12 is greater than the capacitance CS1 of the first capacitor CS11 and the capacitance CFD of the floating diffusion FD11. The capacitance CS1 of the first capacitor CS11 is mainly used for achieving the middle conversion gain, and the capacitance CS2 of the second capacitor CS12 is additionally used for achieving the low conversion gain, paragraph 0058.
Miyauchi teaches a conversion gain read-out mode with high conversion gain (HCG) signal and the low conversion gain (LCG). As a result, it minimizes the degradation of the SNR is to use triple-conversion-gain read-out involving dual-conversion-gain read-out, the LOFIC architecture,, paragraph 0014.
Therefore, it would have been obvious to a person having ordinary skill in the art before the effective filing date of the claimed invention to modify Mabuchi with Miyauchi with the motivation to minimize the degradation of SNR, paragraph 0014.
[Claim 17]
Regarding claim 17, Mabuchi teaches all the limitations of claim 15,
Mabuchi does not teach wherein in the virtual light-shielding accumulation period, the transfer transistor is turned off at a timing when the charge accumulated in the photoelectric conversion unit is read as a single unit.
However, Mabuchi does not wherein the transfer transistor is turned off at a timing when the charge accumulated in the photoelectric conversion unit is read as a single unit.
Miyauchi teaches in Figure 2, a solid-state imaging device 10 that includes pixel part 20 and pixel 200. Miyauchi in Figure 4, further teaches that during dark current read mode the transfer transistor remains turned off as shown in HCG SIG and LOFIC SIG and MCG SIG period. Miyauchi further teaches that each pixel 200 are comprised of one photodiode PD11 and he pixel 200 includes: a floating diffusion FD 11 storing therein the to-be-transferred charges so that the charge can be read in the form of a voltage signal; a photodiode PD11 serving as a photoelectric conversion element for storing, in an exposure period PEXP, therein the charges determined by the amount of incident light; a transfer transistor TG11-Tr serving as a transfer element for transferring to the floating diffusion FD11 the charges stored in the photodiode PD11 serving as the photoelectric conversion element, where the transfer transistor TG11-Tr remains in a non-conduction state during the exposure period PEXP and remains in a conduction state during a transfer period; and a reset transistor RST11-Tr serving as a reset element for performing a reset operation of discharging the charges stored in the floating diffusion FD11, paragraph 0047.
Miyauchi teaches that the present invention is designed to provide a solid-state imaging device, a method for driving a solid-state imaging device, and an electronic apparatus that are capable of preventing degradation of the SNR at a conjunction point of signals produced with different conversion gains while avoiding being affected by the optical specifications, paragraph 0016.
Therefore, it would have been obvious to a person having ordinary skill in the art before the effective filing date of the claimed invention to modify Mabuchi with Miyauchi with the motivation of preventing degradation of the SNR at a conjunction point of signals produced with different conversion gains while avoiding being affected by the optical specifications, paragraph 0016.
[Claim 18]
Regarding claim 18, Mabuchi teaches all the limitations of claim 15.
Mabuchi does not teach the image device further comprising
an overflow control transistor that controls overflow of charge from the photoelectric conversion unit to the lateral overflow integration capacitor.
Miyauchi teaches in Figure 2 a similar a similar solid-state imaging device 10 that includes a pixel 200, an overflow path transistor LO11-Tr (i.e. lateral overflow control transistor)that controls the charge from the photoelectric conversion unit (Miyauchi, Figure 2, PD11) to the lateral overflow integration capacitor (i.e. CS12). Miyauchi further teaches the overflow path transistor LO11-Tr serving as an overflow gate element formed on the overflow path OVFP, where the overflow path transistor LO11-Tr is configured to control the conduction through the overflow path OVFP, paragraph 0049.
Therefore, it would have been obvious to a person having ordinary skill in the art before the effective filing date of the claimed invention to modify Mabuchi with Miyauchi with the motivation to readout the charge generated by each pixel unit correctly.
Claims 6 and 11 are rejected under 35 U.S.C. 103 as being unpatentable over Mabuchi, Keiji (US-2022/0141406-A1) in view of Tian et al. (US-2011/0228144-A1).
[Claim 6]
Regarding claim 6, Mabuchi teaches all the limitations of claim 4.
Mabuchi does not teach wherein
the normal accumulation period and the virtual light-shielding accumulation period are set in a same frame.
Tian teaches similar imaging apparatus that in embodiments, the image frame time is divided into two sections. The first section is for `0-bias frame,` and the second section is for `normal light frame`. During `0-bias frame,` the vfilm voltage (vfilm may be considered as a biasing electrode) is set to be the same as diode voltage. This will make the film not sensitive to light; hence the readout signal during this section is dominated by silicon dark current, paragraph 0191. Tian further teaches in Figure 10, that the integration for zero bias frame and for normal light frame are done consecutively on a single frame.
Therefore, it would have been obvious to a person having ordinary skill in the art before the effective filing date of the claimed invention to modify Mabuchi with Tian with the motivation to suppress dark currents and detect accurate signal from each photosensitive material.
[Claim 11]
Regarding claim 11, Mabuchi teaches all the limitations of claim 3.
Mabuchi does not teach wherein
the signal processing unit performs analog to digital (AD) conversion of a signal level on a basis of reset levels different from each other for each of a normal image generated on a basis of charge accumulated in the normal accumulation period and a virtual light-shielded image generated on a basis of charge accumulated in the virtual light-shielding accumulation period.
Tian teaches in Figure 6, a similar image sensor that includes a plurality of pixels that includes a reset transistor M1 .609 connected between a reference voltage 611 and a floating diffusion node 605. Tian teaches the reset transistor used to reset the diode to a reference voltage. 611 is `VLEVEL,` also termed a reference voltage node or an electrode that ties to the drain of transistor M1, providing reference level or voltage. A control circuitry is used to vary the reference voltage level during operation of the pixel circuit (used for reset of the charge store and for the read out transistor). 613 is readout transistor M2. 615 is select transistor M3. 617 is `sel,` an electrode ties to the gate of transistor M3. 619 is `vcol,` a read out line or electrode that is shared among a group of pixels, used to send out pixel values, paragraph 0179. Tian further teaches in the Figure 5, an ADC 160 that converts pixel signal into digital code. Tian further teaches that the pixel circuitry may be in communication with other electronics (e.g. chip processors 2008).
Tian teaches a method of dark current correction The use of a low voltage on the pixel electrode significantly suppresses the dark current of the pixel circuitry under a dark condition. VLEVEL is pulled back to high voltage such as 3V, to minimize leakage path of transistor M1, and to prepare for readout phase, paragraph 0081.
Therefore, it would have been obvious to a person having ordinary skill in the art before the effective filing date of the claimed invention to modify Mabuchi with Tian with the motivation to suppress dark currents.
Claim 10 is rejected under 35 U.S.C. 103 as being unpatentable over Mabuchi, Keiji (US-2022/0141406-A1) in view of Price et al. (US-2023/0117006-A1).
[Claim 10]
Regarding claim 10, Mabuchi teaches all the limitations of claim 3.
Mabuchi does not teach wherein the signal processing unit performs correction processing of the pixel signal on one normal image generated on a basis of charge accumulated in the normal accumulation period by using a plurality of virtual light-shielded images generated on a basis of charge accumulated in mutually different virtual light-shielding accumulation periods.
Price teaches a system for obtaining dark current images that include one or more processors in Figure 5, where in some instances, multiple estimated dark current images may be utilized to generate a final dark current image that further eliminates the “background” objects, resulting in a more precise representation of the dark counts associated with the image sensor (relative to the estimated dark current images). FIG. 5 illustrates a conceptual representation of generating a final dark current image based on estimated dark current images. In particular, FIG. 5 illustrates weighted averaging 502 performed to generate a final dark current image 504 based on the estimated dark current images 408, 412, and 416, paragraph 0059. The weighted averaging 502 may utilize weights to combine/average pixel values of pixels in the estimated dark current images 408, 412, and 416 that have common coordinates to generate a value for an output pixel (with the same coordinates) of the final dark current image 504, paragraph 0060. The processor (Kirk, Figure 1, processor 102) then a system that includes one or more processors, and one or more hardware storage devices storing instructions that are executable by the one or more processors to configure the system to perform various acts. The acts include obtaining a first image frame, generating a first low-pass filtered image by applying a low-pass filter to the first image frame, and generating a first estimated dark current image by subtracting the first low-pass filtered image from the first image frame, paragraph 0016.
Price teaches multiple estimated dark current images may be used to generate a final dark current image (e.g., by weighted averaging, where per-pixel weights are determined based on average values of surrounding pixels). The final dark current image may be used to generate dark current compensated images, such as by subtracting the final dark current image from newly captured imagery (e.g., newly captured SPAD imagery). Final dark current images may be captured at runtime according to any suitable interval, timing, or schedule. Price further teaches techniques to furthermore provide dark current compensation functionality in a manner that advantageously avoids reliance on SPAD sensor temperature data at runtime, paragraph 0038.
Therefore, it would have been obvious to a person having ordinary skill in the art before the effective filing date of the claimed invention to modify Mabuchi with Price to provide dark current compensation functionality in a manner that advantageously avoids reliance on SPAD sensor temperature data at runtime, paragraph 0038.
Claim 19 is rejected under 35 U.S.C. 103 as being unpatentable over Mabuchi, Keiji (US-2022/0141406-A1) in view of Miyatake et al. (US-2012/0235023-A1).
[Claim 19]
Regarding claim 19, Mabuchi teaches all the limitations of claim 14,
Mabuchi does not teach, wherein
the transfer transistor is ternary driven among a level at which overflow from the photoelectric conversion unit to the floating diffusion is enabled, a level at which overflow from the photoelectric conversion unit to the floating diffusion is disabled, and a level at which charge is transferred from the photoelectric conversion unit to the floating diffusion.
Miyatake teaches a similar solid-state image-sensing device that includes a transfer transistor T1, driven by a gate control signal φ.TX (Miyatake, Figure 1). Miyatake further teaches in Figure 10, where the transfer transistor T1 driven with gate control signal φ.TX driven ternary with VH, VM and VL levels. Miyatake further teaches as in the first embodiment, the signal φ.V is turned low to turn the MOS transistor T4 off. Then, the level of the signal φ.TX is turned to VM, and in addition the signal φ.RS is turned high.
Miyatake further teaches a level at which overflow from the photoelectric conversion unit to the floating diffusion is enabled (Miyatake, Figure 10, this is the period when φ.TX is at VH, φ.RS is low, and φ.V is low),
a level at which overflow from the photoelectric conversion unit to the floating diffusion is disabled, (Miyatake, Figure 10, this is the period when φ.TX is low VL, φ.RS is low and φ.V is high)
a level at which charge is transferred from the photoelectric conversion unit to the floating diffusion, (Miyatake, Figure 10, this is the period when φ.TX is at VM, φ.RS is low and φ.V is low.
Miyatake teaches driving the transfer transistor φ.TX ternary with plurality of voltage levels and as a result as a result of the transistor being operated in a subthreshold region at least in part of the subject brightness range, it is possible to obtain a wide dynamic range in a solid-state image-sensing device using buried photodiodes, paragraph 0020.
Therefore, it would have been obvious to a person having ordinary skill in the art before the effective filing date of the claimed invention to modify Mabuchi with Miyatake with the motivation to obtain a wide dynamic range in a solid-state image-sensing device using buried photodiodes, paragraph 0020.
Claim 20 is rejected under 35 U.S.C. 103 as being unpatentable over Mabuchi, Keiji (US-2022/0141406-A1) in view of Kobayashi et al. (US-2008/0129847-A1).
[Claim 20]
Regarding claim 20, Mabuchi teaches all the limitations of claim 3.
Mabuchi does not teach wherein the signal processing unit determines whether or not to perform correction processing of the pixel signal on a basis of a temperature around the pixel.
Kobayashi teaches a digital camera shown in Figure 1, that includes a solid-state imaging device 5, and a digital signal processing unit 17, that includes an operation control portion 38 (Kobayashi, Figure 4, operation control portion 38) controls the operation of the dark current correcting portion 36 in accordance with photographing conditions, such as the temperature information from the temperature sensor 26 and photographing ISO sensitivity information set in a photographing mode. For example, the operation control portion 38 makes a control such that the dark current correcting portion 36 is stopped in a photographing condition that a dark current decreases at the time of low temperature or setting of low photographing ISO sensitivity. Also, the operation control portion 38 makes a control such that the dark current correcting portion 36 is operated in a photographing condition that a dark current increases at the time of high temperature or setting of high photographing ISO sensitivity. Kobayashi further teaches in Figure 10, an operation flow in the imaging mode of the digital camera, if it is determined `YES` in step S13, the temperature information Timaging around the solid-state imaging device 5 at the time of the imaging in step S11 is acquired (step S31), and the linear function for correction F(y) is generated on the basis of the temperature information Timaging in the third mode (step S34). In step S16,
Kobayashi teaches a correction method based on a temperature of the pixel measured by the temperature sensor (Kobayashi, Figure 1, temperature sensor 26). The operation control 38 makes a control such that the dark current correcting portion 36 is operated in a photographing condition that a dark current increases at the time of high temperature or setting of high photographing ISO sensitivity. Since it is possible to realize an efficient operation by such control, the power consumption can be reduced.
Therefore, it would have been obvious to a person having ordinary skill in the art before the effective filing date of the claimed invention to modify Mabuchi with Kobayashi with motivation to reduce power consumption.
Allowable Subject Matter
Claims 13 and 16 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
[Claim 13]
Regarding claim 13, Mabuchi teaches all the limitations of claim 3,
Mabuchi does not teach wherein
a power supply voltage applied to the lateral overflow integration capacitor during the virtual light-shielding accumulation period is made higher than a power supply voltage applied to the lateral overflow integration capacitor during the normal accumulation period.
Mun et al. (US-2022/0013551-A1) teaches in Figure 2, a similar image sensor device 210 that includes a lateral overflow integration capacitor CAP 232, the capacitor 232 is also coupled to a voltage, such as voltage VDD, for adjusting the capacitance of the capacitor 232 to store as many charges as possible overflowing from the pixel cell 210, paragraph 0039. Mun does not teach applying power supply voltage during the light-shielding accumulation period that is higher than a power supply voltage that is applied during the normal accumulation period.
Ono et al.(US-2023/0300495-A1) teaches in Figure 1, a similar image sensor device 1, that includes a lateral overflow integration capacitor 1105b where one of the electrode of the capacitor 1105b is connected a power supply SubFD-VDD. Ono does not teach applying power supply voltage during the light-shielding accumulation period that is higher than a power supply voltage that is applied during the normal accumulation period.
[Claim 16]
Regarding claim 16, prior art does not teach or reasonably suggest wherein
when the charge photoelectrically converted by the photoelectric conversion unit is not accumulated in the lateral overflow integration capacitor, the pass transistor is turned off, and the transfer transistor, the reset transistor, and the switching transistor are turned on
Miyauchi teaches in Figure 2 a pass transistor SG11-Tr, a transfer transistor TG11-Tr, a reset transistor RST11-Tr and a switching transistor LG11-Tr, and a lateral overflow integration capacitor CS12. Miyauchi further teaches in Figure 4, a timing chart, including parts (A) to (E), to illustrate, as an example, a sequence of read-out operations performed in the dual-conversion-gain read-out mode and the overflow read-out mode on the pixels in the solid-state imaging device, paragraph 0078. During read-out of LOFIC(LCG) SIG, the pass transistor (i.e. SG11-Tr) is off, the transfer transistor is off. Miyauchi does not teach or fails to reasonably suggest to have the transfer transistor on during when the photoelectric conversion unit is not accumulated in the lateral overflow integrated capacitor, the transfer transistor is on.
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant’s disclosure. The following show additional prior art systems/methods for imaging apparatus:
Choi; Woon Il US-20230421921-A1
PARK; Seokyong US-20240022800-A1
Koifman; Vladimir US-20240098379-A1
HOTTA; Ryotaro US-20240365027-A1
SAITO; Tetsuo US-20240380988-A1
Ono; Toshiaki US-20230300495-A1
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/MEHEDI NMN HASSAN/Examiner, Art Unit 2637
/SINH TRAN/
Supervisory Primary Examiner, Art Unit 2637
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