Prosecution Insights
Last updated: October 26, 2026
Application No. 19/117,810

IMPEDANCE CALIBRATION DEVICE

Non-Final OA §102
Filed
Apr 02, 2025
Priority
Oct 12, 2022 — RE 10-2022-0130472 +2 more
Examiner
TRAN, ANH Q
Art Unit
2845
Tech Center
2800 — Semiconductors & Electrical Systems
Assignee
Qualitas Semiconductor Co. Ltd.
OA Round
1 (Non-Final)
90%
Grant Probability
Favorable
1-2
OA Rounds
1m
Est. Remaining
95%
With Interview

Examiner Intelligence

Grants 90% — above average
90%
Career Allowance Rate
1026 granted / 1138 resolved
+22.2% vs TC avg
Minimal +5% lift
Without
With
+5.0%
Interview Lift
resolved cases with interview
Fast prosecutor
1y 8m
Avg Prosecution
9 currently pending
Career history
1147
Total Applications
across all art units

Statute-Specific Performance

§101
2.1%
-37.9% vs TC avg
§103
30.7%
-9.3% vs TC avg
§102
40.1%
+0.1% vs TC avg
§112
9.5%
-30.5% vs TC avg
Black line = Tech Center average estimate • Based on career data from 1138 resolved cases

Office Action

§102
DETAILED ACTION Notice of Pre-AIA or AIA Status The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA . Claim Rejections - 35 USC § 102 In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status. The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action: A person shall be entitled to a patent unless – (a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention. Claim(s) 1, 7-8, 10, 13-14 is/are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Suenaga Shuji (JP2011211608A with English translation attachment). Claim 1, Shuji discloses an impedance calibration device (Fig. 1) comprising: a target driver module including a pull-up resistor circuit (pull-buffer unit 121, Fig. 1) and a pull-down resistor circuit (pull-down buffer unit 122, Fig. 1); a resistance measurement module (comparator CMP1 and counter 124, Fig. 1) configured to measure a pull-up resistance value of the pull-up resistor circuit and a pull-down resistance value of the pull-down resistor circuit; and a control module (control circuit 127, Fig. 1) configured to generate a pull-up code (signals P1 – P3, Fig. 1) for adjusting the pull-up resistance value and a pull-down code (signals N1 – N3, Fig. 1) for adjusting the pull-down resistance value in order to calibrate the pull-up resistance value and the pull-down resistance value; wherein the control module updates the pull-down code based on the pull-down resistance value (MN121 – MN123, Fig. 1) and a preset target pull-down resistance value (resistor Rref=1740 Ω and transistor MN131=10 Ω, see Figs. 6 and 7), and updates the pull-up code based on the pull-up resistance value (MN121 – MN123, Fig. 1) and a preset target pull-up resistance value (resistor Rref=1740 Ω and transistor MN132=10 Ω, see Figs. 3-4). Claim 7, Shuji discloses the impedance calibration device of claim 1, wherein the pull-up resistor circuit comprises a plurality of transistors connected in parallel (transistors MP121 – MP123, Fig. 1), and selectively connects one or more of the plurality of transistors to a signal transmission path based on the pull-up code. Claim 8, Shuji discloses the impedance calibration device, wherein the pull-down resistor circuit comprises a plurality of transistors connected in parallel (transistors MN121 - MN123) , and selectively connects one or more of the plurality of transistors to a signal transmission path based on the pull-down code. Claim 10, Shuji discloses an impedance calibration device (Fig. 1) comprising: a target driver module including a pull-up resistor circuit (Pull-up buffer unit 121, Fig. 1) capable of adjusting a resistance value based on a pull-up code (signals P1 – P3, Fig. 1) and a pull-down resistor circuit (Pull-down buffer unit 122, Fig. 1) capable of adjusting a resistance value based on a pull-down code (signals N1 – N3, Fig. 1); a resistance measurement module (comparator CMP121, counter 124, Fig. 1) including a reference signal circuit (transistors MP131, MN132, and resistor Rref, Fig. 1) configured to generate a reference signal for measuring a resistance value (resistor Rref=1740 Ω and transistor MN131=10 Ω, see Figs. 6 and 7 or resistor Rref=1740 Ω and transistor MN132=10 Ω, see Figs. 3-4) and a measurement circuit (comparator CMP121, Fig. 1) configured to apply the reference signal to the target driver module and measure a generated signal generated at an output node (TP1/TP2 or node N123, Fig. 1) of the target driver module; and a control module (controller 127, Fig. 1) configured to control the target driver module or the resistance measurement module and calibrate the measured resistance value; wherein the reference signal circuit comprises at least one voltage source (VDD supply terminal VDD connected to transistor MP131 or ground terminal GND connected to transistor MN132), at least one current source (resistor Rref is consider as current source), and a plurality of switches (transistors MP131 and MN132) configured to selectively connect the voltage source or the current source to the target driver module. Claim 13, Shuji discloses the impedance calibration device of claim 10, wherein the pull-up resistor circuit (pull-up buffer unit 121, Fig. 1) selectively connects one or more of a plurality of transistors (transistors MP121 – MP123, Fig. 1) to a signal transmission path based on a pull-up code (signals P1 – P3). Claim 14, Shuji discloses the impedance calibration device of claim 10, wherein the pull-down resistor circuit (pull-down buffer unit 122, Fig. 1) selectively connects one or more of a plurality of transistors (transistors MN121 – MN123) to a signal transmission path based on a pull-down code (signals N1 – N3). Allowable Subject Matter Claims 2-6, 9, 11-12, 15-21 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims. Conclusion The prior art made of record and not relied upon is considered pertinent to applicant's disclosure. Akeboshi Noriyuki (JP2005229177A) and Anderson et al. (US 2014/0325135) disclose an impedance calibration device comprising: a target driver module including a pull-up resistor circuit and a pull-down resistor circuit; a resistance measurement module configured to measure a pull-up resistance value of the pull-up resistor circuit and a pull-down resistance value of the pull-down resistor circuit; and a control module configured to generate a pull-up code for adjusting the pull-up resistance value and a pull-down code for adjusting the pull-down resistance value in order to calibrate the pull-up resistance value and the pull-down resistance value; wherein the control module updates the pull-down code based on the pull-down resistance value and a preset target pull-down resistance value, and updates the pull-up code based on the pull-up resistance value and a preset target pull-up resistance value. Lee et al. (US 2017/0077927) disclose an impedance calibration device comprising: a target driver module including a pull-up resistor circuit and a pull-down resistor circuit; a resistance measurement module configured to measure a pull-up resistance value of the pull-up resistor circuit and a pull-down resistance value of the pull-down resistor circuit; and a control module configured to generate a pull-up code for adjusting the pull-up resistance value and a pull-down code for adjusting the pull-down resistance value in order to calibrate the pull-up resistance value and the pull-down resistance value. Any inquiry concerning this communication or earlier communications from the examiner should be directed to ANH Q TRAN whose telephone number is (571)272-1813. The examiner can normally be reached M-F: 9AM - 5PM. Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice. If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Alexander H Taningco can be reached at 571-272-8048. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300. Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000. /ANH Q TRAN/Primary Examiner, Art Unit 2845 9/23/26
Read full office action

Prosecution Timeline

Apr 02, 2025
Application Filed
Sep 28, 2026
Non-Final Rejection mailed — §102 (current)

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Study what changed to get past this examiner. Based on 5 most recent grants.

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Prosecution Projections

1-2
Expected OA Rounds
90%
Grant Probability
95%
With Interview (+5.0%)
1y 8m (~1m remaining)
Median Time to Grant
Low
PTA Risk
Based on 1138 resolved cases by this examiner. Grant probability derived from career allowance rate.

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