Detailed Office Action
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Abstract
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Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claims 1, 5 – 8, 11 – 19 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Tachibana et al. (USPGPUB 2003/0234736).
Regarding claim 1, Tachibana et al. disclose a circuit arrangement (fig. 6) comprising a digital-to-analog Converter DAC (paragraph 0099), and a comparator (30, fig. 6) the DAC comprising: a coarse resistor-string digital-to-analog conversion unit (R4,…, R15) for selectively outputting 2N-level analog voltages in response to upper N-bit digital data, wherein N is a natural number greater than or equal to 2 (fig. 6); a fine resistor-string digital-to-analog conversion unit (R0,…R3) for selectively outputting 2N-level analog voltages in response to lower N-bit digital data (fig. 6), and a combining unit (21, C6, 30 form the combination circuit) for combining an output of the coarse resistor-string digital-to-analog conversion unit and the output of the fine resistor-string digital-to- analog conversion unit (fig. 6), the combining unit comprising a capacitor (C6), the output of the fine resistor-string digital-to-analog conversion unit being connectable to a first terminal of the capacitor (fig. 6); a second terminal of the capacitor being connectable connected to a first input of the comparator (30) and the output of the coarse resistor-string digital-to-analog conversion unit is connectable to the first terminal of the capacitor (fig. 6).
Regarding claim 5, Tachibana et al. disclose a circuit arrangement (fig. 6), wherein the output of the coarse resistor string digital to analog conversion unit is connectable to the first terminal of the capacitor, further comprising a frontend circuit (22) configured to receive an input signal and to supply a processed signal to a second input of the comparator (30) the frontend circuit being permanently connected to the second input of the comparator and the processed signal is generated on the basis of the input signal and the output of the coarse resistor-string digital-to-analog conversion unit (fig. 6).
Regarding claim 6, Tachibana et al. disclose a discriminator (figs. 6, 9) comprising a plurality of discriminator stages for comparing an input signal with multiple thresholds, each of the discriminator stages comprising a comparator (30); a coarse multiplexer (61, fig. 9) being connectable to a selected tap between resistors of a coarse resistor-string (R4,…, R15) for selectively outputting 2ᵀ -level analog voltages in response to upper N-bit digital data, wherein N is a natural number greater than or equal to 2 (fig. 6, 9); a fine multiplexer (62, fig. 9) being connectable to a selected tap between resistors of a fine resistor-string for selectively outputting 2N-level analog voltages in response to lower N- bit digital data (figs. 6, 9), and a combining unit (21, C6, 30 form the combining circuit) for combining an output of the coarse multiplexer and the output of the fine multiplexer, the combining unit comprising a capacitor (C6, fig. 6), the output of the fine multiplexer being connectable to a first terminal of the capacitor, a second terminal of the capacitor being connectable connected to a first input of the comparator (figs. 6, 9).
Regarding claim 7, Tachibana et al. disclose discriminator (figs. 6, 9 ) wherein the output of the coarse multiplexer is connectable to a second input of the comparator (figs. 6, 9).
Regarding claim 8, Tachibana et al. disclose discriminator (figs. 6, 9) wherein the output of the coarse multiplexer is connectable to a frontend circuit (22, fig. 6) configured to receive an input signal and to supply a processed signal to a second input of the comparator (30) the processed signal being based on the input signal and the output of the coarse multiplexer.
Regarding claim 11, Tachibana et al. disclose a Digital-to-Analog Converter- DAC (figs. 6, 9), comprising: a coarse resistor-string digital-to-analog conversion unit (R4,…,R15, 61 form the string the DAC)-for selectively outputting 2N-level analog voltages in response to upper N-bit digital data, wherein N is a natural number greater than or equal to 2 (fig. 6); a fine resistor-string digital-to-analog conversion unit (R0,…, R3, 62 form the string DAC) for selectively outputting 2N-level analog voltages in response to lower N-bit digital data, and a combining unit (21, C6, 30 form the combining circuit) for combining an output of the coarse resistor-string digital-to-analog conversion unit and the output of the fine resistor-string digital-to-analog conversion unit, the combining unit comprising a capacitor (C6), the output of the coarse resistor-string digital-to-analog conversion unit and the output of the fine resistor-string digital-to-analog conversion unit being connectable (61, 62) to a first terminal of the capacitor, wherein the coarse resistor-string digital-to- analog conversion unit comprises a coarse resistor-string (R4,…, R15) and a coarse multiplexer (61, fig. 9) configured to be connected to a selected tap between resistors of the coarse resistor-string, and the fine resistor-string digital-to-analog conversion comprises a fine resistor- string (figs. 6, 9) and a fine multiplexer (62, fig. 9) configured to be connected to a selected tap between resistors of the fine resistor-string, the coarse resistor-string and the fine resistor-string being connected in series (figs. 6, 9).
Regarding claim 12, Tachibana et al. disclose a Digital-to-Analog Converter- DAC (figs.1, 6, 9), further comprising a first buffer receiving a reference voltage and controlling a voltage supplied to the coarse resistor-string (fig. 1).
Regarding claim 13, Tachibana et al. disclose a Digital-to-Analog Converter- DAC (figs. 1, 6, 9), wherein the first buffer comprises a first buffer capacitor for storing an offset voltage (fig. 1).
Regarding claim 14, Tachibana et al. disclose a Digital-to-Analog Converter- DAC (figs. 1, 6, 9), wherein the first buffer further comprises a second buffer capacitor for storing a reference voltage (figs. 1, 6, 9).
Regarding claim 15, Tachibana et al. disclose a Digital-to-Analog Converter- DAC (figs. 1, 6, 9), wherein first buffer comprises a first buffer circuit and a second buffer circuit , each of the first and the second buffer circuits comprising a first buffer capacitor, respectively, the first buffer circuit and the second buffer circuit being configured to be alternatingly operated (figs. 1, 6, 9).
Regarding claim 16, Tachibana et al. disclose a Digital-to-Analog Converter- DAC (figs. 1, 6, 9),, wherein the coarse resistor-string digital-to-analog conversion unit further comprises a high-ohmic coarse resistor-string which is connected in parallel to the coarse resistor-string, a resistance of the high-ohmic coarse resistor-string being greater than the resistance of the coarse resistor-string, the high-ohmic coarse resistor-string being configured to be connected to the coarse multiplexer when the coarse multiplexer is connected to the first terminal of the capacitor (figs. 1, 6, 9).
Regarding claim 17, Tachibana et al. disclose a Digital-to-Analog Converter- DAC (figs. 1, 6, 9), wherein the fine resistor-string digital-to-analog conversion unit further comprises a low-ohmic fine resistor-string which is connected in parallel to the fine resistor-string, a resistance of the low-ohmic fine resistor-string being less than the resistance of the fine resistor-string-, the low-ohmic fine resistor-string being configured to be connected to the fine multiplexer when the fine multiplexer is connected to the first terminal of the capacitor(HH) (figs. 1, 6, 9).
Regarding claim 18, Tachibana et al. disclose a Digital-to-Analog Converter- DAC (figs. 1, 6, 9), further comprising an additional switchable resistor-string-between the coarse resistor-string and the fine resistor-string (figs. 1, 6, 9).
Regarding claim 19, Tachibana et al. disclose a circuit arrangement (figs. 1, 6, 9), wherein the output of the fine resistor-string digital-to-analog conversion unit is connected to the first terminal of the capacitor during a phase φ2, and the coarse resistor-string digital-to-analog conversion unit is connected to the first terminal of the capacitor during a phase φ₁ different from phase φ2 (figs. 1, 6, 9).
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to JEAN BRUNER JEANGLAUDE whose telephone number is (571)272-1804. The examiner can normally be reached Monday-Thursday 7:00 AM-5:00 PM.
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/JEAN B JEANGLAUDE/Primary Examiner, Art Unit 2845
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