DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Interpretation
The following is a quotation of 35 U.S.C. 112(f):
(f) Element in Claim for a Combination. – An element in a claim for a combination may be expressed as a means or step for performing a specified function without the recital of structure, material, or acts in support thereof, and such claim shall be construed to cover the corresponding structure, material, or acts described in the specification and equivalents thereof.
The following is a quotation of pre-AIA 35 U.S.C. 112, sixth paragraph:
An element in a claim for a combination may be expressed as a means or step for performing a specified function without the recital of structure, material, or acts in support thereof, and such claim shall be construed to cover the corresponding structure, material, or acts described in the specification and equivalents thereof.
The claims in this application are given their broadest reasonable interpretation using the plain meaning of the claim language in light of the specification as it would be understood by one of ordinary skill in the art. The broadest reasonable interpretation of a claim element (also commonly referred to as a claim limitation) is limited by the description in the specification when 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph, is invoked.
As explained in MPEP § 2181, subsection I, claim limitations that meet the following three-prong test will be interpreted under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph:
(A) the claim limitation uses the term “means” or “step” or a term used as a substitute for “means” that is a generic placeholder (also called a nonce term or a non-structural term having no specific structural meaning) for performing the claimed function;
(B) the term “means” or “step” or the generic placeholder is modified by functional language, typically, but not always linked by the transition word “for” (e.g., “means for”) or another linking word or phrase, such as “configured to” or “so that”; and
(C) the term “means” or “step” or the generic placeholder is not modified by sufficient structure, material, or acts for performing the claimed function.
Use of the word “means” (or “step”) in a claim with functional language creates a rebuttable presumption that the claim limitation is to be treated in accordance with 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph. The presumption that the claim limitation is interpreted under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph, is rebutted when the claim limitation recites sufficient structure, material, or acts to entirely perform the recited function.
Absence of the word “means” (or “step”) in a claim creates a rebuttable presumption that the claim limitation is not to be treated in accordance with 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph. The presumption that the claim limitation is not interpreted under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph, is rebutted when the claim limitation recites function without reciting sufficient structure, material or acts to entirely perform the recited function.
Claim limitations in this application that use the word “means” (or “step”) are being interpreted under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph, except as otherwise indicated in an Office action. Conversely, claim limitations in this application that do not use the word “means” (or “step”) are not being interpreted under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph, except as otherwise indicated in an Office action.
This application includes one or more claim limitations that do not use the word “means,” but are nonetheless being interpreted under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph, because the claim limitation(s) uses a generic placeholder that is coupled with functional language without reciting sufficient structure to perform the recited function and the generic placeholder is not preceded by a structural modifier. Such claim limitation(s) is/are: recovery block, deadlock manager block, deadlock information module, deadlock clear module, master recovery block, master blocks, virtual command generation module, virtual response reception module, command monitor module, response monitor module, deadlock detection module, system reset block, slave recovery block, slave blocks
Because this/these claim limitation(s) is/are being interpreted under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph, it/they is/are being interpreted to cover the corresponding structure described in the specification as performing the claimed function, and equivalents thereof.
If applicant does not intend to have this/these limitation(s) interpreted under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph, applicant may: (1) amend the claim limitation(s) to avoid it/them being interpreted under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph (e.g., by reciting sufficient structure to perform the claimed function); or (2) present a sufficient showing that the claim limitation(s) recite(s) sufficient structure to perform the claimed function so as to avoid it/them being interpreted under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph.
Claim Rejections - 35 USC § 112
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claims 1-20 are rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention.
Claim 1 recites “an order of deadlock occurrences of the deadlock transmitted from the recovery block.” However, this was recited as “recovery block that generates and transmits a deadlock occurrence signal,” so no antecedent basis for transmitting occurring without the signal. Also, it is unclear how “an order of deadlock occurrences” can be “of the deadlock transmitted” since only one deadlock is recited, whereas the claim limitation implies multiple deadlocks. Further clarification is necessary.
Further, claim 1 recites “transmits the deadlock resolution command configured to transmit in the order of deadlock occurrences of the occurrence locations to the recovery block,” but it is unclear what is being “configured to transmit.” Further clarification is necessary.
Claim 14 recites similar claim limitations and thus is rejected for similar reasons.
Claims 2-13 and claims 15-20 are rejected for being dependent upon rejected parent claims.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 1 and 7 is/are rejected under 35 U.S.C. 103 as being unpatentable over Armstrong (US 20020156939 A1) in view of Zhang (“Chapter 18: Industrial control system operation routines,” 2010, Elsevier Inc) in view of Gass (US 4162526 A) in view of Woo (US 20190302180 A1).
Per claim 1, Armstrong teaches
(Currently Amended) A recovery device configured to resolve a system deadlock .. ([0018] “an apparatus for monitoring the state of a computer system running multiple operating systems controlled by a partition manager;” wherein, monitoring the state may include deadlock states. The apparatus would then resolve any deadlock states), the recovery device comprising:
a recovery block that generates and transmits a deadlock occurrence signal when a deadlock in a system occurs; ([0042] when a CPU is in a looped condition – i.e, a deadlock – a signal -- i.e, a deadlock occurrence signal -- is sent to the service processor to perform a hardware reset)
a deadlock manager block that transmits an interrupt and …; and ([0018] service processor sends the interrupt)
a central processing unit (CPU) operably coupled to … and configured to receive the interrupt from the deadlock manager block and clear the interrupt in an operational state,
([0019] the service processor sends a hardware interrupt signal to the CPU. The interrupt signal re-sets the CPU to take it tout of the error loop so that it may resume normal operations – i.e., “clear the interrupt in an operational state.” )
wherein the deadlock manager block comprises:
a deadlock information module configured to collect occurrence locations and an order of deadlock occurrences of the deadlock transmitted from the recovery block; and ( [0019] the dedicated service processor executes a poll to a memory location in the partition manager called a heartbeat area which contains time stamped information detailing the run state condition of a plurality of the CPU. Since this collection of information, as well as further processing is used during the recovery processing, this heartbeat area can be considered a recovery block. [0032] the collected information includes “a physical processor identification (ID) – i.e., “occurrence locations”)
a deadlock clear module configured to transmit a deadlock resolution command in the order of deadlock occurrences, ( [0042] if the looping condition is identified in a particular CPU indicating its deadlocked status, a hardware reset command – i.e, “a deadlock resolution command” – is sent to reset that particular CPU)
transmits the deadlock resolution command configured to transmit in the order of deadlock occurrences of the occurrence locations to the recovery block ( [0045] the heartbeat data is read in the first-in-first-out (FIFO) manner – i.e, “in the order of deadlock occurrences” – and will be dealt with accordingly by the heartbeat area using the comparison method described in [0042]).
Although Armstrong fails to teach a system bus
Zhang teaches a system bus (page 748, second paragraph, system bus).
It would have been obvious to a person of ordinary skill in the art to combine the teaching from Zhang to incorporate the use of system bus to connect the various components since the bus would offer a predictable functionality of connecting all the processors in the embedded control system (Zhang, page 748, second paragraph).
Armstrong in view of Zhang fails to teach
operates an internal timer to wait for a particular operation to be completed, upon receiving the deadlock occurrence signal from the recovery block
wherein the deadlock manager block determines that the CPU is in a deadlock when the internal timer expires
when the deadlock resolution command is received, the recovery block resolves a deadlock of a corresponding interface associated with the deadlock resolution command and controls a corresponding function block associated with the deadlock resolution command to be isolated from the system bus.
However, Gass teaches
operates an internal timer to wait for a particular operation to be completed, upon receiving the deadlock occurrence signal from the recovery block (col 2 line 66-col 3 line 7, once a fault is detected, an interrupt is sent to the processor which starts the timer)
wherein the deadlock manager block determines that the CPU is in a deadlock when the internal timer expires (col 2 line 66-col 3 line 7, if the fault does not impair the capability of the processor, the processor will reset the timer before the timer times out. However, if the timer expires, it is determined that the CPU is in a deadlock)
when the deadlock resolution command is received, the recovery block resolves a deadlock of a corresponding interface associated with the deadlock resolution command and controls a corresponding function block associated with the deadlock resolution command to be isolated from the system bus. (Gass, col 2 line 66- col 3 line 7, power is cut off from the CPU if the deadlock is not resolved)
It would have been obvious to a person of ordinary skill in the art prior to the effective filing date of the claimed invention to incorporate Gass’s teaching with that of Armstrong in view of Zhang because it would have a predictable result of not responding to noise instead of the actual issues (Gass, col 5 lines 35-40). Furthermore, it would have been obvious to a person of ordinary skill in the art prior to the effective filing date of the claimed invention to incorporate Gass’ teaching in order to teach that the deadlock resolution command is used to isolate the functional component from the system bus (Gass, col 2 line 66-col 3 line 7) because by doing so it yields a predictable result of isolating the faulty component.
Armstrong in view of Zhang in view of Gass fails to teach
a vehicle
However, Woo teaches
a vehicle ([0083] a block diagram illustrating an autonomous vehicle including an SoC, according to an example embodiment)
It would have been obvious to a person of ordinary skill in the art to combine the teaching of Armstrong in view of Zhang in view of Gass with the teaching of Woo in order to teach that that this resolution of deadlocked state can be implemented in the vehicle because autonomous cars contain system-on-chips that may involve deadlocked states (Woo [0022]-[0023]).
Per claim 7,
Armstrong in view of Zhang in view of Gass in view of Woo teaches
(Original) The recovery device of claim 1, wherein the recovery block is a master recovery block operably connected to a particular master block among a plurality of master blocks, and (Armstrong, FIG. 1, the partition manager and the service processor is used in the recovery process and can be reconsidered a recovery block. It is connected to the main master block which is represented by the partitions)
the master recovery block is operably coupled to the particular master block through a command channel via which a command is received from the particular master block and a response channel via which a response is transmitted to the particular master block. (Armstrong, FIG. 1, [0037] each CPU processes data and periodically stores data in the array structure in the heart beat area of the partition manager – since this represents a communication channel of outgoing messages from the master block, it represents the command channel. [0042] if any of the CPU is in a looped condition, the hardware reset request is sent by the service processor – this represents the incoming messages to the master block, i.e, response channel)
Claim 14 is/are rejected under 35 U.S.C. 103 as being unpatentable over Armstrong in view of Gass in view of Woo.
Per claim 14,
(Currently Amended) A recovery method for resolving a system deadlock in …, the recovery method comprising ([0018] “an apparatus for monitoring the state of a computer system running multiple operating systems controlled by a partition manager;” wherein, monitoring the state may include deadlock states. The apparatus would then resolve any deadlock states):
a deadlock monitoring process of, by a recovery block, monitoring occurrence of a deadlock in a system; ([0037]-[0042] a heartbeat data is collected from each CPU in order to detect any looping condition – i.e, a deadlock)
…
a deadlock occurrence information collection process of collecting occurrence locations and an order of deadlock occurrences of the deadlock transmitted from the recovery block: ([0045] the heartbeat data is read and processed by the recovery block in a first-in-first-out (FIFO) manner – i.e, in an order of deadlock occurrence; [0032] the heartbeat data includes the physical processor ID – i.e, occurrence location)
a deadlock occurrence signal transmission process of, by the recovery block, generating and transmitting a deadlock occurrence signal when the deadlock in the system occurs; ([0042] when a CPU is in a looped condition – i.e, a deadlock – a signal -- i.e, a deadlock occurrence signal -- is sent to the service processor to perform a hardware reset)
an interrupt transmission process of, by the deadlock manager block, transmitting an interrupt to a central processing unit (CPU), upon receiving the deadlock occurrence signal from the recovery block; ([0018] service processor sends the interrupt to the deadlock occurrence location – i.e, a CPU)
.., and transmitting the deadlock resolution command configured to transmit in the order of deadlock occurrences of the occurrence locations to the recovery block; and ([0045] the heartbeat data is read and processed by the recovery block in a first-in-first-out (FIFO) manner – i.e, in an order of deadlock occurrence; [0032] the heartbeat data includes the physical processor ID – i.e, occurrence location)
a deadlock resolving process of, by the recovery block, resolving a deadlock of a corresponding interface associated with the deadlock resolution command upon receiving the deadlock resolution command ([0019] the service processor sends a hardware interrupt signal to the CPU. The interrupt signal re-sets the CPU to take it tout of the error loop so that it may resume normal operations – i.e., “clear the interrupt in an operational state.” ), ….
Although Armstrong fails to teach
a deadlock determination process of, by a deadlock manager block, receiving a signal of the deadlock occurrence from the recovery block and determining whether the deadlock has occurred in the system;
a deadlock resolution command transmission process of, by the deadlock manager block, determining that the CPU is in a deadlock when an internal timer expires,
controlling a corresponding function block associated with the deadlock resolution command to be isolated from the system bus.
Gass teaches
a deadlock determination process of, by a deadlock manager block, receiving a signal of the deadlock occurrence from the recovery block and determining whether the deadlock has occurred in the system; (col 2 line 66-col 3 line 7, determines whether the CPU deadlock has occurred by waiting for the expiration of the internal timer)
a deadlock resolution command transmission process of, by the deadlock manager block, determining that the CPU is in a deadlock when an internal timer expires, (col 2 line 66-col 3 line 7, determines whether the CPU deadlock has occurred by waiting for the expiration of the internal timer)
controlling a corresponding function block associated with the deadlock resolution command to be isolated from the system bus. (Gass, col 2 line 66- col 3 line 7, power is cut off from the CPU if the deadlock is not resolved)
It would have been obvious to a person of ordinary skill in the art prior to the effective filing date of the claimed invention to incorporate Gass’s teaching with that of Armstrong because it would have a predictable result of not responding to noise instead of the actual issues (Gass, col 5 lines 35-40). Furthermore, it would have been obvious to a person of ordinary skill in the art prior to the effective filing date of the claimed invention to incorporate Gass’ teaching in order to teach that the deadlock resolution command is used to isolate the functional component from the system bus (Gass, col 2 line 66-col 3 line 7) because by doing so it yields a predictable result of isolating the faulty component.
Although Armstrong in view of Gass fails to teach
a vehicle
Woo teaches a vehicle ([0083] a block diagram illustrating an autonomous vehicle including an SoC, according to an example embodiment)
It would have been obvious to a person of ordinary skill in the art to combine the teaching of Armstrong in view of Gass with the teaching of Woo in order to teach that that this resolution of deadlocked state can be implemented in the vehicle because autonomous cars contain system-on-chips that may involve deadlocked states (Woo [0022]-[0023]).
Allowable Subject Matter
If claims 2-6, 8-13, 15-20 are rewritten in independent form and further amended to overcome any pending 35 U.S.C. 112(b) rejections, the claims would be in an allowable form.
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure.
Tomlin et al (US 20190079824 A1) teaches a system with an error queue manager configured to receive an error message from at least one of the plurality of hardware blocks, and using the command identifier, identify and keep track of the location of the errors and perform operations to resolve said error.
Contact Information
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/K.L.R./Examiner, Art Unit 2114
/ASHISH THOMAS/Supervisory Patent Examiner, Art Unit 2114
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