DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Information Disclosure Statement
The information disclosure statement (IDS) document submitted on April 17, 2025 is in compliance with the provisions of 37 CFR 1.97. Accordingly, the information disclosure statement is being considered by the examiner.
Priority
Acknowledgment is made of applicant's claim for foreign priority under 35 U.S.C. 119(a)-(d). Receipt is acknowledged of papers submitted under 35 U.S.C. 119(a)-(d), which papers have been placed of record in the file.
Claim Interpretation - 35 USC § 112
The following is a quotation of 35 U.S.C. 112(f):
(f) Element in Claim for a Combination. – An element in a claim for a combination may be expressed as a means or step for performing a specified function without the recital of structure, material, or acts in support thereof, and such claim shall be construed to cover the corresponding structure, material, or acts described in the specification and equivalents thereof.
The following is a quotation of pre-AIA 35 U.S.C. 112, sixth paragraph:
An element in a claim for a combination may be expressed as a means or step for performing a specified function without the recital of structure, material, or acts in support thereof, and such claim shall be construed to cover the corresponding structure, material, or acts described in the specification and equivalents thereof.
The claims in this application are given their broadest reasonable interpretation using the plain meaning of the claim language in light of the specification as it would be understood by one of ordinary skill in the art. The broadest reasonable interpretation of a claim element (also commonly referred to as a claim limitation) is limited by the description in the specification when 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph, is invoked.
As explained in MPEP § 2181, subsection I, claim limitations that meet the following three-prong test will be interpreted under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph:
(A) the claim limitation uses the term “means” or “step” or a term used as a substitute for “means” that is a generic placeholder (also called a nonce term or a non-structural term having no specific structural meaning) for performing the claimed function;
(B) the term “means” or “step” or the generic placeholder is modified by functional language, typically, but not always linked by the transition word “for” (e.g., “means for”) or another linking word or phrase, such as “configured to” or “so that”; and
(C) the term “means” or “step” or the generic placeholder is not modified by sufficient structure, material, or acts for performing the claimed function.
Use of the word “means” (or “step”) in a claim with functional language creates a rebuttable presumption that the claim limitation is to be treated in accordance with 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph. The presumption that the claim limitation is interpreted under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph, is rebutted when the claim limitation recites sufficient structure, material, or acts to entirely perform the recited function.
Absence of the word “means” (or “step”) in a claim creates a rebuttable presumption that the claim limitation is not to be treated in accordance with 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph. The presumption that the claim limitation is not interpreted under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph, is rebutted when the claim limitation recites function without reciting sufficient structure, material or acts to entirely perform the recited function.
Claim limitations in this application that use the word “means” (or “step”) are being interpreted under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph, except as otherwise indicated in an Office action. Conversely, claim limitations in this application that do not use the word “means” (or “step”) are not being interpreted under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph, except as otherwise indicated in an Office action.
This application includes one or more claim limitations that use the word “unit” or “element” are being interpreted under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph, because the claim limitation(s) uses a generic placeholder that is coupled with functional language without reciting sufficient structure to perform the recited function and the generic placeholder is not preceded by a structural modifier. Such claim limitation(s) is/are: “a light receiving element configured to …” in claim 1, claim 17, selection pulse generation unit configured to …” in claim 11 and claim 12, “arithmetic processing unit configured to…” in claim 13, “ the arithmetic processing unit obtains….” in claim 14.
Because this/these claim limitation(s) is/are being interpreted under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph, it/they is/are being interpreted to cover the corresponding structure described in the specification as performing the claimed function, and equivalents thereof.
If applicant does not intend to have this/these limitation(s) interpreted under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph, applicant may: (1) amend the claim limitation(s) to avoid it/them being interpreted under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph (e.g., by reciting sufficient structure to perform the claimed function); or (2) present a sufficient showing that the claim limitation(s) recite(s) sufficient structure to perform the claimed function so as to avoid it/them being interpreted under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph.
Claims 2-10 are also being are being interpreted under 35 U.S.C. 112(f) or pre AIA 35 U.S.C. 112, sixth paragraph as being dependent from claim 1.
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claim(s) 1, 2,5, 6,7,9,10,11, 12,13,15,16,17 is/are rejected under 35 U.S.C. 102 (a)(1) as being anticipated by Kobayashi et al. (US Pub. No.: US 2019/0068908 A1).
Regarding claim 1, Kobayashi discloses an imaging element (Para 28; solid-state image sensor 100) comprising: a light receiving element (Para 30; SPAD 111) configured to detect a presence or absence of a photon (Para 31; if a single photon is incident on the SPAD 111, the pulse signal PLS is output from the inverter 113 with a frequency that corresponds to the reception frequency of a single photon. Para 33; the number of pulses of the clock signal CLK is counted by counter 114), the light receiving element being provided for each pixel (Para 30; SPAD 111; Each pixel 110 is provided with a SPAD 111, a quenching element 112, an inverter 113, a counter 114);
and a detection circuit configured to detect a photon incident on the light receiving element (Para 30-33; if a single photon is incident on the SPAD 111, the pulse signal PLS is output from the inverter 113 with a frequency that corresponds to the reception frequency of a single photon. Para 33; the number of pulses of the clock signal CLK is counted by counter 114),
the detection circuit being provided corresponding to the light receiving element (Para 30; counter 114; Each pixel 110 is provided with a SPAD 111, a quenching element 112, an inverter 113, a counter 114),
wherein the detection circuit includes a photon detection unit configured to detect a photon incident on the light receiving element by recharge control with a plurality of periods with respect to the light receiving element (Para 31-33; A bias voltage Vbias is applied to the other end of the quenching element 112. A bias voltage Vbias that is greater than a breakdown voltage of the SPAD 111 is applied to the SPAD 111 via the quenching element 112. Thus, the SPAD 111 operates in a Geiger mode. That is to say, an avalanche multiplication phenomenon is caused if a single photon is incident on the SPAD 111. As a result, an avalanche current is generated, and a voltage drop occurs in the quenching element 112. The quenching element 112 is a resistor element for stopping the avalanche multiplication phenomenon that occurs at the SPAD 111. If a single photon is incident on the SPAD 111, the aforementioned phenomenon occurs, and thus, the voltage changes at the node PLSa. The inverter 113 generates a pulse signal PLS in accordance with a voltage change at the node PLSa, and outputs the generated pulse signal PLS to the node PLSd. Thus, a pulse signal PLS whose waveform has been shaped is output from the inverter 113. Thus, in a sensor unit 303 (see FIGS. 3A and 3B), if a single photon is incident on the SPAD 111, the pulse signal PLS is output from the inverter 113 with a frequency that corresponds to the reception frequency of a single photon. If the input selection switch 115 is set so that the clock signal CLK is provided to the input terminal of the counter 114, the number of pulses of the clock signal CLK is counted by the counter 114.).
a plurality of storage units ( Para 30; memories 116) , and a selection control unit (Para 42; switch 121) configured to select one of the plurality of storage units as a storage unit configured to store a number of detected photons detected by the photon detection unit (Para 42; Upon the transfer switch 121 entering the ON state, the count value of the counter 114 is transferred to the pixel memory 116. The pixel memory 116 temporarily stores the count value provided from the counter 114. By causing the readout switch 122 to enter the ON state).
Regarding claim 2, Kobayashi discloses the imaging element according to claim 1, wherein the detection circuit further includes a counter (Para 33, 38; counter 114 ; If the input selection switch 115 is set so that the clock signal CLK is provided to the input terminal of the counter 114, the number of pulses of the clock signal CLK is counted by the counter 114.) configured to count a pulse generated when the photon detection unit detects a photon, the plurality of storage units is constructed by utilizing memories (Para 30; pixel memory 116), each storing a count value of the counter, and the selection control unit is disposed between the counter and the plurality of storage units ( Para 42; switches 121, Fig.3B; wherein it is located between counter and memory 116) , and performs a control to selectively input the count value of the counter to the plurality of storage units (Para 42; Upon the transfer switch 121 entering the ON state, the count value of the counter 114 is transferred to the pixel memory 116.).
Regarding claim 5, Kobayashi discloses The imaging element according to claim 4, wherein each counter of the plurality of storage units repeats a period in which a counting operation is performed and a period in which a counting operation is not performed a plurality of times (Para 30-40; An enable signal ENABLE for controlling whether or not to cause the counter 114 to operate is provided to an enable terminal of the counter 114 from the timing generator 102 via the AND element 118. The enable signal ENABLE is input to one input terminal of the AND element 118. The counter 114 performs a counting operation if the enable terminal of the counter 114 is at the High level, and the counter 114 stops the counting operation if the enable terminal of the counter 114 is at the Low level).
Regarding claim 6, Kobayashi discloses The imaging element according to claim 1, wherein the selection control unit performs an operation of selecting one of the plurality of storage units in synchronization with switching of a period of the recharge control (Para 42; The transfer switch 121 enters the ON state when the control pulse MEM is switched to the High level. Upon the transfer switch 121 entering the ON state, the count value of the counter 114 is transferred to the pixel memory 116. The pixel memory 116 temporarily stores the count value provided from the counter 114. By causing the readout switch 122 to enter the ON state, the count value stored in the pixel memory 116 is written in the column memory 103 via a signal line 105.).
Regarding claim 7, Kobayashi discloses The imaging element according to claim 6, wherein the selection control unit generates a selection pulse for selecting one of the plurality of storage units, and the photon detection unit performs the recharge control with the plurality of periods in synchronization with the selection pulse (Para 50; At timing t204, which is a timing immediately before timing t205, the control pulse MEM is switched to the High level. Upon the control pulse MEM being switched to the High level, the transfer switch 121 enters the ON state, and the count value of the counter 114 is stored in the pixel memory 116. Accordingly, the number of pulses of the pulse signal PLS that is counted from timing t203 until timing t204 serves the imaging count value.).
Regarding claim 9, Kobayashi discloses The imaging element according to claim 6, wherein the detection circuit further includes a recharge period switching control unit configured to switch the period of the recharge control (Para 31; The inverter 113 generates a pulse signal PLS in accordance with a voltage change at the node PLSa, and outputs the generated pulse signal PLS to the node PLSd. Thus, a pulse signal PLS whose waveform has been shaped is output from the inverter 11), and the photon detection unit generates a selection pulse for selecting one of the plurality of storage units on a basis of a switching signal output from the recharge period switching control unit (Para 42; The transfer switch 121 enters the ON state when the control pulse MEM is switched to the High level. Upon the transfer switch 121 entering the ON state, the count value of the counter 114 is transferred to the pixel memory 116. The pixel memory 116 temporarily stores the count value provided from the counter 114. By causing the readout switch 122 to enter the ON state, the count value stored in the pixel memory 116 is written in the column memory 103 via a signal line 105.).
Regarding claim 10, Kobayashi discloses The imaging element according to claim 1, wherein the imaging element has a stacked structure in which at least two semiconductor substrates are stacked ( Para 59; Figs.3A ,3B; stacking two substrates 301 and 302 ) , the at least two semiconductor substrates including a first semiconductor substrate on which the light receiving element is formed (Para 60; the solid-state image sensor 100 is constituted by a substrate (upper substrate) 301 for receiving an optical image formed by the optical system 401) and a second semiconductor substrate on which the detection circuit is formed (Para 60; a substrate (lower substrate) 302 that mainly includes a digital circuit.).
Regarding claim 11, Kobayashi discloses The imaging element according to claim 10, wherein the imaging element further comprises a selection pulse generation unit (Para 35; NAND element 117) configured to generate a selection pulse for selecting one of the plurality of storage units (Para 35; Only when the enable signal ENABLE is at the High level, and the output of the NAND element 117 is at the High level, the output of the AND element 118 is at the High level, and the counter 114 performs the counting operation), and
the selection pulse generation unit is disposed on the second semiconductor substrate outside a pixel array unit in which the detection circuits are disposed in an array (Fig. 3B; wherein NAND element 117 is disposed on substrate 302).
Regarding claim 12, Kobayashi discloses The imaging element according to claim 10, wherein the imaging element further comprises a selection pulse generation unit (Para 35; NAND element 117) configured to generate a selection pulse for selecting one of the plurality of storage units ( Para 35; Only when the enable signal ENABLE is at the High level, and the output of the NAND element 117 is at the High level, the output of the AND element 118 is at the High level, and the counter 114 performs the counting operation) , and
the selection pulse generation unit is disposed on the second semiconductor substrate inside a pixel array unit in which the detection circuits are disposed in an array (Fig. 3B; wherein NAND element 117 is disposed on substrate 304), and the
selection pulse generation unit is disposed to form a pair with each detection circuit (Fig. 3B; wherein each counting unit in the pixel includes one NAND element 117).
Regarding claim 13, Kobayashi discloses the imaging element according to claim 1, wherein the imaging element further comprises an arithmetic processing unit configured to obtain an image output on a basis of each output value of the plurality of storage units ( Para 42-51; The count value stored in the pixel memory 116 is written in the column memory 103 via a signal line 105. pixel signal values held by the column memory 103 are sequentially output to the signal processing unit 402 via the output line Output.).
Regarding claim 15, Kobayashi discloses the imaging element according to claim 1, wherein the light receiving element is an avalanche photodiode (Para 30; SPAD 111).
Regarding claim 16, Kobayashi discloses the imaging element according to claim 15, wherein the light receiving element is a single photon avalanche diode (Para 30; SPAD 111 (Single Photon Avalanche Diode).
Regarding claim 17, Kobayashi discloses an electronic apparatus (Para 28; solid-state image sensor 100) comprising an imaging element (Figs. 3A, 3B; Para 59; two substrates (semiconductor chips) 301 and 302 ) , wherein the imaging element includes:
a light receiving element (Para 30; SPAD 111 ) configured to detect a presence or absence of a photon (Para 31; if a single photon is incident on the SPAD 111, the pulse signal PLS is output from the inverter 113 with a frequency that corresponds to the reception frequency of a single photon. Para 33; the number of pulses of the clock signal CLK is counted by counter 114), the light receiving element being provided for each pixel (Para 30; SPAD 111; Each pixel 110 is provided with a SPAD 111, a quenching element 112, an inverter 113, a counter 114); and
a detection circuit (Para 30-33; if a single photon is incident on the SPAD 111, the pulse signal PLS is output from the inverter 113 with a frequency that corresponds to the reception frequency of a single photon. Para 33; the number of pulses of the clock signal CLK is counted by counter 114) configured to detect a photon incident on the light receiving element,
the detection circuit (Para 30; counter 114; Each pixel 110 is provided with a SPAD 111, a quenching element 112, an inverter 113, a counter 114) being provided corresponding to the light receiving element,
the detection circuit including a photon detection unit configured to detect a photon
incident on the light receiving element by recharge control with a plurality of periods with respect to the light receiving element (Para 31-33; A bias voltage Vbias is applied to the other end of the quenching element 112. A bias voltage Vbias that is greater than a breakdown voltage of the SPAD 111 is applied to the SPAD 111 via the quenching element 112. Thus, the SPAD 111 operates in a Geiger mode. That is to say, an avalanche multiplication phenomenon is caused if a single photon is incident on the SPAD 111. As a result, an avalanche current is generated, and a voltage drop occurs in the quenching element 112. The quenching element 112 is a resistor element for stopping the avalanche multiplication phenomenon that occurs at the SPAD 111. If a single photon is incident on the SPAD 111, the aforementioned phenomenon occurs, and thus, the voltage changes at the node PLSa. The inverter 113 generates a pulse signal PLS in accordance with a voltage change at the node PLSa, and outputs the generated pulse signal PLS to the node PLSd. Thus, a pulse signal PLS whose waveform has been shaped is output from the inverter 113. Thus, in a sensor unit 303 (see FIGS. 3A and 3B), if a single photon is incident on the SPAD 111, the pulse signal PLS is output from the inverter 113 with a frequency that corresponds to the reception frequency of a single photon. If the input selection switch 115 is set so that the clock signal CLK is provided to the input terminal of the counter 114, the number of pulses of the clock signal CLK is counted by the counter 114),
a plurality of storage units (Para 30; memories 116), and a selection control unit (Para 42; switch 121) configured to select one of the plurality of storage units as a storage unit configured to store a number of detected photons detected by the photon detection unit (Para 42; Upon the transfer switch 121 entering the ON state, the count value of the counter 114 is transferred to the pixel memory 116. The pixel memory 116 temporarily stores the count value provided from the counter 114. By causing the readout switch 122 to enter the ON state).
Allowable Subject Matter
3. Claims 3,4,8, and 14 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
The following is a statement of reasons for the indication of allowable subject matter:
Regarding claim 3, Kobayashi discloses The imaging element according to claim 2, wherein the detection circuit further includes a read control unit (Para 42; readout switch 122 to enter the ON state, the count value stored in the pixel memory 116 is written in the column memory 103 via a signal line 105.).
However, the prior art does not disclose wherein the detection circuit further includes a read control unit configured to read, during a hold period of one storage unit of the plurality of storage units, a hold value of another storage unit.
Regarding claim 4, Kobayashi discloses the plurality of storage units (Para 42; memory 116).
However, Kobayashi does not disclose “the plurality of storage units are constructed by utilizing counters, each counting a pulse generated when the photon detection unit detects a photon, and the selection control unit is disposed between the photon detection unit and the plurality of storage units, and performs a control to selectively input the number of detected photons to the plurality of storage units” in combination of other limitation in the claim.
Regarding claim 8, Kobayashi discloses the detection circuit (Para 30-33; if a single photon is incident on the SPAD 111, the pulse signal PLS is output from the inverter 113 with a frequency that corresponds to the reception frequency of a single photon. Para 33; the number of pulses of the clock signal CLK is counted by counter 114).
However, the prior art does not disclose The imaging element according to claim 6, wherein the detection circuit further includes a recharge period switching control unit configured to switch the period of the recharge control, and the selection control unit generates a selection pulse for selecting one of the plurality of storage units in synchronization with a switching signal output from the recharge period switching control unit.
Regarding claim 14, Kobayashi discloses the arithmetic processing unit (Para 42-51; The count value stored in the pixel memory 116 is written in the column memory 103 via a signal line 105. pixel signal values held by the column memory 103 are sequentially output to the signal processing unit 402 via the output line Output.).
However, the prior art does not disclose the arithmetic processing unit obtains incident illuminance in a plurality of exposure periods from each output value of the plurality of storage units, and obtains average illuminance of the incident illuminance in the plurality of exposure periods.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to XI WANG whose telephone number is (469)295-9155. The examiner can normally be reached on 9:00 am-5:00 pm.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, SINH TRAN can be reached on 571-272-7564. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/XI WANG/ Primary Examiner, Art Unit 2637
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