DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Priority
Acknowledgment is made of applicant’s claim for foreign priority under 35 U.S.C. 119 (a)-(d). Receipt is acknowledged of certified copies of papers required by 37 CFR 1.55.
Information Disclosure Statement
The information disclosure statement(s) (IDS) submitted 4/18/2025 is/are in compliance with the provisions of 37 CFR 1.97 and being considered by the examiner.
Specification
The disclosure is objected to because of the following informalities:
The headings of the parts of the description (Title of the Invention, Technical Field and so on) should not be in brackets. MPEP 204.
Appropriate correction is required.
Claim Objections
Claim 1, line 4, recites “target capacitor”, should be--a target capacitor--.
Claim 1, lines 17-18, and claim 5, line 2, recite “the capacitance of the junction capacitor”, should be-- the junction capacitance
Appropriate correction is required.
Claim Rejections - 35 USC § 112(b)
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
Claims 1-13 are rejected under 35 U.S.C. 112(b) as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor, or a joint inventor, regards as the invention.
Claim 1, line 6, there is insufficient antecedent basis for the term “the capacitor” and it is unclear whether it refers to a target capacitor or an adjustment capacitor.
For examination purposes, this term will be understood to mean “the target capacitor.” A similar correction must be made in claim 3, line 1; claim 6, line 2; claim 7, line 5; claim 8, line 3; claim 12, line 3.
Claim 1, line 16, there is insufficient antecedent basis for the term “the legs.” For examination purposes, this term will be understood to mean “the unit leg.”
Claim 10, line 1, and claim 11, line 11, there is insufficient antecedent basis for the term “the adjustment capacitors.” For examination purposes, this term will be understood to mean “a plurality of adjustment capacitors.”
Claims 2-13 are also rejected under 35 U.S.C. 112(b) as dependent on the rejected claim(s).
Appropriate correction is required.
Claim Rejections - 35 USC § 112(d)
The following is a quotation of 35 U.S.C. 112(d):
(d) REFERENCE IN DEPENDENT FORMS.—Subject to subsection (e), a claim in dependent form shall contain a reference to a claim previously set forth and then specify a further limitation of the subject matter claimed. A claim in dependent form shall be construed to incorporate by reference all the limitations of the claim to which it refers.
Claim 5 is rejected under 35 U.S.C. 112(d), as being of improper dependent form for failing to further limit the subject matter of the claim upon which it depends, or for failing to include all the limitations of the claim upon which it depends.
Claim 5 fails to further limit the subject matter of claim 1 because it recites “wherein the capacitance of the adjustment capacitor is at least 5 times greater than the capacitance of the junction capacitor,” which is already recited in claim 1.
Applicant may cancel the claim(s), amend the claim(s) to place the claim(s) in proper dependent form, rewrite the claim(s) in independent form, or present a sufficient showing that the dependent claim(s) complies with the statutory requirements.
For examination purposes, this claim will be understood to mean “wherein the capacitance of the adjustment capacitor is at least [[5]] 7 times greater than the junction capacitance.” See Specification, p. 3, line 6.
Appropriate correction is required.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
This application currently names joint inventors. In considering patentability of the claims the examiner presumes that the subject matter of the various claims was commonly owned as of the effective filing date of the claimed invention(s) absent any evidence to the contrary. Applicant is advised of the obligation under 37 CFR 1.56 to point out the inventor and effective filing dates of each claim that was not commonly owned as of the effective filing date of the later invention in order for the examiner to consider the applicability of 35 U.S.C. 102(b)(2)(C) for any potential 35 U.S.C. 102(a)(2) prior art against the later invention.
Claims 1, 3-13 are rejected under 35 U.S.C. 103 as being unpatentable over U.S. Patent Application Publication No. 2020/0144032, published 5/7/2020 (“Ulrich”), cited by the applicant.
Regarding Claims 1, 3, 5-9, 12-13 (as best understood), Ulrich discloses in Figs. 1, 16, 20, 24C, 37B, 41-42 and the corresponding description:
An impedance adjustment circuit configured to adjust an impedance by adjusting an equivalent capacitance (Abstract, Figs. 16, 20; ¶7, 172-188; impedance matching network), the impedance adjustment circuit comprising:
a unit leg (Fig. 20, EVC 76 of impedance matching network 90B), configured to adjust the equivalent capacitance according to a connection with a target capacitor (discrete capacitor 78 of each EVC 76 of impedance matching network 90B represented by C1 in Fig. 1 or the capacitance of the plasma chamber 21) the unit leg comprises:
an adjustment capacitor (62B) having one electrode connected to a reference voltage rail (Ground) and connected to the [target] capacitor equivalently to adjust the equivalent capacitance,
a leg voltage source (HVDC bias source 67B),
two switches connected in series with the leg voltage source (two switches of Driver Circuit 66B),
a first inductor (64B) having one electrode connected to a node where the two switches are connected and the other electrode connected to the other electrode of the adjustment capacitor (Fig. 20), and
a diode (D1, PIN diode 65) having an anode connected to an RF rail (via capacitor 78), an RF voltage is provided to the anode and a cathode connected to the other electrode of the first inductor (64B), and a junction capacitance is formed between the anode and the cathode (¶¶172-173),
a control unit (Fig. 16, control unit 85) that controls the [unit leg] so that the above equivalent capacitance changes (¶¶137-138, control unit 85 controls driver circuits in all disclosed embodiments),
wherein a capacitance of the adjustment capacitor is at least 5 times greater than the capacitance of the junction capacitor (¶178, diode 65 has capacitance of 2.5 pF and capacitor 62B has capacitance of 442 pF, that is, more than 170 times greater).
Fig. 20 of Ulrich does not show a parallel inductor connected in parallel with said unit leg. However, Ulrich does disclose such parallel inductors (Figs. 24C, 37B, 41-42).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the impedance matching circuit of Fig. 20 of Ulrich by adding a parallel inductor disclosed in Figs. 24C, 37B, 41-42 of Ulrich as a blocking choke for the benefit of filtering out DC voltage and RF isolation, as taught by Ulrich (¶¶286, 300, 307).
Regarding Claim 4, Ulrich discloses wherein a voltage provided by the leg voltage source is greater in magnitude than the RF voltage provided to the RF rail (¶290, “The maximum RF voltage that can be applied is less than or equal to the HVDC bias”).
Regarding Claims 10-11 (as best understood), Ulrich does not explicitly disclose “wherein the adjustment capacitors included in the plurality of unit legs have different [claim 10] or same [claim 11] capacitances.” However, Ulrich discloses that the adjustment capacitor may range from 442 pF to 470 pF (¶178) and also teaches that the capacitances of the adjustment capacitors are design parameters that can be set as desired for controlling the capacitance of each EVC unit leg 76 (¶¶7, 172-173). In addition, the capacitance of the adjustment capacitors may be set (same, greater or different) as a result of optimization to achieve the desired characteristics, as well known in the art. MPEP 2144.05(II)(A).
Allowable Subject Matter
Claim 2 would be allowable if rewritten to overcome the rejection(s) under 35 U.S.C. 112(b) set forth in this Office action and to include all of the limitations of the base claim(s) and any intervening claims.
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure.
U.S. Patent Application Publication No. 2013/0207738 (“Mason”) discloses an impedance matching circuit including PIN diodes and DC bias voltage sources 524 and 528 assisting in turning the diodes off (thus increasing switching speed) and in replenishing charge on the body capacitance of the switching transistor that is lost to leakage current (Fig. 5, ¶¶ 58-68).
The PIN Diode Circuit Designers' Handbook, Microsemi Corp., 1998, teaches using an inductor to isolate the DC bias source and the RF circuit (p. 7) and discloses a DC bias source feeding a PIN diode through an RF choke (Fig. 2.11).
Any inquiry concerning this communication or earlier communications from the examiner should be directed to VICTOR COLE, telephone number (571) 272-4686. The examiner can be reached Monday-Friday, 9AM-5PM ET.
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If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, ANDREA LINDGREN BALTZELL, can be reached at (571) 272-5918. The fax phone number for the organization where this application or proceeding is assigned is (571) 273-8300.
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/VICTOR COLE/
Examiner, Art Unit 2843
/ANDREA LINDGREN BALTZELL/Supervisory Patent Examiner, Art Unit 2843
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