Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Response to Amendment
The amendment filed June 21st, 2026 does not place the application in condition for allowance.
The 112(b) rejection of claim 4 has been withdrawn due to Applicant’s amendment.
The rejections over Chen et al. are maintained.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
Claims 1-5, 8, and 10-14 are rejected under 35 U.S.C. 103 as being unpatentable over Chen et al. (US 2023/0027636 A1) in view of Wang (CN-115692544-A). Wang is mapped to the English machine translation provided by the EPO.
In view of Claim 1, Chen et al. teaches a method for manufacturing a back contact solar cell (Fig. 8 – Paragraph 0094 & 0085); comprising:
a back face of a silicon wafer having a first region and a second region (See Annotated Chen et al. Fig. 8, below);
depositing a tunneling layer in the first region on the back face of the silicon wafer and forming a porous lattice in the tunneling layer located in the first region on the back face of the silicon wafer (Figs 1 & 8, #12 – Paragraph 0077-0078);
forming a doped polysilicon layer on a surface of the tunneling layer away from the silicon wafer (Fig. 8, #20 the portion “below” #12).
Chen et al. does not disclose that wherein a doping concentration in the doped polysilicon layer gradually decreases in a direction away from the tunneling layer.
Wang discloses a doping concentration in a doped polysilicon layer gradually decreases in a direction away from a tunneling layer (Page 5, Lines 20-45 - Example 2, see steps S2 & S3, S2 a tunneling layer is deposited, S3 doped amorphous silicon is heavily doped closer to the tunneling layer and gradually decreases shown in Fig. 1). Wang discloses that this doping configuration can improve the tunneling current, improve the contact ability, can effectively reduce the Auger recombination and reduce parasitic absorption of the polysilicon long-wave band (Page 5, Lines 40-46). Accordingly, it would have been obvious to one of ordinary skill in the art at the time the invention was filed to adopt Wang’s doping strategy and having the doping concentration in the doped polysilicon layer gradually decreases in a direction away from the tunneling layer in Chen et al. method of manufacturing a back contact solar cell for the advantages of improving the tunneling current, improving the contact ability, effectively reducing the Auger recombination and reducing parasitic absorption of the polysilicon long-wave band.
Annotated Chen et al. Fig. 8
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In view of Claim 2, Chen et al. and Wang are relied upon for the reasons given above in addressing Claim 1. Chen et al. teaches that when forming the porous lattice in the tunneling layer located in the first region on the back face of the silicon wafer comprises etching the tunneling layer to form the porous lattice (Fig. 1, #12 – Paragraph 0078 – dry etching, and porous structure also has grooves/openings not extending through the layer).
In view of Claim 3, Chen et al. and Wang are relied upon for the reasons given above in addressing Claim 1. Chen et al. discloses that the forming the porous lattice in the tunneling layer located in the first region on the back face of the silicon wafer comprises etching the tunneling layer by corrosive solution containing an additive to form the porous lattice in the tunneling layer (Paragraph 0078 – chemical corrosion).
In view of Claim 4, Chen et al. and Wang are relied upon for the reasons given above in addressing Claim 1. Wang discloses forming the doped polysilicon layer on the surface of the tunneling layer away from the silicon wafer comprises: depositing an intrinsic polysilicon layer on the surface of the tunneling layer (Page 5, Lines 24-27); doping the intrinsic polysilicon by a plurality of heavy phosphorous doping to form the doped polysilicon layer (Page 5, Lines 30-39).
In view of Claim 5, Chen et al. and Wang are relied upon for the reasons given above in addressing Claim 1. Wang discloses a doping concentration of a region of the doped polysilicon layer adjacent to the tunneling layer is 4E20 atoms/cm3 and a doping concentration of a region of the doped polysilicon layer farthest from the tunneling layer is 1E20 atoms/cm3 (Page 6, Lines 29-33).
In regards to the limitation that, “a doping concentration of a region of the doped polysilicon layer adjacent to the tunneling layer is 1E20 atoms/cm3 to 6E20 atoms/cm3, a doping concentration of a region of the doped polysilicon layer farthest from the tunneling layer is 1E19 atoms/cm3 to 3E20 atoms/cm3”, the Examiner directs Applicant to MPEP 2144.05 I. In the case where the claimed ranges “overlap or lie inside ranges disclosed by the prior art” a prima facie case of obviousness exists. Accordingly, it would have been obvious to one of ordinary skill in the art to have selected the overlapping ranged disclosed by Wang because selection of the overlapping portion or ranges has been held to be a prima facie case of obviousness.
In view of Claim 8, Chen et al. and Wang are relied upon for the reasons given above in addressing Claim 1. Chen et al. teaches that before forming the porous lattice in the tunneling layer located in the first region on the back face of the silicon wafer that the method further comprises depositing the tunneling layer on the back surface of the wafer and that it comprises a silicon oxide or aluminum oxide layer (Paragraph 0020) or a silicon carbide layer (Paragraph 0018).
In view of Claim 10, Chen et al. teaches a back contact solar cell (Fig. 8 – Paragraph 0094 & 0085); comprising:
a back face of a silicon wafer having a first region and a second region (See Annotated Chen et al. Fig. 8, below);
a porous lattice in a tunneling layer located in the first region on the back face of the silicon wafer (Figs 1 & 8, #12 – Paragraph 0078);
a doped polysilicon layer on a surface of the tunneling layer away from the silicon wafer (Fig. 8, #20 the portion “below” #12);
the tunneling layer can be in direct contact with the back face of the silicon wafer at local areas of the silicon substrate (Paragraph 0083 – the first doped layer 11 may be locally discretely distributed near each hole region of the passivation layer);
in the case where the doped layer 11 is locally distributed near the holes of porous tunneling layer 12, then in those regions the passivation layer would be directly touching the back surface of the silicon substrate.
Chen et al. does not disclose that wherein a doping concentration in the doped polysilicon layer gradually decreases in a direction away from the tunneling layer.
Wang discloses a doping concentration in a doped polysilicon layer gradually decreases in a direction away from a tunneling layer (Page 5, Lines 20-45 - Example 2, see steps S2 & S3, S2 a tunneling layer is deposited, S3 doped amorphous silicon is heavily doped closer to the tunneling layer and gradually decreases shown in Fig. 1). Wang discloses that this doping configuration can improve the tunneling current, improve the contact ability, can effectively reduce the Auger recombination and reduce parasitic absorption of the polysilicon long-wave band (Page 5, Lines 40-46). Accordingly, it would have been obvious to one of ordinary skill in the art at the time the invention was filed to adopt Wang’s doping strategy and having the doping concentration in the doped polysilicon layer gradually decreases in a direction away from the tunneling layer in Chen et al. method of manufacturing a back contact solar cell for the advantages of improving the tunneling current, improving the contact ability, effectively reducing the Auger recombination and reducing parasitic absorption of the polysilicon long-wave band.
Annotated Chen et al. Fig. 8
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In view of Claim 11, Chen et al. and Wang are relied upon for the reasons given above in addressing Claim 10. Chen et al. teaches that the porous lattice does not completely penetrate the tunneling layer (Fig. 1, #12 – Paragraph 0078 – dry etching, and porous structure also has grooves/openings not extending through the layer).
In view of Claim 12, Chen et al. and Wang are relied upon for the reasons given above in addressing Claim 10. Chen et al. teaches that the tunneling layer on the back surface of the wafer comprises a silicon oxide or aluminum oxide layer (Paragraph 0020) or a silicon carbide layer (Paragraph 0018).
In view of Claim 13, Chen et al. and Wang are relied upon for the reasons given above in addressing Claim 1. Chen et al. discloses that the forming the porous lattice in the tunneling layer located in the first region on the back face of the silicon wafer comprises etching the tunneling layer by corrosive solution containing an additive to form the porous lattice in the tunneling layer (Paragraph 0078 – chemical corrosion).
In view of Claim 14, Chen et al. and Wang are relied upon for the reasons given above in addressing Claim 10. Chen et al. teaches that the tunneling layer on the back surface of the wafer comprises a silicon oxide or aluminum oxide layer (Paragraph 0020) or a silicon carbide layer (Paragraph 0018).
Claim 6 is rejected under 35 U.S.C. 103 as being unpatentable over Chen et al. (US 2023/0027636 A1) in view of Wang (CN-115692544-A) in view of Song (KR-20100128151-A). Wang and Song are mapped to the English machine translation provided by the EPO.
In view of Claim 6, Chen et al. and Wang are relied upon for the reasons given above in addressing Claim 2. Chen et al. does not disclose that the tunneling layer is etched by laser and the pulse width of the laser ranges from 1 ps to 50 ns, and a wavelength of the laser ranges from 200 nm to 800 nm.
Song discloses a tunneling layer that can be etched via layer with a pulse width of 100 fs to 100 ns (Page 3, Line 57), and the wavelength can range from 126-2940 nm (Page 3, Line 55). Song discloses that this configuration enables fine and precise machining (Page 3, Line 2). Accordingly, it would have been obvious to one of ordinary skill in the art at the time the invention was filed to etch the tunneling layer of modified Chen et al. via laser with a pulse width of 100 fs to 100 ns and a wavelength that can range from 126-2940 nm for the advantage of ablating the layer in a fine a precise fashion.
In regards to the limitation that, “the tunneling layer is etched by laser and the pulse width of the laser ranges from 1 ps to 50 ns, and a wavelength of the laser ranges from 200 nm to 800 nm”, the Examiner directs Applicant to MPEP 2144.05 I. In the case where the claimed ranges “overlap or lie inside ranges disclosed by the prior art” a prima facie case of obviousness exists. Accordingly, it would have been obvious to one of ordinary skill in the art to have selected the overlapping ranged disclosed by Song because selection of the overlapping portion or ranges has been held to be a prima facie case of obviousness.
Claim 7 is rejected under 35 U.S.C. 103 as being unpatentable over Chen et al. (US 2023/0027636 A1) in view of Wang (CN-115692544-A) in view of Carlson et al. (US 2017/0062633 A1). Wang is mapped to the English machine translation provided by the EPO.
In view of Claim 7, Chen et al. and Wang are relied upon for the reasons given above in addressing Claim 3. Modified Chen does not disclose that when the tunneling layer is etched by the corrosive solution containing the additive that the concentration of the corrosive solution is in a range of 0.5% to 15%.
Carlson et al. teaches that concentrations of etchants can be equal to or greater 10% and that the resultant surfaces may be substantially smoothed relative to a starting rough surface (Paragraph 0061). Accordingly, it would have been obvious to one of ordinary skill in the art at the time the invention was filed to have the concentration of the corrosive solution of Chen et al. be equal to or greater than 10% so that the porous lattice of Chen et al. is created so that the side surfaces are relatively smoothed.
Claim 7 is rejected under 35 U.S.C. 103 as being unpatentable over Chen et al. (US 2023/0027636 A1) in view of Wang (CN-115692544-A) in view of Garralaga Rojas (WO-2010122168-A2). Wang is mapped to the English machine translation provided by the EPO.
In view of Claim 7, Chen et al. and Wang are relied upon for the reasons given above in addressing Claim 3. Modified Chen does not disclose that when the tunneling layer is etched by the corrosive solution containing the additive that the concentration of the corrosive solution is in a range of 0.5% to 15%.
Garralaga Rojas discloses that the concentration of a etching solution (corrosive solution) can be less than 10% (Paragraph 0036) and that the concentration of the solution can influence the speed of the process and the resulting pores (Paragraph 0040). Accordingly, it would have been obvious to one of ordinary skill in the art at the time the invention was filed to have the concentration of the corrosive solution be less than 10% for the advantages of influencing the speed of the etching process and the resulting pores.
Claim 9 is rejected under 35 U.S.C. 103 as being unpatentable over Chen et al. (US 2023/0027636 A1) in view of Wang (CN-115692544-A) in view of Zhang et al. (US 2024/0145610 A1). Wang is mapped to the English machine translation provided by the EPO.
In view of Claim 9, Chen et al. and Wang are relied upon for the reasons given above in addressing Claim 8. Chen et al. does not disclose that the tunneling layer is deposited via PECVD, PEALD, LPCVD, PVD or ALD.
Zhang et al. discloses a tunneling layer can be deposited via PEALD and can overcome shortcomings in the art (Paragraph 0006-0007) while be deposited with a controllable thickness and pinholes with a high density and a large size can be achieved (Paragraph 0095). Accordingly, it would have been obvious to one of ordinary skill in the art at the time the invention was filed to utilize the PEALD method of depositing a tunneling layer as disclosed by Zhang et al. in modified Chen et al. method for the advantages of utilizing a method that offers depositing the layer with a controlled thickness and pinholes with a high density.
Response to Arguments
Applicant argues that Chen et al. does not disclose depositing a tunneling layer in the first region on the back face of the silicon wafer and forming a porous lattice in the tunneling layer located in the first region on the back face of the silicon wafer. The Examiner respectfully points out to Applicant that Chen et al. discloses depositing a tunneling layer in the first region on the back face of the silicon wafer and forming a porous lattice in the tunneling layer located in the first region on the back face of the silicon wafer (Figs 1 & 8, #12 – Paragraph 0077-0078). Accordingly, this argument is unpersuasive.
Applicant argues that Chen et al. does not disclose that the tunneling layer is in direct contact with the back face of the silicon wafer. The Examiner respectfully points out to Applicant that the tunneling layer can be in direct contact with the back face of the silicon wafer at local areas of the silicon substrate (Paragraph 0083 – the first doped layer 11 may be locally discretely distributed near each hole region of the passivation layer); and in the case where the doped layer 11 is locally distributed near the holes of porous tunneling layer 12, then in those regions the passivation layer would be directly touching the back surface of the silicon substrate. Accordingly, this argument is unpersuasive.
Conclusion
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to DANIEL P MALLEY JR. whose telephone number is (571)270-1638. The examiner can normally be reached Monday-Friday 8am-430pm EST.
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If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Jeffrey T Barton can be reached at 571-272-1307. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/DANIEL P MALLEY JR./Primary Examiner, Art Unit 1726
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