DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Interpretation
1. The following is a quotation of 35 U.S.C. 112(f):
(f) Element in Claim for a Combination. – An element in a claim for a combination may be expressed as a means or step for performing a specified function without the recital of structure, material, or acts in support thereof, and such claim shall be construed to cover the corresponding structure, material, or acts described in the specification and equivalents thereof.
The following is a quotation of pre-AIA 35 U.S.C. 112, sixth paragraph:
An element in a claim for a combination may be expressed as a means or step for performing a specified function without the recital of structure, material, or acts in support thereof, and such claim shall be construed to cover the corresponding structure, material, or acts described in the specification and equivalents thereof.
This application includes one or more claim limitations that use the word “means” or “step” but are nonetheless not being interpreted under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph because the claim limitation(s) recite(s) sufficient structure, materials, or acts to entirely perform the recited function. Such claim limitation(s) is/are: “means” in claims 1-17, 19-21.
Because this/these claim limitation(s) is/are not being interpreted under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph, it/they is/are not being interpreted to cover only the corresponding structure, material, or acts described in the specification as performing the claimed function, and equivalents thereof.
If applicant intends to have this/these limitation(s) interpreted under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph, applicant may: (1) amend the claim limitation(s) to remove the structure, materials, or acts that performs the claimed function; or (2) present a sufficient showing that the claim limitation(s) does/do not recite sufficient structure, materials, or acts to perform the claimed function.
Claim Rejections - 35 USC § 103
2. In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
3. Claims 1-4, 10-17, 19-21 are rejected under 35 U.S.C. 103 as being unpatentable over Wei et al. (US Pub. No. US2020/0363974) in view of Goyal et al. (US Pub. No. US20220382688)
As per claims 1 and 19, Wei discloses a method for reporting asset information, comprising:
reading, in response to a target device (fig.3, DIMM 304) supporting memory expansion, Serial Presence Detect (SPD) information (fig.3, serial presence detect (SPD) data 342) of a designated memory bank mounted to the target device from a configuration space register (paragraph 20, configure a memory address decode register for DIMMs) of a Memory Expander Controller (MXC) (fig.3, memory controller 326) of the target device by means of a Basic Input Output System (BIOS) (fig.3, BIOS 322), wherein the target device is a device that supports which is an open interconnection standard (paragraph 26, configure the operations between CPU 320 and the DIMMs. SPD data 342 includes information as to the configuration, capacity, signal timing requirements, and other parameters for the operation between CPU 320 and DIMMs 302, 304, and 306); and
reporting, in response to target SPD information having been read, the target SPD information to a Central Processing Unit (CPU) (fig.3, CPU 302) of the target device as system asset information by means of the BIOS (paragraph 36, a BIOS reads system association information from a NVDIMM).
Wei discloses all the limitations as the above but does not explicitly disclose wherein the target device is a device that supports a Computer Express Link (CXL) protocol. However, Goyal discloses this. (paragraph 6, deriving a plurality Compute Express Link (CXL) flow control units (flits) from the plurality of data packets received at a physical layer of a CXL memory controller.)
It would have been obvious to one with ordinary skill in the art before the effective filling date of the claimed invention was made to consider the teachings of Goyal with the teaching of Wei to allows efficient, direct, and low-latency sharing of data without requiring complex software-managed coherency, thus enhance the system performance.
As per claim 2, Wei discloses wherein the reading, in response to the target device supporting memory expansion, SPD information of the designated memory bank mounted to the target device from the configuration space register of the MXC of the target device by means of the BIOS comprises: accessing, in response to the target device supporting memory expansion, the configuration space register of the MXC by the BIOS in a memory map manner, so as to read the SPD information of the designated memory bank mounted to the target device from the configuration space register of the MXC. (paragraph 26, configure the operations between CPU 320 and the DIMMs. SPD data 342 includes information as to the configuration, capacity, signal timing requirements, and other parameters for the operation between CPU 320 and DIMMs 302, 304, and 306)
As per claim 3, Wei discloses wherein the reporting, in response to target SPD information having been read, the target SPD information to the CPU of the target device as system asset information by means of the BIOS comprises: adding, in response to the target SPD information having been read, the target SPD information to a designated data structure of the BIOS by means of the BIOS, so as to report the target SPD information to the CPU of the target device as the system asset information of the BIOS, wherein the designated data structure is a data structure for reporting the system asset information. (paragraph 26, BIOS 322 configures the operations between CPU 320 and DIMMs 302, 304, and 306, the CPU can communicate with memory 340 in the DIMMs directly via the high-bandwidth communication interface.)
As per claim 4, Wei discloses wherein before reading, in response to the target device supporting memory expansion, the SPD information of the designated memory bank mounted to the target device from the configuration space register of the MXC of the target device by means of the BIOS, the method further comprises: reading, after the MXC is powered on, the SPD information of the designated memory bank mounted to the target device by means of the MXC; and writing the read SPD information of the designated memory bank into the configuration space register of the MXC (paragraph 39, the applications and operating system can direct which type of data read or write is suitable for DRAM DIMMS or NVDIMMs.)
As per claim 10, Wei discloses wherein before reading, in response to the target device supporting memory expansion, the SPD information of the designated memory bank mounted to the target device from the configuration space register of the MXC of the target device by means of the BIOS, the method further comprises: reading memory expansion indication information from a specific configuration space register of the MXC of the target device by means of the BIOS, wherein the specific configuration space register is a configuration space register that records a device type of the target device, and the memory expansion indication information is configured to indicate whether the target device supports memory expansion(paragraph 26, configure the operations between CPU 320 and the DIMMs. SPD data 342 includes information as to the configuration, capacity, signal timing requirements, and other parameters for the operation between CPU 320 and DIMMs 302, 304, and 306); and determining, in response to the memory expansion indication information indicating that the target device supports memory expansion, that the target device supports memory expansion (paragraph 36, a service associated with the information handling system, or another indication associated with the information handling system, as needed or desired.)
As per claim 11, Wei discloses wherein after reading the memory expansion indication information from the specific configuration space register of the MXC of the target device by means of the BIOS, the method further comprises: determining, in response to the memory expansion indication information indicating that the target device does not support memory expansion, that the target device has no SPD information (paragraph 32, information within respective SPD data 342 that uniquely associated each NVDIMM with information handling system 300.)
As per claim 12, Wei discloses wherein after reading the SPD information of the designated memory bank mounted to the target device from the configuration space register of the MXC of the target device by means of the BIOS, the method further comprises: starting a timer in response to the SPD information being not read, wherein a timing time of the timer is a preset time interval between two adjacent readings of the SPD information of the designated memory bank (paragraph 14, BIOS 122 also represents firmware code to provide runtime services for OS 124 and other programs executed by CPU); and reading, in response to the timing time of the timer arriving, the SPD information of the designated memory bank again from the configuration space register of the MXC by means of the BIOS (paragraph 14, BIOS 122 also represents firmware code to provide runtime services for OS 124 and other programs executed by CPU 102.)
As per claim 13, Wei discloses wherein before reading the SPD information of the designated memory bank mounted to the target device from the configuration space register of the MXC of the target device by means of the BIOS, the method further comprises: acquiring first bit information corresponding to the SPD information of the designated memory bank from the configuration space register of the MXC, wherein the first bit information is configured to identify whether the SPD information stored in the configuration space register of the MXC is valid(paragraph 47, groups of tenants (users) share a common chassis, and each of the tenants has a unique set of resources assigned to them), and the SPD information of the designated memory bank read from the configuration space register of the MXC is executed in response to the first bit information being configured to identify that the SPD information stored in the configuration space register of the MXC is valid. (paragraph 26, configure the operations between CPU 320 and the DIMMs. SPD data 342 includes information as to the configuration, capacity, signal timing requirements, and other parameters for the operation between CPU 320 and DIMMs 302, 304, and 306)
As per claim 14, Wei discloses wherein the designated memory bank is a group of memory banks; and the method further comprises: acquiring, in response to a memory fault occurring, fault indication information corresponding to the group of memory banks from the configuration space register of the MX(paragraph 47, groups of tenants (users) share a common chassis, and each of the tenants has a unique set of resources assigned to them)C, wherein the fault indication information corresponding to the group of memory banks is configured to indicate whether each memory bank in the group of memory banks fails; and performing fault location according to the fault indication information corresponding to the group of memory banks, so as to locate the failed memory bank in the group of memory banks. (paragraph 26, configure the operations between CPU 320 and the DIMMs. SPD data 342 includes information as to the configuration, capacity, signal timing requirements, and other parameters for the operation between CPU 320 and DIMMs 302, 304, and 306)
As per claim 15, Wei discloses wherein the acquiring, in response to the memory fault occurring, the fault indication information corresponding to the group of memory banks (paragraph 47, groups of tenants (users) share a common chassis, and each of the tenants has a unique set of resources assigned to them) from the configuration space register of the MXC comprises: acquiring, in response to the memory fault occurring, second bit information corresponding to each memory bank in the group of memory banks from the configuration space register of the MXC, wherein the second bit information corresponding to each memory bank is configured to indicate whether each memory bank fails. (paragraph 26, configure the operations between CPU 320 and the DIMMs. SPD data 342 includes information as to the configuration, capacity, signal timing requirements, and other parameters for the operation between CPU 320 and DIMMs 302, 304, and 306)
As per claim 16, Wei discloses the method further comprising: respectively storing, in response to the MXC being connected to a group of host-side servers, the SPD information corresponding to each host-side server in the group of host-side servers in different areas of one designated memory bank. (paragraph 26, configure the operations between CPU 320 and the DIMMs. SPD data 342 includes information as to the configuration, capacity, signal timing requirements, and other parameters for the operation between CPU 320 and DIMMs 302, 304, and 306)
As per claim 17, Wei discloses wherein after respectively storing the SPD information corresponding to each host-side server in the group of host-side servers in different areas of one designated memory bank (paragraph 47, groups of tenants (users) share a common chassis, and each of the tenants has a unique set of resources assigned to them), the method further comprises: reading, after the MXC is powered on, the SPD information of the designated memory bank mounted to the target device by means of the MXC; and updating, according to the size of different areas of the designated memory bank, the memory size in the read SPD information of the designated memory bank, and writing the updated memory size into the configuration space register of the MXC, wherein the memory size in the read SPD information of the designated memory bank before the update is the memory size of the designated memory bank. (paragraph 26, configure the operations between CPU 320 and the DIMMs. SPD data 342 includes information as to the configuration, capacity, signal timing requirements, and other parameters for the operation between CPU 320 and DIMMs 302, 304, and 306)
As per claim 20, Wei discloses an electronic device, comprising a memory (fig.3, memory 340), a processor(fig.3, CPU 302), and a computer program stored in the memory and runnable on the processor, wherein the processor is configured to execute the computer program to: read, in response to a target device (fig.3, DIMM 304) supporting memory expansion, Serial Presence Detect (SPD) information (fig.3, serial presence detect (SPD) data 342) of a designated memory bank mounted to the target device from a configuration space register (paragraph 20, configure a memory address decode register for DIMMs) of a Memory Expander Controller (MXC) (fig.3, memory controller 326) of the target device by means of a Basic Input Output System (BIOS) (fig.3, BIOS 322), which is an open interconnection standard(paragraph 26, configure the operations between CPU 320 and the DIMMs. SPD data 342 includes information as to the configuration, capacity, signal timing requirements, and other parameters for the operation between CPU 320 and DIMMs 302, 304, and 306); and
report, in response to target SPD information having been read, the target SPD information to a Central Processing Unit (CPU) (fig.3, CPU 302) of the target device as system asset information by means of the BIOS (paragraph 36, a BIOS reads system association information from a NVDIMM).
Wei discloses all the limitations as the above but does not explicitly disclose wherein the target device is a device that supports a Computer Express Link (CXL) protocol. However, Goyal discloses this. (paragraph 6, deriving a plurality Compute Express Link (CXL) flow control units (flits) from the plurality of data packets received at a physical layer of a CXL memory controller.)
It would have been obvious to one with ordinary skill in the art before the effective filling date of the claimed invention was made to consider the teachings of Goyal with the teaching of Wei to allows efficient, direct, and low-latency sharing of data without requiring complex software-managed coherency, thus enhance the system performance.
As per claim 21, Wei discloses wherein the configuration space register of the MXC comprises a configuration space register in the MXC that is only configured to store the SPD information, and the configuration space register is one register or a group of registers. (paragraph 26, configure the operations between CPU 320 and the DIMMs. SPD data 342 includes information as to the configuration, capacity, signal timing requirements, and other parameters for the operation between CPU 320 and DIMMs 302, 304, and 306)
4. Claims 5-8 are rejected under 35 U.S.C. 103 as being unpatentable over Wei et al. (US Pub. No. US2020/0363974) in view of Goyal et al. (US Pub. No. US20220382688) and further in view of Li et al. (US Pub. No. US20230385220)
As per claim 5, Wei the writing the read SPD information of the designated memory bank into the configuration space register of the MXC comprises: writing the read SPD information of the designated memory bank into one register, wherein the space size of the register is a designated space size. (paragraph 27, BIOS 322 can store information related to the memory mode (e.g., application-direct mode, memory mode, storage mode) in which to operate the NVDIMM, to namespaces instantiated on the NVDIMM, or the like.)
Wei in view of Goyal disclose all the limitations as the above but do not disclose wherein the configuration space register of the MXC comprises: a Designated Vendor-Specific Extended Capability (DVSEC) register. However, Li discloses this. (paragraph 17, a set of registers (e.g., configuration, status and/or designated vendor-specific extended capability/DVSEC registers), wherein the registers 48 include DVSEC registers that report CXL memory capability and provide configuration information. Table I below shows two additional features of the DVSEC registers as further cited in paragraph 20)
It would have been obvious to one with ordinary skill in the art before the effective filling date of the claimed invention was made to consider the teachings of Li with the teaching of Wei in view of Goyal so as to help to determine the CXL capability so as to yield the predicatable result so as to control efficiently, thus enhance the system performance.
As per claim 6, Wei discloses wherein the configuration space register of the MXC comprises: the writing the read SPD information of the designated memory bank into the configuration space register of the MXC further comprises: respectively writing sub-SPD information read from each data block in a plurality of data blocks into one register, wherein the SPD information of the designated memory bank is divided into a plurality of pieces of sub-SPD information, and each piece of sub-SPD information in the plurality of pieces of sub-SPD information is respectively stored in each data block in the plurality of data blocks. (paragraph 37, if the association information received from BIOS 322 does not match the association information in its SPD data 342, each NVDIMM 304, 306, and 308 operates to block further boot operations from BIOS 322.)
Wei in view of Goyal disclose all the limitations as the above but do not disclose a Designated Vendor-Specific Extended Capability (DVSEC) register. However, Li discloses this. (paragraph 17, a set of registers (e.g., configuration, status and/or designated vendor-specific extended capability/DVSEC registers), wherein the registers 48 include DVSEC registers that report CXL memory capability and provide configuration information. Table I below shows two additional features of the DVSEC registers as further cited in paragraph 20)
It would have been obvious to one with ordinary skill in the art before the effective filling date of the claimed invention was made to consider the teachings of Li with the teaching of Wei in view of Goyal so as to help to determine the CXL capability so as to yield the predicatable result so as to control efficiently, thus enhance the system performance.
As per claim 7, Wei discloses wherein before respectively writing the sub-SPD information read from each data block in the plurality of data blocks into one register, the method further comprises: setting the corresponding register for each data block according to the space size of each data block, wherein the space size of the corresponding register set for each data block is greater than or equal to the space size of each data block. (paragraph 26, configure the operations between CPU 320 and the DIMMs. SPD data 342 includes information as to the configuration, capacity, signal timing requirements, and other parameters for the operation between CPU 320 and DIMMs 302, 304, and 306)
Wei in view of Goyal disclose all the limitations as the above but do not disclose a Designated Vendor-Specific Extended Capability (DVSEC) register. However, Li discloses this. (paragraph 17, a set of registers (e.g., configuration, status and/or designated vendor-specific extended capability/DVSEC registers), wherein the registers 48 include DVSEC registers that report CXL memory capability and provide configuration information. Table I below shows two additional features of the DVSEC registers as further cited in paragraph 20)
It would have been obvious to one with ordinary skill in the art before the effective filling date of the claimed invention was made to consider the teachings of Li with the teaching of Wei in view of Goyal so as to help to determine the CXL capability so as to yield the predicatable result so as to control efficiently, thus enhance the system performance.
As per claim 8, Wei discloses wherein before respectively writing the sub-SPD information read from each data block in the plurality of data blocks into one register, the method further comprises: numbering each data block in the plurality of data blocks; and setting a corresponding register identifier for each data block, wherein the register identifier corresponding to each data block comprises: a first register identifier for identifying a register vendor of the register corresponding to each data block, and a second register identifier for identifying the register corresponding to each data block, wherein some identifiers in the second register identifier corresponding to each data block are matched with a number of each data block (paragraph 33, when information handling system 300 is booted, BIOS 322 operates to read the identification information (i.e., the number, the service tag, or the like) from NVDIMMs 304, 306, and 308, and to compare the identification information from the NVDIMMs with the associated information on the information handling system.)
Wei in view of Goyal disclose all the limitations as the above but do not disclose a Designated Vendor-Specific Extended Capability (DVSEC) register. However, Li discloses this. (paragraph 17, a set of registers (e.g., configuration, status and/or designated vendor-specific extended capability/DVSEC registers), wherein the registers 48 include DVSEC registers that report CXL memory capability and provide configuration information. Table I below shows two additional features of the DVSEC registers as further cited in paragraph 20)
It would have been obvious to one with ordinary skill in the art before the effective filling date of the claimed invention was made to consider the teachings of Li with the teaching of Wei in view of Goyal so as to help to determine the CXL capability so as to yield the predicatable result so as to control efficiently, thus enhance the system performance.
5. Claim 9 is rejected under 35 U.S.C. 103 as being unpatentable over Wei et al. (US Pub. No. US2020/0363974) in view of Goyal et al. (US Pub. No. US20220382688) and further in view of Taveira et al. (US Pub. No. US 20240028769)
Wei in view of Goyal discloses all the limitations as the above but does not explicitly disclose wherein after reading the SPD information of the designated memory bank mounted to the target device by means of the MXC, the method further comprises: determining a first hash value corresponding to the read SPD information of the designated memory bank; and comparing the first hash value with a second hash value corresponding to the SPD information recorded in the configuration space register of the MXC, wherein the read SPD information of the designated memory bank is written into the configuration space register of the MXC in response to the first hash value and the second hash value being inconsistent. However, Taveira discloses this. (paragraph 23, information to uniquely identify the memory module and the BMC, such as a hash of the unique device identifier and a unique BMC identifier)
Wei discloses all the limitations as the above but does not explicitly disclose wherein the target device is a device that supports a Computer Express Link (CXL) protocol. However, Goyal discloses this. (paragraph 6, deriving a plurality Compute Express Link (CXL) flow control units (flits) from the plurality of data packets received at a physical layer of a CXL memory controller.)
It would have been obvious to one with ordinary skill in the art before the effective filling date of the claimed invention was made to consider the teachings of Goyal with the teaching of Wei to allows efficient, direct, and low-latency sharing of data without requiring complex software-managed coherency, thus enhance the system performance.
6. The prior art made of record and not relied upon is considered pertinent to applicant’s disclosure.
Kloth [US Pub. No. US20250036589] discloses ll DIMMs have in common is the SPD (Serial Presence Detect) ROM on the DIMM PCB.
/HENRY TSAI/Supervisory Patent Examiner, Art Unit 2184
Conclusion
7. Any inquiry concerning this communication or earlier communications from the examiner should be directed to KIM T HUYNH whose telephone number is (571)272-3635 or via e-mail addressed to [kim.huynh3@uspto.gov]. The examiner can normally be reached on M-F 7.00AM- 4:00PM. If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Tsai Henry can be reached at (571)272-4176 or via e-mail addressed to [Henry.Tsai@USPTO.GOV].
The fax phone numbers for the organization where this application or proceeding is assigned are (571)273-8300 for regular communications and After Final communications. Any inquiry of a general nature or relating to the status of this application or proceeding should be directed to the receptionist whose telephone number is (571)272-2100.
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/K. T. H./
Examiner, Art Unit 2184
/HENRY TSAI/Supervisory Patent Examiner, Art Unit 2184