DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Inventorship
This application currently names joint inventors. In considering patentability of the claims the examiner presumes that the subject matter of the various claims was commonly owned as of the effective filing date of the claimed invention(s) absent any evidence to the contrary. Applicant is advised of the obligation under 37 CFR 1.56 to point out the inventor and effective filing dates of each claim that was not commonly owned as of the effective filing date of the later invention in order for the examiner to consider the applicability of 35 U.S.C. 102(b)(2)(C) for any potential 35 U.S.C. 102(a)(2) prior art against the later invention.
Information Disclosure Statement
The information disclosure statements submitted on 4/22/2025 and 7/16/2026 are in compliance with the provisions of 37 CFR 1.97. Accordingly, the information disclosure statements are being considered by the examiner.
Specification
Applicant is reminded of the proper language and format for an abstract of the disclosure.
The abstract should be in narrative form and generally limited to a single paragraph on a separate sheet within the range of 50 to 150 words in length. The abstract should describe the disclosure sufficiently to assist readers in deciding whether there is a need for consulting the full patent text for details.
The language should be clear and concise and should not repeat information given in the title. It should avoid using phrases which can be implied, such as, “The disclosure concerns,” “The disclosure defined by this invention,” “The disclosure describes,” etc. In addition, the form and legal phraseology often used in patent claims, such as “means” and “said,” should be avoided.
The WO abstract submitted 4/22/2025 is improper under U.S. standards and practice.
The lengthy specification has not been checked to the extent necessary to determine the presence of all possible minor errors. Applicant’s cooperation is requested in correcting any errors of which applicant may become aware in the specification.
Claim Objections
Claims 1-20 are objected to because of the following informalities:
Claim 1 recites the limitation "the logic" in line 5. There is insufficient antecedent basis for this limitation in the claim. The applicant recited “logic” in line 3 and two instances of “logic” in line 4. Which logic is the applicant referencing?
Claims 2-6 inherit from claim 1.
Claim 7 recites the limitation "the logic" in line 6. There is insufficient antecedent basis for this limitation in the claim. The applicant recited “logic” in line 5 and two instances of “logic” in line 6. Which logic is the applicant referencing?
Claims 8-14 inherit from claim 7.
Claim 15 recites the limitation "the logic" in line 10. There is insufficient antecedent basis for this limitation in the claim. The applicant recited “logic” in line 8 and two instances of “logic” in line 9. Which logic is the applicant referencing?
Claims 16-20 inherit from claim 15.
Appropriate correction is required.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
Claim(s) 1-4 and 15-18 is/are rejected under 35 U.S.C. 103 as being unpatentable over Wei et al. (US 20080303495) in view of Bemanian et al. (US 20120068229).
Claim 1; Wei et al. disclose a voltage regulator controller (e.g. fig. 1) comprising: fixed-functionality hardware logic, the logic to: generate a first set of control signals (e.g. PWM1, En1, PWM2, En2) to control current in one or more coupled inductor pairs (181, 182) in a voltage regulator (10) circuit, wherein the control signals for each coupled inductor pair operate at a first frequency (e.g. [0028, [0038]]; Fsw) representing a base operation frequency of each coupled inductor phase (e.g. para. [0028]); and generate a second control signal at a second frequency to control current in an uncoupled inductor in the VR circuit, wherein the second frequency ([0038]; NACFsw) is set relative to the first frequency to control ripple in an output current of the VR circuit; wherein the first set of control signals and the second control signal represent, in combination, an odd phase count (3 phases; Phase 181, 182 and 28).
However, Wei et al. does not disclose whether there are one or more substrates and the logic is coupled to the one or more substrates.
Bemanian et al. teach a core die substrate having core logic blocks to produce density and flexibility while reducing time and cost for development and going from prototyping to production, reducing cost per die, reducing or eliminating NRE, and increasing performance.
Therefore, it would have been obvious to one having ordinary skill in the art at the time the invention was effectively filed to modify Wei et al. to include one or more substrates and the logic is coupled to the one or more substrates in order to produce higher density and flexibility while reducing time and cost for development and going from prototyping to production, reducing cost per die, reducing or eliminating NRE, and increasing performance as taught by Bemanian et al.
Claim 2; second frequency = NAC*Fsw; NAC=the number of active coupled phase.
Claim 3; Wei et al. and Bemanian et al. disclose the claimed subject matter in regards to claim 1 supra, except for the second frequency is set to a value approximately equal to 2N times the first frequency, wherein N is the number of coupled inductor pairs in the VR circuit.
It would have been obvious to one having ordinary skill in the art at the time the invention was effectively filed to modify Wei et al. and Bemanian et al. to set the second frequency at 2N time the first frequency, since it has been held that discovering an optimum value of a result effective variable involves only routine skill in the art. In re Boesch, 617 F.2d 272, 205 USPT 215 (CCPA 1980).
Therefore, it would have been obvious to one of ordinary skill in the art at the time the invention was effectively filed to modify Wei et al. and Bemanian et al. to include having the second frequency set to a value approximately equal to 2N times the first frequency, wherein N is the number of coupled inductor pairs in the VR circuit in order to use frequencies proportional to other phases to keep noise at acceptable levels.
Claims 4; phase shift 360/NAC, [0038].
Claims 15 and 16; a semiconductor apparatus comprising: a processor (15); a voltage regulator circuit (60) coupled to the processor, the voltage regulator circuit comprising one or more coupled inductor pairs (121, 122) and an uncoupled inductor (14), wherein an output of the uncoupled inductor is electrically coupled to an output of each of the one or more coupled inductor pairs; and logic implemented at least partly in one or more of fixed-functionality hardware logic, the logic to: generate a first set of control signals (e.g. PWM1, En1, PWM2, En2) to control current in one or more coupled inductor pairs (181, 182) in a voltage regulator (10) circuit, wherein the control signals for each coupled inductor pair operate at a first frequency (e.g. [0028, [0038]]; Fsw) representing a base operation frequency of each coupled inductor phase (e.g. para. [0028]); and generate a second control signal at a second frequency to control current in an uncoupled inductor in the VR circuit, wherein the second frequency ([0038]; NACFsw) is set relative to the first frequency to control ripple in an output current of the VR circuit; set a phase shift of the second control signal relative to a first phase of one of the first set of control signals (e.g. phase shift 360/NAC, [0038]) to further control the ripple in the output current of the VR circuit; wherein the first set of control signals and the second control signal represent, in combination, an odd phase count (3 phases; Phase 181, 182 and 28).
However, Wei et al. does not disclose whether there are one or more substrates and the logic is coupled to the one or more substrates.
Bemanian et al. teach a core die substrate having core logic blocks to produce density and flexibility while reducing time and cost for development and going from prototyping to production, reducing cost per die, reducing or eliminating NRE, and increasing performance.
Therefore, it would have been obvious to one having ordinary skill in the art at the time the invention was effectively filed to modify Wei et al. to include one or more substrates and the logic is coupled to the one or more substrates in order to produce higher density and flexibility while reducing time and cost for development and going from prototyping to production, reducing cost per die, reducing or eliminating NRE, and increasing performance as taught by Bemanian et al.
Claims 17 and 18; Wei et al. and Bemanian et al. disclose the claimed subject matter in regards to claim 1 supra, except for the second frequency is set to a value approximately equal to 2N times the first frequency, wherein N is the number of coupled inductor pairs in the VR circuit; phase shift 360/NAC, [0038].
It would have been obvious to one having ordinary skill in the art at the time the invention was effectively filed to modify Wei et al. and Bemanian et al. to set the second frequency at 2N time the first frequency, since it has been held that discovering an optimum value of a result effective variable involves only routine skill in the art. In re Boesch, 617 F.2d 272, 205 USPT 215 (CCPA 1980).
Therefore, it would have been obvious to one of ordinary skill in the art at the time the invention was effectively filed to modify Wei et al. and Bemanian et al. to include having the second frequency set to a value approximately equal to 2N times the first frequency, wherein N is the number of coupled inductor pairs in the VR circuit in order to use frequencies proportional to other phases to keep noise at acceptable levels.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
Claim(s) 7-10 is/are rejected under 35 U.S.C. 102a1/a2 as being anticipated by Wei et al.
Claim 7; Wei et al. disclose a voltage regulator comprising: one or more coupled inductor pairs (181, 182); an uncoupled inductor (28), wherein an output of the uncoupled inductor is electrically coupled to an output of each of the one or more coupled inductor pairs; and a control circuit (36) comprising logic to: generate a first set of control signals (PWM1, En1, PWM2, En2) to control current in one or more coupled inductor pairs in a voltage regulator (10) circuit, wherein the control signals for each coupled inductor pair operate at a first frequency (Fsw) representing a base operation frequency of each coupled inductor phase; generate a second control signal at a second frequency (NAC*Fsw) to control current in an uncoupled inductor in the VR circuit, wherein the second frequency is set relative to the first frequency to control ripple in an output current of the VR circuit; and set a phase shift (e.g. 360/2*NAC, [0038]) of the second control signal relative to a first phase of one of the first set of control signals to further control the ripple in the output current of the VR circuit; wherein the first set of control signals and the second control signal represent, in combination, an odd phase count (3 phases; Phase 181, 182 and 28).
Claim 8; second frequency = NAC*Fsw; NAC=the number of active coupled phase.
Claim 9; Wei et al. disclose the claimed subject matter in regards to claim 7 supra, except for the second frequency is set to a value approximately equal to 2N times the first frequency, wherein N is the number of coupled inductor pairs in the VR circuit.
It would have been obvious to one having ordinary skill in the art at the time the invention was effectively filed to modify Wei et al. to set the second frequency at 2N time the first frequency, since it has been held that discovering an optimum value of a result effective variable involves only routine skill in the art. In re Boesch, 617 F.2d 272, 205 USPT 215 (CCPA 1980).
Therefore, it would have been obvious to one of ordinary skill in the art at the time the invention was effectively filed to modify Wei et al. to include having the second frequency set to a value approximately equal to 2N times the first frequency, wherein N is the number of coupled inductor pairs in the VR circuit in order to use frequencies proportional to other phases to keep noise at acceptable levels.
Claim 10; ripple control, phase shift 360/NAC, [0038].
Allowable Subject Matter
Claims 5, 6, 11-14 and 19-20 would be allowable if rewritten to overcome the objection(s) set forth in this Office action and to include all of the limitations of the base claim and any intervening claims.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to GARY L LAXTON whose telephone number is (571)272-2079. The examiner can normally be reached Monday-Friday, 8 am-4 pm.
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/GARY L LAXTON/ Primary Examiner, Art Unit 2838 9/29/2026
