DETAILED ACTION
This Office Action is sent in response to Applicant’s Communication received 04/23/25 for application number 19/123,720. The Office hereby acknowledges receipt of the following and placed of record in file: Specification, Drawings, Abstract, Oath/Declaration, IDS, and Claims.
The Preliminary Amendment filed 04/23/25 is acknowledged. Claims 1, 3, 4, 10, 12, 13, and 19 are amended. Claims 1-20 are pending.
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Interpretation
The following is a quotation of 35 U.S.C. 112(f):
(f) Element in Claim for a Combination. – An element in a claim for a combination may be expressed as a means or step for performing a specified function without the recital of structure, material, or acts in support thereof, and such claim shall be construed to cover the corresponding structure, material, or acts described in the specification and equivalents thereof.
The following is a quotation of pre-AIA 35 U.S.C. 112, sixth paragraph:
An element in a claim for a combination may be expressed as a means or step for performing a specified function without the recital of structure, material, or acts in support thereof, and such claim shall be construed to cover the corresponding structure, material, or acts described in the specification and equivalents thereof.
The claims in this application are given their broadest reasonable interpretation using the plain meaning of the claim language in light of the specification as it would be understood by one of ordinary skill in the art. The broadest reasonable interpretation of a claim element (also commonly referred to as a claim limitation) is limited by the description in the specification when 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph, is invoked.
As explained in MPEP § 2181, subsection I, claim limitations that meet the following three-prong test will be interpreted under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph:
(A) the claim limitation uses the term “means” or “step” or a term used as a substitute for “means” that is a generic placeholder (also called a nonce term or a non-structural term having no specific structural meaning) for performing the claimed function;
(B) the term “means” or “step” or the generic placeholder is modified by functional language, typically, but not always linked by the transition word “for” (e.g., “means for”) or another linking word or phrase, such as “configured to” or “so that”; and
(C) the term “means” or “step” or the generic placeholder is not modified by sufficient structure, material, or acts for performing the claimed function.
Use of the word “means” (or “step”) in a claim with functional language creates a rebuttable presumption that the claim limitation is to be treated in accordance with 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph. The presumption that the claim limitation is interpreted under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph, is rebutted when the claim limitation recites sufficient structure, material, or acts to entirely perform the recited function.
Absence of the word “means” (or “step”) in a claim creates a rebuttable presumption that the claim limitation is not to be treated in accordance with 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph. The presumption that the claim limitation is not interpreted under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph, is rebutted when the claim limitation recites function without reciting sufficient structure, material or acts to entirely perform the recited function.
Claim limitations in this application that use the word “means” (or “step”) are being interpreted under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph, except as otherwise indicated in an Office action. Conversely, claim limitations in this application that do not use the word “means” (or “step”) are not being interpreted under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph, except as otherwise indicated in an Office action.
This application includes one or more claim limitations that do not use the word “means,” but are nonetheless being interpreted under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph, because the claim limitation(s) uses a generic placeholder that is coupled with functional language without reciting sufficient structure to perform the recited function and the generic placeholder is not preceded by a structural modifier. Such a claim limitation is:
“a centralized di/dt manager that is configured to perform operations” in Claim 1.
Because this claim limitation is being interpreted under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph, it is being interpreted to cover the corresponding structure described in the specification as performing the claimed function, and equivalents thereof.
A review of the Specification shows that the following appears to be the corresponding structure described for the 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph limitation:
“In some implementations, the system 100, e.g., the di/dt manager 104, can include a plurality of status registers…” Par 26. As such, the di/dt manager is a component which contains computing registers.
If applicant does not intend to have this limitation interpreted under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph, applicant may: (1) amend the claim limitation(s) to avoid it/them being interpreted under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph (e.g., by reciting sufficient structure to perform the claimed function); or (2) present a sufficient showing that the claim limitation recites sufficient structure to perform the claimed function so as to avoid it being interpreted under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
Claims 1-5, 8-14, and 17-20 are rejected under 35 U.S.C. 103 as being unpatentable over Ho et al., US 2020/0341533 A1, in view of Park, US 2015/0220672 A1, and further in view of Zheng et al., US 20120146706 A1.
Regarding Claim 1, Ho discloses a device [processor circuit and power management circuit, Fig. 2] comprising:
a plurality of computing devices, wherein each computing device has respective clock gating logic that is configured to apply clock gating to a portion of the computing device [throttle circuit 213 sends gated core clock signals to respective processor cores]; and
a centralized di/dt manager that is configured to perform operations [throttle circuit 213] comprising:
receiving, from the plurality of computing devices, respective clock gating requests to perform the clock gating;
computing, from the clock gating requests, a total clock gating value of the device;
determining, from the total clock gating value, which of the clock gating requests from the plurality of computing devices to approve, such that a total approved clock gating is less than a clock gating threshold of the device [throttle circuit 213 also receives clock signal 222 which is used to generate gated core clock signals 226 and cache clock signal 228. Based on a current value of throttle amount 220, throttle circuit 213 may disable one or more of gated core clock signals 226 and/or insert one or more idle cycles into cache clock signal 228. The value of throttle amount 220 may change as the total number of currently available power credits changes and reaches a different threshold value. Based on a changed value of throttle amount 220, throttle circuit 213 may enable or disable various throttling actions; the number of power credits in a given allotment may be fixed or may vary dependent on power usage of a computing system that includes processor circuit 100. A number of power credits are spent (e.g., decremented from power credit total 115) based on power usage by the circuits of processor circuit 100; i.e. based on power credits available (total value threshold), throttle circuit 213 will determine which gated core clock signals 226 are to be disabled, par 65, 41, 43].
However, Ho does not explicitly teach wherein each clock gating request specifies a respective clock gating value representing how much of the requesting computing device will be clock gated; and providing, the each of the plurality of computing devices, responses to the respective clock gating requests, each response representing whether the clock gating request is approved.
Park teaches wherein each clock gating request specifies a respective clock gating value representing how much of the requesting computing device will be clock gated [power state defining unit may define a power state using a CGEN (clock gating enable) signal and extracts a power value; i.e. clock gating enable (request) is associated with a value, par 40, 41].
It would have been obvious to one of ordinary skill in the art, having the teachings of Ho and Park before him before the effective filing date of the claimed invention, to incorporate the respective values for each power management signal as taught by Park, into the device as disclosed by Ho, to enable accurate power consumption analysis [Park, par 5].
However, the combination of references does not explicitly teach providing, the each of the plurality of computing devices, responses to the respective clock gating requests, each response representing whether the clock gating request is approved.
Zheng teaches providing, the each of the plurality of computing devices, responses to the respective gating requests, each response representing whether the gating request is approved [each gating request is reviewed and an acknowledgement is returned for each, Fig. 8; par 44].
It would have been obvious to one of ordinary skill in the art, having the teachings of Ho, Park, and Zheng before him before the effective filing date of the claimed invention, to incorporate the individual acknowledgement of gating requests as taught by Zheng, into the device as disclosed by Ho and Park, to allow for improved transition between operating modes [Zheng, par 3].
Regarding Claim 2, Ho, Park, and Zheng disclose the device of Claim 1. Ho further discloses wherein each computing device applies the requested clock gating if and only if the centralized di/dt manager has provided a response approving the clock gating request [throttle circuit determines which gated core clock signals are sent (i.e. only those that are approved are sent gated core clock signals), par 65, 41, 43].
Regarding Claim 3, Ho, Park, and Zheng disclose the device of Claim 1. Ho further discloses wherein determining which of the clock gating requests to approve comprises: comparing the total clock gating value to the clock gating threshold of the device; determining that the total clock gating value is less than the clock gating threshold; and in response, approving the clock gating requests from all of the computing devices [throttle circuit 213 also receives clock signal 222 which is used to generate gated core clock signals 226 and cache clock signal 228. Based on a current value of throttle amount 220, throttle circuit 213 may disable one or more of gated core clock signals 226 and/or insert one or more idle cycles into cache clock signal 228. The value of throttle amount 220 may change as the total number of currently available power credits changes and reaches a different threshold value. Based on a changed value of throttle amount 220, throttle circuit 213 may enable or disable various throttling actions; the number of power credits in a given allotment may be fixed or may vary dependent on power usage of a computing system that includes processor circuit 100. A number of power credits are spent (e.g., decremented from power credit total 115) based on power usage by the circuits of processor circuit 100; that is, based on power credits available (total value threshold), throttle circuit 213 will determine which gated core clock signals 226 are to be disabled (depending on power credits, if insufficient credits are available, then all clock gating requests would be approved), par 65, 41, 43].
Regarding Claim 4, Ho, Park, and Zheng disclose the device of Claim 1. Ho further discloses wherein determining which of the clock gating requests to approve comprises: comparing the total clock gating value to the clock gating threshold of the device; determining that the total clock gating value is greater than the clock gating threshold; and in response, providing approvals to fewer than all of the plurality of computing devices [throttle circuit 213 also receives clock signal 222 which is used to generate gated core clock signals 226 and cache clock signal 228. Based on a current value of throttle amount 220, throttle circuit 213 may disable one or more of gated core clock signals 226 and/or insert one or more idle cycles into cache clock signal 228. The value of throttle amount 220 may change as the total number of currently available power credits changes and reaches a different threshold value. Based on a changed value of throttle amount 220, throttle circuit 213 may enable or disable various throttling actions; the number of power credits in a given allotment may be fixed or may vary dependent on power usage of a computing system that includes processor circuit 100. A number of power credits are spent (e.g., decremented from power credit total 115) based on power usage by the circuits of processor circuit 100; that is, based on power credits available (total value threshold), throttle circuit 213 will determine which gated core clock signals 226 are to be disabled (any amount over the available power credits will not need to be disabled, i.e. fewer than all will be clock gated), par 65, 41, 43].
Regarding Claim 5, Ho, Park, and Zheng disclose the device of Claim 4. Ho further discloses wherein providing the approvals to fewer than all of the plurality of computing devices comprises selecting a combination of the plurality of computing devices whose clock gating values are less than the clock gating threshold [throttle circuit 213 also receives clock signal 222 which is used to generate gated core clock signals 226 and cache clock signal 228. Based on a current value of throttle amount 220, throttle circuit 213 may disable one or more of gated core clock signals 226 and/or insert one or more idle cycles into cache clock signal 228. The value of throttle amount 220 may change as the total number of currently available power credits changes and reaches a different threshold value. Based on a changed value of throttle amount 220, throttle circuit 213 may enable or disable various throttling actions; the number of power credits in a given allotment may be fixed or may vary dependent on power usage of a computing system that includes processor circuit 100. A number of power credits are spent (e.g., decremented from power credit total 115) based on power usage by the circuits of processor circuit 100; that is, based on power credits available (total value threshold), throttle circuit 213 will determine which gated core clock signals 226 are to be disabled (which would consist of a combination of signals that are less than the total power credits available), par 65, 41, 43].
Regarding Claim 8, Ho, Park, and Zheng disclose the device of Claim 1. Ho further discloses wherein each clock gating value represents a percentage of a computing device that is to be clock gated [power credit is a percentage of the total power credit allotment, par 65, 41, 43].
Regarding Claim 9, Ho, Park, and Zheng disclose the device of Claim 1. Ho further discloses wherein the centralized di/dt manager and the plurality of computing devices are integrated on a single system on a chip [computing system can include systems-on-a-chip (SoCs), par 2].
Regarding Claim 10, Ho discloses a method [using the processor circuit and power management circuit, Fig. 2]. The remainder of Claim 10 repeats the same limitations as recited in Claim 1, and is rejected accordingly.
Regarding Claims 11-14, 17, and 18, Ho, Park, and Zheng disclose the method of Claim 10. Claims 11-14, 17, and 18 repeat the same limitations as recited in Claims 2-5, 8, and 9, respectively, and are rejected accordingly.
Regarding Claim 19, Ho discloses one or more non-transitory storage media encoded with instructions that when executed by a centralized di/dt manager included in a device cause the di/dt manager to perform operations [storage media containing instructions on cache memory 205 performed by power management circuit 210 and throttle circuit 213, Fig. 2]. The remainder of Claim 19 repeats the same limitations as recited in Claim 1, and is rejected accordingly.
Regarding Claim 20, Ho, Park, and Zheng disclose the non-transitory storage media of Claim 19. Claim 20 repeats the same limitations as recited in Claim 2, and is rejected accordingly.
Claims 6, 7, 15, and 16 are rejected under 35 U.S.C. 103 as being unpatentable over Ho, Park, and Zheng, and further in view of Bulja et al., US 2021/0313390 A1.
Regarding Claim 6, Ho, Park, and Zheng disclose the device of Claim 1. Ho further discloses wherein each of the plurality of computing devices is associated with a weight [energy modeling circuit generates weighted estimates and uses weighted estimates to generate power credits, which are in turn used by throttle circuit 213 to generate gated core clock signals, par 53].
However, the combination of references does not explicitly teach wherein computing the total clock gating value of the device comprises multiplying the clock gating value of each request by a respective weight from the requesting computing device.
Bulja teaches wherein computing the total clock gating value of the device comprises multiplying the clock gating value of each request by a respective weight from the requesting computing device [total dielectric value of an EA-controlled multi-surface structure may be weighted in the horizontal direction based on relative sizes of Er and EA regions (e.g., dielectric tiles 210 and EA blocks 230) in each of the stacked EA smart surface layers of the EA-controlled multi-surface structure; i.e. total value is based on weighted values (multiplying value by the weight), par 91].
It would have been obvious to one of ordinary skill in the art, having the teachings of Ho, Park, Zheng, and Bulja before him before the effective filing date of the claimed invention, to incorporate the weighted values in the total value determination as taught by Bulja, into the device as disclosed by Ho, Park, and Zheng, to consider the appropriate effect components may have on the system [Bulja, par 91].
Regarding Claim 7, Ho, Park, Zheng, and Bulja disclose the device of Claim 6. Bulja further teaches wherein the weight is proportional to a size of the computing device of a frequency of the computing device [total dielectric value of an EA-controlled multi-surface structure may be weighted in the horizontal direction based on relative sizes of Er and EA regions (e.g., dielectric tiles 210 and EA blocks 230) in each of the stacked EA smart surface layers of the EA-controlled multi-surface structure (i.e. based on the size of the region), par 91].
Regarding Claims 15 and 16, Ho, Park, and Zheng disclose the method of Claim 10. Claims 15 and 16 repeat the same limitations as recited in Claims 6 and 7, respectively, and are rejected accordingly.
Conclusion
Applicant is reminded that in amending a response to a rejection of claims, the patentable novelty must be clearly shown in view of the state of the art disclosed by the references cited and the objections made. Applicant must also show how the amendments avoid such references and objections. See 37 CFR §1.111(c).
Any inquiry concerning this communication or earlier communications from the examiner should be directed to PAUL J YEN whose telephone number is (571)270-5047. The examiner can normally be reached M-F 8-5 PT.
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If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Andrew J Jung can be reached at (571) 270-3779. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/Paul Yen/Primary Examiner, Art Unit 2175
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