DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Information Disclosure Statement
The information disclosure statement (IDS) documents submitted on April 25, 2025, and March 11 2026 are in compliance with the provisions of 37 CFR 1.97. Accordingly, the information disclosure statement is being considered by the examiner.
Claim Rejections - 35 USC § 102
1. In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
Claims 11, 20, 21,30 are rejected under 35 U.S.C. 102(a) (2) as being anticipated by Lyu et al. (US Pub. No.: US 2023/0206476 A1).
Regarding claim 11, Lyu et al. discloses a control device (Para 45; Fig. 3; camera system 100), comprising a main processor (Para 114; general processor 158), a coprocessor (Para 148-149; CNN module 190b; Figs. 3, 4) , and an AI chip ( Fig. 4; Para 81,82; 119; system on chip, hardware engines 204a-204n of processor 102 ; The hardware engines 204a-204n are generally configured to perform operators that may include, but are not limited to, a resampling operator, a warping operator, component operators that manipulate lists of components (e.g., components may be regions of a vector that share a common attribute and may be grouped together with a bounding box), a matrix inverse operator, a dot product operator, a convolution operator, conditional operators (e.g., multiplex and demultiplex), ) , wherein:
the AI chip is configured to preprocess an image, and the preprocessing comprises performing a matrix-related operation on the image (Para 119, 150; The dedicated hardware modules 204a-204n may be configured to decompose the high-resolution 2D image I to generate the sub-images 352a-352n and the high-resolution depth map image D to generate the sub-images 354a-354n.);
the coprocessor is configured to perform a floating-point operation process on the
preprocessed image (Para 141-149, Fig. 7; The sub-images may be used to calculate an alignment matrix using low-bit-width floating-point representation and operations. The processor 102 may be configured to perform the data arrangement 350 in order to implement an accelerated alignment of high-resolution 2D images and high-resolution depth map images using a low-bit-width floating-point representation; The data arrangement 350 may be performed by the processor 102 and/or the CNN module 190b.);
and the AI chip is further configured to process image data processed by the coprocessor ( Para 152-156; The processor 102 and/or the CNN module 190b may be configured to use the dedicated hardware modules 204a-204n to calculate the Q matrices 362a-362n using the intrinsic matrices of the camera 356a-356n and 358a-358n, the projection matrix of the camera 360, and Equation 7 above; an aligned depth image may be generated.),and output a processed result to the main processor for next processing (Para 115; The processor 158 may be configured to communicate with the circuit 102 and/or access results generated by components of the circuit 102.).
Regarding claim 20, Lyu et al. discloses the control device according to claim 11, wherein the image is captured by a camera, the camera is a live streaming camera (Para 37; Fig. 1; automated number plate recognition (ANPR) cameras 100a, traffic cameras 100b, vehicle cameras 100c, access control cameras 100d, automatic teller machine (ATM) cameras 100e, bullet cameras 100f, dome cameras 100n, etc.), and the control device is an embedded hardware processing platform in the live streaming camera ( Fig.3; Para 11, 93,94, 117; he processor generally comprises a plurality of hardware engines configured to perform the matrix operations.).
Regarding claim 21, Lyu et al. discloses an electronic apparatus ( Para 45; camera system 100 ) , comprising the control device according to claim 11 for controlling a camera (Figs. 3, 4) , wherein the camera comprises an image sensor (Para 34; capture device include sensors) and a lens (Para 45; the lens 160, ) , the image is captured by the image sensor, and the control device is configured to control the lens to focus ( Para 58; 82; The capture device 104 may be configured to capture video image data (e.g., light collected and focused by the lens 160). The capture device 104 may capture data received through the lens 160 to generate a video bitstream (e.g., pixel data for a sequence of video frames). The pixel data signals may be enhanced by the processor 102 (e.g., color conversion, noise filtering, auto exposure, auto white balance, auto focus, etc.).).
Regarding claim 30, Lyu et al. discloses the camera is a live streaming camera (Para 37; Fig. 1; automated number plate recognition (ANPR) cameras 100a, traffic cameras 100b, vehicle cameras 100c, access control cameras 100d, automatic teller machine (ATM) cameras 100e, bullet cameras 100f, dome cameras 100n, etc.), and the control device is an embedded hardware processing platform in the live streaming camera ( Fig.3; Para 11, 93,94, 117; he processor generally comprises a plurality of hardware engines configured to perform the matrix operations.).
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102 of this title, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim 18 is rejected under 35 U.S.C. 103 as being unpatentable over Lyu et al. (US Pub. No.: US 2023/0206476 A1), in view of Holub (US Pub. No.: 2019/0287226 A1).
Regarding claim 18, Lyu et al. discloses the control device according to claim 11, wherein the main processor is a CPU (Para 165; CPU), and the AI chip is a DSP chip (Para 127; digital signal processor).
However, Lyu et al. does not disclose the coprocessor is a Neon coprocessor.
Holub discloses a Neon coprocessor (Para 76; vector operation support (vector processor), such as ARM NEON processors).
It would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention to modify Lyu with the teaching of Holub to utilize Neon processor for the coprocessor to accurately perform floating point operation with improved processing speed and machine learning capability.
Regarding claim 28, Lyu et al. discloses wherein the main processor is a CPU (Para 165; CPU), and the AI chip is a DSP chip (Para 127; digital signal processor).
However, Lyu et al. does not disclose the coprocessor is a Neon coprocessor.
Holub discloses a Neon coprocessor (Para 76; vector operation support (vector processor), such as ARM NEON processors).
It would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention to modify Lyu with the teaching of Holub to utilize Neon processor for the coprocessor to accurately perform floating point operation with improved processing speed and machine learning capability.
Allowable Subject Matter
Claim 12 is objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
Regarding claim 12, Prior art on record Lyu discloses wherein a pre-trained target detection network is deployed in the AI chip ( Para 48; the processor/SoC 102 may be configured to execute one or more artificial neural network models (e.g., facial recognition CNN, object detection CNN, object classification CNN, 3D reconstruction CNN, etc.) stored in the memory 150.) .
However, the prior art does not disclose “the preprocessed image satisfies a format requirement of the target detection network; the floating-point operation process is configured to normalize the preprocessed image to obtain normalized image data;
the AI chip is further configured to input the normalized image data into the target detection network, and obtain an output result of the target detection network, and the output result is configured to determine a position of a subject to be shot in the image;
and the main processor is configured to determine the position of the subject to be shot in the image according to the output result, and determine a focusing region based on the position to control a device for capturing the image to focus based on the focusing region” in combination of other limitation in the claim.
Claims 13-17, 19 are objected to as being dependent from claim 12.
Regarding claim 22, Prior art on record Lyu discloses wherein a pre-trained target detection network is deployed in the AI chip ( Para 48; the processor/SoC 102 may be configured to execute one or more artificial neural network models (e.g., facial recognition CNN, object detection CNN, object classification CNN, 3D reconstruction CNN, etc.) stored in the memory 150.) .
However, the prior art does not disclose “the preprocessed image satisfies a format requirement of the target detection network; the floating-point operation process is configured to normalize the preprocessed image to obtain normalized image data;
the AI chip is further configured to input the normalized image data into the target detection network, and obtain an output result of the target detection network, and the output result is configured to determine a position of a subject to be shot in the image; and the main processor is configured to determine the position of the subject to be shot in the image according to the output result, and determine a focusing region based on the position to control a device for capturing the image to focus based on the focusing region” in combination of other limitation in the claim.
Claims 23,24,25,26,27,29 are objected to as being dependent from claim 22.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to XI WANG whose telephone number is (469)295-9155. The examiner can normally be reached on 9:00 am-5:00 pm.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, SINH TRAN can be reached on 571-272-7564. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/XI WANG/Primary Examiner, Art Unit 2637
