Detailed Action
Status of Claims
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claims 1-30 are presented for examination.
Claims 1-18 are cancelled.
Claims 19-30 are new.
Claims 19-30 are rejected.
This Action is Non-Final.
Information Disclosure Statement
The information disclosure statement (IDS) submitted on 04/25/2025,the submission is in compliance with the provisions of 37 CFR 1.97. Accordingly, the information disclosure statement is being considered by the examiner.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 19-30 are rejected under 35 U.S.C. 103 as being unpatentable over Bilger et al. (US Patent Application Pub. No: 20090129189 A1) in view of Park et al. (US Patent Application Pub. No: 20230178166 A1).
As per claim 19,Bilger teaches a device [Fig.1, a memory device 10.], comprising:
a plurality of memory devices [Fig.1, The memory device 10 comprises a plurality of memory cells 11,…], each having a serial self-repair interface [Paragraphs 0022;0094, the memory device 10 for self-repair, internal timings, interface parameters or a plurality of these data….], one of the memory devices acting as a main memory [Fig.1, a memory device 10.], and all other memory devices acting as shadow memories [Fig.1, a plurality of memory cells 11.]; and
a sharing structure comprising logic circuitry [Fig. ,…a logic 1 is written to a memory cell 11 under test.], for inputting a same set of self-repair data to each of the plurality of memory devices and receiving self-repair outputs from the plurality of memory devices [Paragraph 0093,… Retrievable data concerning the memory device may include also the temperature of the die, retention times, remaining redundancy of the memory device for self-repair, internal timings or interface parameters and a health status of the memory device (which may be determined by one or more of the retrievable data).],
wherein the, logic configured to detect mismatches between the self-repair outputs of the plurality of memory devices [Paragraphs 0063;0068,…A mismatch between Q1 and Qt occurs which will cause an error signal Err at the output of the XOR gate 30.], the fault identification logic comprises a plurality of XOR gates configured to compare self-repair outputs from respective pairs of the plurality of memory devices, and the fault identification logic comprises an N-input OR gate having a number of inputs equal to the number of XOR gates [Paragraphs 0063;0068, …, a mismatch between the output of sampling element 28a and the output of any other sampling element 28b, 28c will cause an error signal Err1, Err2, Err3 at the output of the respective XOR gate 30a, 30b, 30c. The plurality of output signals Err1, Err2, Err3 can be processed as a digital number in subsequent parts of the system or the memory device 10 to determine the timing margin applicable to the memory cells 11 under test.].
Bilger teach does not explicitly disclose sharing structure comprises fault identification.
Park discloses sharing structure comprises fault identification [Paragraphs 0022;0028,… a shared built-in self-test (BIST) structure in which a plurality of memory channels 121, 122, . . . , 12n are connected to a memory controller 110 via a single bus (130),…].
It would have been obvious one ordinary skill in the art before the effective filling, date of the claimed invention, to include Park’s a system with multiple memory devices comprising arrays of memory cells into Bilger’s a memory device for the benefit of a high capacity, and can ensure stable and quick real-time processing of large capacities of data and product with high quality and finish final mounting test on a pass sample for each operation when final pass sample is processed as a good product and a defective sample for each operation is processed as a fail (Park,[0004]-[0006]) to obtain the invention as specified in claim 1.
As per claim 20, Bilger and Park teach all the limitations of claim 19 above, where Park teaches, a device, wherein sharing structure comprises a main self-repair chain test and a plurality of shadow self-repair chain tests [Park, Paragraphs 0022;0028,… a shared built-in self-test (BIST) structure in which a plurality of memory channels 121, 122, . . . , 12n are connected to a memory controller 110 via a single bus (130),…].
As per claim 21, Bilger and Park teach all the limitations of claim 19 above, where Bilger and Park teach, a device, wherein the sharing structure comprises fault [Park, Paragraphs 0022;0028,… a shared built-in self-test (BIST) structure in which a plurality of memory channels 121, 122, . . . , 12n are connected to a memory controller 110 via a single bus (130),…], reinjection logic configured to flip the values of the self-repair outputs of the plurality of memory devices [Bilger, Paragraphs 0022;0094,… the memory device 10 for self-repair, internal timings, interface parameters or a plurality of these data….].
As per claim 22, Bilger and Park teach all the limitations of claim 19 above, where Bilger teaches, a device, wherein the device is configured to apply the same self-repair data to each of the plurality of memory devices having serial self-repair interfaces [Bilger, Paragraphs 0022;0094, …the memory device 10 for self-repair, internal timings, interface parameters or a plurality of these data….].
As per claims 23-26, claims 23-26 are rejected in accordance to the same rational and reasoning as the above claims 19-22 above, wherein claims 23-26 are the method claims for the device of claims 19-22.
As per claims 27-30, claims 27-30 are rejected in accordance to the same rational and reasoning as the above claims 19-22 above, wherein claims 27-30 are the device claims for the device of claims 19-22.
Any comments considered necessary by applicant must be submitted no later than the payment of the issue fee and, to avoid processing delays, should preferably accompany the issue fee. Such submissions should be clearly labeled “Comments on Statement of Reasons for Allowance.”
Conclusion
RELEVANT ART CITED BY THE EXAMINER
The following prior art made of record and not relied upon is cited to establish the level of skill in the applicant’s art and those arts considered reasonably pertinent to applicant’s disclosure. See MPEP 707.05(c).
References Considered Pertinent but not relied upon
Kraipak et al. (US Patent Application Pub. No: 20180174665 A1) teaches the memory system has a built-in self-repairable memory (BISRM) comprising a main memory area and a redundant memory area comprising at least one spare column. Kraipak discloses a built-in-self test (BIST) controller configured to validate memory locations of the main memory area by writing test data to the memory locations through a test data bus. Kraipak suggests an error injection system configured to inject fault data to a memory location, of the memory locations, through the test data bus. Kraipak further discloses the error injection system comprises at least one error injection component configured to generate the fault data in accordance with fault configuration data written to a fault test data register.
NADEAU-DOSTIE et al.(US Patent Application Pub. No: 20080065929 A1) teaches a system has a fuse box module for retrieving data from a nonvolatile memory operatively coupled to the fuse box module. NADEAU-DOSTIE discloses an external repair register is provided for storing memory repair data, where the external repair register is operatively coupled to a corresponding embedded memory. NADEAU-DOSTIE suggests a set of serial links is provided for interconnecting the external repair registers in series configuration to form a daisy chain commencing at an end and terminating at another end at the fuse box module, where the fuse box module determines the bit length of the daisy chain.
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/GETENTE A YIMER/Primary Examiner, Art Unit 2181
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