DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Priority
Receipt is acknowledged of certified copies of papers submitted under 35 U.S.C. 119(a)-(d), which papers have been placed of record in the file.
Claim Objections
Claims 9-10 are objected to because of the following informalities:
Claim 9 recites the limitation “the horizontal time.” There is insufficient antecedent basis for this limitation in the claim.
The claim contains no earlier recitation or limitation of a “horizontal time.”
Appropriate correction is required.
Any remaining claim(s) is/are objected to, as being dependent upon one or more objected base claims.
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claims 1, 3-5, 8 and 9 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Kong et al (US 2018/0315390 A1).
Regarding claim 1, Kong discloses a data driving device [e.g., Fig. 7A: 300b; Paragraph 91: an amplifying circuit 310b, an output switching circuit 320b, a decoder 330b, an input switching circuit 340b, and a shift register 350b] comprising:
a latch circuit [e.g., Fig. 7A: 350b] configured to store pixel image data [e.g., Fig. 1: DATA; Paragraph 92: The shift register 350b may store the image data DATA, for example, pixel data of one line; the shift register 350b may output the first pixel data PD1 and the second pixel data PD2];
a digital-to-analog converting circuit [e.g., Fig. 7A: 330b, DEC1, DEC2] configured to convert a digital signal [e.g., Fig. 7A: PD1] corresponding to the pixel image data into an analog signal [e.g., Paragraph 93: The first decoder DECI may select a gray voltage corresponding to the first pixel data PD1 from among gray voltages V0 to V255 and may output the selected gray voltage as a first pixel signal];
a buffer circuit [e.g., Fig. 7A: 310b, 340b; SA1] including an input switch [e.g., Fig. 7A: ISW1, ISW2, ICSW; Paragraph 94: The first input switch ISW1 may be turned on or off in response to a first input control signal ICON1; Paragraph 94: the second input switch ISW2 and the input connection switch ICSW may be turned on or off in response to a second input control signal ICON2] controlling connection with the digital-to-analog converting circuit [e.g., Paragraph 95: the first input switch ISW1 and the second input switch ISW2 may be turned on, and the input connection switch ICSW may be turned off] and configured to transmit the analog signal to a pixel [Figs. 1-4B, 6: PX; Paragraph 72: When the scan clock signal CLK is applied to the scan line SL, the first pixel signal used to charge the first data line DL1 may be provided to the first pixel PX1]; and
an output switch [e.g., Fig. 7A: OSW1, OSW2, CSW] configured to control connection between a data line [e.g., Figs. 2-4B: DL1, DL2] connected [e.g., via Fig. 7A: OP1, OP2] to the pixel and the buffer circuit [e.g., Paragraph 65: The first output switch OSW1 may be connected between an output node the first amplifier SA1 and the first output pad OP1; The connection switch CSW may be connected between the first output pad OP1 and the second output pad OP2],
wherein the input switch is turned off [e.g., Fig. 7A: ISW1 off, ISW2 off, ICSW off; Fig. 7B: ISW1 off; Fig. 7C: ISW2 off, ICSW off; Fig. 11: both EN1 & CON on/off, both EN2 & CON on/off] for a first time period [e.g., Paragraph 96: the first input switch ISW1 may be turned off, the second input switch ISW2 and the input connection switch ICSW may be turned on during the first period of the horizontal driving period; Fig. 7B] to delay the analog signal by the first time period and input the delayed analog signal [e.g., Fig. 7A: ISW2 on, ICSW on; Fig. 7B: ISW1 on; Fig. 11: only one of EN1 & CON on, only one of EN2 & CON on] to the buffer circuit [e.g., Paragraph 94: the first input control signal ICON1 may be a signal generated through an exclusive OR operation of the first enable signal EN1 and the connection control signal CON, and the second input control signal ICON2 may be a signal generated through an exclusive OR operation of the second enable signal EN2 and the connection control signal CON; Paragraph 96: the first input switch ISW1 is turned on, the second input switch ISW2 and the input connection switch ICSW are turned off during the second period of the horizontal driving period, and thus, the first decoder DEC1 may provide the first pixel signal to the first amplifier SA1; Fig. 7C].
The first pixel signal is available from the head of the horizontal driving period — the pixel data is presented at the period boundary [e.g., Paragraph 92: may output the pixel data of one line in synchronization with the synchronization signal Hsync; Paragraph 103: In response to the horizontal synchronization signal Hsync, the first pixel data PD1 and the second pixel data PD2 may be provided as the first input data Din1] and DEC1's selection is withheld from SA1 by the open ISW1 throughout the first period [Fig. 7B: DEC1 drawn active, ISW1 open] — so the analog signal delivered upon turn-on is the same first pixel signal, delayed by the first period (e.g., see Paragraphs 55-115).
Regarding claim 3, Kong discloses a timing control circuit [e.g., Fig. 1: timing controller; Figs. 2, 18: 210; Fig. 2: 210a; Fig. 1: 200; Paragraph 66: the control signals may include the first enable signal EN1, the second enable signal EN2, the first output control signal OC1, the second output control signal OC2, and the connection control signal CON] configured to generate a latch output signal [e.g., Fig. 1: CTRL2; Paragraph 161: horizontal synchronization signals and timing signals; Paragraph 92: the synchronization signal Hsync; Paragraph 92: a timing signal generated based on the horizontal synchronization signal Hsync] at each horizontal time [e.g., Figs. 11-12: H; Fig. 5: 1H],
wherein the digital signal is output from the latch circuit according to the latch output signal [Paragraph 92: The shift register 350b may store the image data DATA, for example, pixel data of one line, which is provided by the timing controller 300 (of FIG. 1) and may output the pixel data of one line in synchronization with the synchronization signal Hsync (of FIG. 5) or a timing signal generated based on the horizontal synchronization signal Hsync],
wherein the input switch is turned off for the first time period from the time when the digital signal is output [e.g., Paragraph 96: turned off... during the first period of the horizontal driving period; Paragraph 79: may coarse-drive the first data line DL1 and the second data line DL2 during a first period P1 of one horizontal driving period 1H; Fig. 5: P1 commencing at the 1H boundary at which Din1 is presented] (e.g., see Fig. 11; Paragraph 109-115).
Regarding claim 4, Kong discloses the timing control circuit is further configured to generate an output enable signal [e.g., Fig. 11: OC1, OC2, CON; see Paragraphs 65-70; Paragraph 66: the first output control signal OC1, the second output control signal OC2] that controls on/off of the output switch [e.g., Paragraph 65; Fig. 7A: OSW1, OSW2],
wherein the output switch is turned off [e.g., Fig. 7A: ISW1 off, ISW2 off, ICSW off, OSW1 off, OSW2 off, CSW off; Fig. 7B: ISW1 off, OSW2 off; Fig. 7C: ISW2 off, ICSW off, OSW2 off; Fig. 11: both EN1 & CON on/off, both EN2 & CON on/off, OC1 off, OC2 off, CON off] for the first time period from the time when the digital signal is output according to the output enable signal [e.g., Paragraph 80: the first output control signal OC1 is logic high, and the second output control signal OC2 is logic low; Fig. 5: OC2].
The second output switch OSW2 is thereby held off, per the output control signal OC2, from the head of the horizontal driving period at which the pixel data is presented [e.g., Paragraph 92; Paragraph 103], and therefore is turned off for (at least) the first time period from the time when the digital signal is output (e.g., see Paragraph 109-115).
Regarding claim 5, Kong discloses the input switch and the output switch operate in synchronization [e.g., Paragraph 94: the second input switch ISW2 and the input connection switch ICSW may be turned on or off in response to a second input control signal ICON2; Paragraph 94: the second input control signal ICON2 may be a signal generated through an exclusive OR operation of the second enable signal EN2 and the connection control signal CON; Paragraph 80: the first enable signal EN1 may be logic high, and the second enable signal EN2 may be logic low].
With EN2 logic low, the exclusive-OR relation makes ICON2 track CON — the very signal that controls the connection switch CSW — so the input-side switches ISW2/ICSW and the output-side switch CSW switch identically and simultaneously: on together during the first period [e.g., Paragraph 81: the connection control signal CON may be logic high; Paragraph 96: the second input switch ISW2 and the input connection switch ICSW may be turned on during the first period of the horizontal driving period] and off together during the second period [e.g., Paragraph 82: the connection control signal CON may be logic low; Paragraph 96: are turned off during the second period of the horizontal driving period].
The synchronization is thus established by the control-signal architecture itself, not merely observed coincidence [e.g., Fig. 7A: ISW2, ICSW, and CSW drawn controlled by the common connection control signal CON; ISW1 by its complement CONB] (e.g., see Figs. 7ABC, 11; Paragraph 90-115).
Regarding claim 8, Kong discloses a parasitic capacitor [e.g., Fig. 6: Cp (capacitor drawn on the data line DL, outside the pixel PX); Paragraph 84: The data charging time TDC may be set based on a full-range transition of pixel data; Paragraph 84: a time required to charge the first data line DL1 and the second data line DL2 -- the drawn Cp is the line capacitance the amplifiers must charge each horizontal period] is formed on the data line,
wherein the output switch, when turned off [e.g., Fig. 7A: OSW1 off, OSW2 off, CSW off; Fig. 7B: OSW2 off; Fig. 7C: OSW2 off; Fig. 11: OC1 off, OC2 off, CON off], is configured to release a connection between the parasitic capacitor formed on the data line and the buffer circuit [e.g., Paragraph 65 (OSW1, OSW2, and CSW are connected in series between the amplifier output nodes and the output pads OP1/OP2 to which the data lines connect); Paragraph 80: the second output control signal OC2 is logic low (OSW2 open, releasing the second data line's capacitance from SA2); Paragraph 82: the connection control signal CON may be logic low (CSW open, releasing the second data line's capacitance from SA1 during the second period)] (e.g., see Figs. 7ABC, 11; Paragraph 90-115).
Regarding claim 9, Kong discloses the input switch is,
in a first mode [e.g., Fig. 7A: ISW2 on, ICSW on; Fig. 7B: ISW1 on; Fig. 11: only one of EN1 & CON on, only one of EN2 & CON on; Paragraph 95: driven in a normal operation mode], continuously turned on during the horizontal time [e.g., Paragraph 95: the first input switch ISW1 and the second input switch ISW2 may be turned on, and the input connection switch ICSW may be turned off -- no off event during the horizontal driving period is disclosed in the normal operation mode], and
in a second mode [e.g., Fig. 7A: ISW1 off, ISW2 off, ICSW off; Fig. 7B: ISW1 off; Fig. 7C: ISW2 off, ICSW off; Fig. 11: both EN1 & CON on/off, both EN2 & CON on/off; Paragraph 96: driven in a low-power operation mode], turned off during part of the horizontal time [e.g., Paragraph 96: the first input switch ISW1 may be turned off, the second input switch ISW2 and the input connection switch ICSW may be turned on during the first period of the horizontal driving period] (e.g., see Figs. 7ABC, 11; Paragraph 90-115).
Claim Rejections - 35 USC § 103
The factual inquiries set forth in Graham v. John Deere Co., 383 U.S. 1, 148 USPQ 459 (1966), that are applied for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102 of this title, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
This application currently names joint inventors. In considering patentability of the claims the examiner presumes that the subject matter of the various claims was commonly owned as of the effective filing date of the claimed invention(s) absent any evidence to the contrary. Applicant is advised of the obligation under 37 CFR 1.56 to point out the inventor and effective filing dates of each claim that was not commonly owned as of the effective filing date of the later invention in order for the examiner to consider the applicability of 35 U.S.C. 102(b)(2)(C) for any potential 35 U.S.C. 102(a)(2) prior art against the later invention.
Claims 6-7 and 10 are rejected under 35 U.S.C. 103 as being unpatentable over Kong et al (US 2018/0315390 A1) in view of Hsueh et al (US 2011/0090198 A1).
Regarding claim 6, Kong doesn’t appear to expressly disclose the digital-to-analog converting circuit includes a plurality of switches, as instantly claimed.
Kong's decoders select among the gray voltages without reciting the selecting switch structure [e.g., Paragraph 93].
However, Hsueh discloses the digital-to-analog converting circuit includes a plurality of switches [e.g., Fig. 2: illustrated switches; Fig. 6: 604; Fig. 6: 600, 602, 604; Paragraph 24: the decoder 600 includes a plurality of transistors 602 arranged in a plurality of columns]
each connected to a plurality of gamma voltages [e.g., Paragraphs 2-6, 24-28: voltages; Paragraph 22 (the decoder receives the R-string tap voltage levels, each on a separate conductor line — the gray-scale (gamma) voltage set of an LCD column driver)],
wherein on/off of the plurality of switches is determined according to the digital signal [e.g., Paragraph 25: The turning on and off of each of the transistors 602 in a column is controlled by the same bit of the multi-bit digital input code],
wherein one of the plurality of gamma voltages is determined as the analog signal according to on/off state of the plurality of switches (e.g., see Paragraphs 2-6, 20-28).
Kong and Hsueh are analogous art, because they are from the shared inventive field of display driving devices.
Therefore, it would have been obvious to one having ordinary skill in the art at the time of filing to combine Hsueh’s circuitry with Kong’s DAC unit, so as to maintain full resolution and brightness of the display.
It would have been obvious to a person of ordinary skill in the art at the time of filing to implement Kong's decoders DEC1 /DEC2 — which select among gray voltages VO to V255 [e.g., Kong, Paragraph 93] — using Hsueh's transistor-switch decoder structure, so as to maintain full resolution and brightness of the display [e.g., Hsueh, Paragraph 29: for compensating for the reduced brightness level] while reducing the conductor-line count of the decoder [e.g., Hsueh, Paragraph 22: 160 conductive lines are used to connect the DAC decoder and summing circuitry 400A to the two PDACs and two NDACs].
All claimed elements were known; the combination applies a known decoder implementation to Kong's decoder function by known methods with no change in the respective functions, yielding predictable results. KSR Int'l Co. v. Teleflex Inc., 550 U.S. 398 (2007).
It would have been obvious to one of ordinary skill in the art at the time of filing because all the claimed elements were known in the prior art and one skilled in the art could have combined Hsueh’s circuitry with Kong’s DAC unit as claimed by known methods with no change in their respective functions, and the combination would have yielded predictable results to one of ordinary skill in the art at the time of the filing. See KSR International Co. v. Teleflex Inc., et al., Docket No. 04-1350 (U.S. 30 April 2007).
Regarding claim 7, Hsueh discloses the latch circuit [e.g., Fig. 1: 106; Fig. 3: 306], the digital-to-analog converting circuit [e.g., Fig. 1: 110; Fig. 3: 400] and the buffer circuit [e.g., Fig. 1: 112; Figs. 4B, 5A: 406] share a ground [e.g., Figs. 4B, 5A: illustrated ground; Paragraphs 29, 33: ground].
Hsueh's single LCD column driver integrates the data-storage, conversion, and buffering chain [e.g., Paragraph 20: shift registers 302, input registers 304, data latches 306, level shifters 308, and DAC decoder and summing circuitry 400; Figs. 1, 3], with the converting/buffering circuitry referenced to ground [e.g., Paragraphs 29, 33 (switches coupled to ground within the DAC decoder and summing circuitry); Figs. 4B, 5A].
In the combination, Kong's latch, decoder, and amplifier chain [e.g., Kong, Fig. 7A] implemented as a unitary display driving circuit shares the common ground reference in the manner Hsueh shows, for the same reasons and with the same predictable results articulated for claim 6 (e.g., see Paragraphs 2-6, 20-37).
Regarding claim 10, Kong does not expressly disclose the recited output connection switch.
However, Hsueh disclose the buffer circuit further includes an output connection switch [e.g., Figs. 4B, 5A: 420] that operates on/off in a manner opposite to the on/off of the input switch [e.g., Figs. 4B, 5A: 414; Paragraph 34: switches 408, 416, and 420 open and close together, and switches 410 and 414 open and close together, but switches 408, 416, and 420 are not open at the same time switches 410 and 414 are open, and vice versa],
wherein the output connection switch is configured to maintain the input/output of the buffer circuit at the voltage of the data line [e.g., Figs. 4B, 5A: LCD Column -- the closed switch 420 configuring the amplifier as a follower whose input and output equal the voltage driven to the panel line; Paragraph 34: opamp 406 acts as a unity gain buffer outputting the output of MSB DAC decoder 402 to the LCD column] during the time when the input switch is turned off (e.g., see Paragraphs 29-35).
It would have been obvious to combine Hsueh's oppositely-phased connection switch arrangement with Kong's buffer circuit for the reasons and with the predictable results articulated for claim 6 (e.g., see Hsueh, Paragraphs 29-35).
Claim 10 is additionally rejected under 35 U.S.C. 103 as being unpatentable over Kong et al (US 2018/0315390 A1) in view of Kawagoshi (US 2011/0018853 A1).
Regarding claim 10, Kong does not expressly disclose the buffer circuit further
including an output connection switch that operates on/off in a manner opposite to the on/off of the input switch, wherein the output connection switch is configured to maintain the input/output of the buffer circuit at the voltage of the data line during the time when the input switch is turned off — in the integrated relationship now required through amended claim 1, i.e., in combination with an input switch that is turned off for a first time period to delay the analog signal into the buffer circuit.
Kawagoshi discloses exactly this integrated switch scheme in a signal line driving circuit.
Kawagoshi's channel comprises an amplifier, an input switch, an output switch, and a charge share switch in the claimed topology [e.g., Paragraph 27: includes an odd-numbered amplifier AMP11, an even-numbered amplifier AMP12, charge share switches SW11, SW12, and SW13, output switches SW14 and SW15, and input switches SW16 and SW17; Paragraph 29: A non-inverting input terminal of the odd-numbered amplifier AMP11 is connected to the input switch SW16; Fig. 1],
the connection switch tied between the amplifier's input and the pixel-side terminal of the output switch [e.g., Paragraph 33: The charge share switch SW12 is connected between a node between the output switch SW14 and the odd-numbered output terminal SKOUT11 and a node between the input switch SW16 and the noninverting input terminal of the odd-numbered amplifier AMP11], the terminal being the panel data line [e.g., Paragraph 29: The odd-numbered output terminal SKOUT11 is connected to a load F11 serving as a capacitive load of a liquid crystal panel].
The connection switch operates on/off opposite to the input switch: during the operation period at the head of each horizontal period [e.g., Paragraph 37: A charge sharing operation period is a period between a rising edge of the strobe signal STB and a falling edge of the strobe signal STB; Paragraph 37: the charge sharing operation period is provided at the beginning of one horizontal period, i.e., immediately after the switching of one horizontal period],
the connection switches are on while the input and output switches are off [e.g., Paragraph 17: During the charge sharing operation, the first charge share switch and the second charge share switch are turned on, and at the same time, the first output switch and the first input switch are turned off; Paragraph 38: the output switches SW14 and SW15 and the input switches SW16 and SW17 are turned off], and
all reverse together at the close of the period [e.g., Paragraph 40: in response to the falling edge of the strobe signal STB, the charge share switches SW11, SW12, and SW13 are turned off, and at the same time, the output switches SW14 and SW15 and the input switches SW16 and SW17 are turned on].
While the input switch is off, the connection switch maintains the buffer's input/output at the voltage of the data line [e.g., Paragraph 38: allows the electric charge of the loads F11 and F12 to be fed back to the non-inverting input terminals; Paragraph 17: This allows an output voltage of the first amplifier to be equal to a load voltage after completion of the charge sharing operation; Paragraph 40: the output voltages of the odd-numbered amplifier AMP 11 and the even-numbered amplifier AMP 12 become equal to the load voltage], and
upon turn-on the delayed analog signal from the pre-stage converter is input to the amplifier [e.g., Paragraph 41: the inputs of the odd-numbered amplifier AMP 11 and the even-numbered amplifier AMP 12 are connected to a DA converter (not shown) which is provided at the pre-stage].
Kong and Kawagoshi are analogous art from the shared field of display data-line (source) driving circuits.
It would have been obvious to a person of ordinary skill in the art at the time of filing to incorporate Kawagoshi's oppositely-phased connection switch, tied to the pixel-side terminal of the output switch, into Kong's buffer circuit and to operate it opposite to Kong's input switching during the input off period, in order to keep the amplifier's input from floating and to make the amplifier's output equal to the load voltage at reconnection, thereby suppressing output fluctuation and reducing peak circuit current [e.g., Kawagoshi, Paragraph
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17: the peak circuit current flowing immediately after the charge sharing operation can be reduced; Fig. 2: AMPLIFIER GND CURRENT (suppressed spikes; contrast prior-art Fig. 6)] — benefits directly applicable to Kong's driver, whose low-power scheme creates precisely such disconnect/ reconnect events each horizontal period, and squarely within Kong's stated objective of reducing driver power [e.g., Kong, Paragraph 3: research into various technologies for reducing power consumed by display driving circuits has been conducted; Paragraph 115: a driving load of the amplifier is reduced, and image quality degradation may be prevented].
All claimed elements were known; the combination unites them by known methods with no change in their respective functions and yields predictable results. KSR Int'l co. v. Teleflex Inc., 550 U.S. 398 (2007).
It would have been obvious to one of ordinary skill in the art at the time of filing because all the claimed elements were known in the prior art and one skilled in the art could have combined Kawagoshi's output connection switch switch with Kong's buffer circuit as claimed by known methods with no change in their respective functions, and the combination would have yielded predictable results to one of ordinary skill in the art at the time of the filing. See KSR International Co. v. Teleflex Inc., et al., Docket No. 04-1350 (U.S. 30 April 2007).
Necessity of the new ground. This ground is necessitated by Applicant's amendment. Before the amendment, claim 10 did not require the subject matter of original claim 2; as amended through claim 1, claim 10 for the first time requires the output connection switch to operate opposite an input switch that is turned off for a first time period to delay the analog signal into the buffer circuit — an integrated three-switch timing relationship not previously required of claim 10. Kawagoshi is applied to address that newly required relationship.
Claim 10 is additionally rejected under 35 U.S.C. 103 as being unpatentable over Kong et al (US 2018/0315390 A1) in view of the Applicant’s Admission of Obviousness.
Regarding claim 10, Kong doesn’t appear to expressly disclose the buffer circuit further includes an output connection switch that operates on/off in a manner opposite to the on/off of the input switch, wherein the output connection switch is configured to maintain the input/output of the buffer circuit at the voltage of the data line during the time when the input switch is turned off, as instantly claimed.
However, the above claimed subject matter encompasses elected Species 2 (i.e., the buffer circuit of Fig. 7).
The Applicant admits, “the embodiments represent obvious variations of a common buffer architecture and do not constitute independent and distinct inventions” (see page 7 of the 19 February 2026 Election).
Therefore, it would have been obvious to one having ordinary skill in the art at the time of filing to combine the Applicant’s admitted obvious output connection switch with Kong’s buffer circuit, so as to provide an “obvious variation of a common buffer architecture.”
Moreover, it would have been obvious to one of ordinary skill in the art at the time of filing because all the claimed elements were known in the prior art and one skilled in the art could have combined the Applicant’s admitted obvious output connection switch with Kong’s buffer circuit as claimed by known methods with no change in their respective functions, and the combination would have yielded predictable results to one of ordinary skill in the art at the time of the filing. See KSR International Co. v. Teleflex Inc., et al., Docket No. 04-1350 (U.S. 30 April 2007).
Response to Arguments
Applicant's arguments filed on 1 June 2026 have been fully considered but they are not persuasive.
Applicant argues that Kong shows, at most, "periods during which switches are turned on or off as part of circuit control operations," and does not disclose that the analog signal is "intentionally delayed for a first time period and thereafter supplied to a buffer circuit."
Kong's express disclosure is to the contrary.
In the low-power operation mode, the first input switch ISW1 is "turned off... during the first period of the horizontal driving period" while the second decoder's signal is amplified, and then "the first input switch ISW1 is turned on... during the second period of the horizontal driving period, and thus, the first decoder DEC1 may provide the first pixel signal to the first amplifier SA1" [Paragraph 96].
The first pixel signal exists from the head of the period: the pixel data of one line is output "m synchronization with the synchronization signal Hsync" [Paragraph 92] and presented at the horizontal boundary [Paragraph 103], and DEC1's corresponding gray-voltage selection [Paragraph 93] is withheld from the amplifier by the open ISW1 for the entirety of the first period [Fig. 7B].
The withholding is deliberate: it is the defining operation of Kong's coarse-then-fine scheme, in which the amplifier must first output the second pixel signal before receiving the first [Paragraphs 81-83].
The analog signal is therefore delayed by the first period and input to the buffer circuit upon the switch's turn-on — precisely the claimed operation.
Applicant's contention that the claim requires "delaying the analog signal itself" as something distinct from the off period of the input switch is inconsistent with the broadest reasonable interpretation of the claim in light of the specification.
The specification discloses no delay mechanism other than the off state of the input switch: "The buffer circuit 230 may turn off the input switch for a predetermined first time so that the analog signal is input to the buffer circuit 230 with a delay of the first time" [Specification, Paragraph 69], with the conversion permitted to complete during that same window — the converting circuit "may complete the conversion operation for the digital signal into an analog signal before the analog signal is input to the buffer circuit 230a—for example, before the first time ends" [Specification, Paragraph 92].
Under the claim as properly construed, holding the input switch off for the first time period such that the (settled) analog signal reaches the buffer circuit only thereafter is delaying the analog signal by the first time period.
Kong's operation meets the limitation for the reasons above; a construction requiring more would exclude the specification's own embodiments.
Applicant's arguments with respect to claims 1 and 3-10 have been considered but are moot in view of any new ground(s) of rejection.
Conclusion
Applicant's amendment necessitated any new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
For example: Applicant's amendment incorporated the subject matter of original claim 2 into claim 1, thereby changing the scope of claims 6-10, which previously did not require that subject matter. The sole new ground of rejection in this action is applied to amended claim 10 and was necessitated by that amendment; all remaining grounds are maintained from the March 11, 2026 action against claims of identical scope, with additional citations from the same references provided in response to Applicant's arguments. Accordingly, the action may properly be made final under MPEP 706.07(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any extension fee pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to Jeff Piziali whose telephone number is (571)272-7678. The examiner can normally be reached on Monday - Friday (7:30AM - 4PM). The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/Jeff Piziali/
Primary Examiner, Art Unit 2628
24 July 2026
Prosecution Insights