DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Priority
Receipt is acknowledged of certified copies of papers submitted under 35 U.S.C. 119(a)-(d), which papers have been placed of record in the file.
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claims 1-5, 8 and 9 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Kong et al (US 2018/0315390 A1).
Regarding claim 1, Kong discloses a data driving device comprising:
a latch circuit [e.g., Fig. 7A: 350b] configured to store pixel image data [e.g., Fig. 1: DATA; Paragraph 92: shift register 350b may store the image data DATA];
a digital-to-analog converting circuit [e.g., Fig. 7A: 330b] configured to convert a digital signal [e.g., Fig. 7A: PD] corresponding to the pixel image data into an analog signal [e.g., Paragraph 92: first decoder DEC1 may select a gray voltage corresponding to the first pixel data PD1 from among gray voltages V0 to V255 and may output the selected gray voltage as a first pixel signal];
a buffer circuit [e.g., Fig. 7A: 310b, 340b] including an input switch [e.g., Fig. 7A: ISW1, ISW2, ICSW] controlling connection with the digital-to-analog converting circuit and configured to transmit the analog signal to a pixel [Figs. 1-4B, 6: PX]; and
an output switch [e.g., Fig. 7A: OSW1, OSW2, CSW] configured to control connection between a data line [Figs. 1-4B, 6: DL] connected [e.g., via Fig. 7A: OP1, OP2] to the pixel and the buffer circuit (e.g., see Paragraphs 32-164).
Regarding claim 2, Kong discloses the input switch is turned off [e.g., Fig. 7A: ISW1 off, ISW2 off, ICSW off; Fig. 7B: ISW1 off; Fig. 7C: ISW2 off, ICSW off; Fig. 11: both EN1 & CON on/off, both EN2 & CON on/off] for a first time period to delay the analog signal by the first time period and input the delayed analog signal [e.g., Fig. 7A: ISW2 on, ICSW on; Fig. 7B: ISW1 on; Fig. 11: only one of EN1 & CON on, only one of EN2 & CON on] to the buffer circuit [e.g., Paragraph 94: the first input control signal ICON1 may be a signal generated through an exclusive OR operation of the first enable signal EN1 and the connection control signal CON, and the second input control signal ICON2 may be a signal generated through an exclusive OR operation of the second enable signal EN2 and the connection control signal CON].
Regarding claim 3, Kong discloses a timing control circuit [e.g., Fig. 1: timing controller; Figs. 2, 18: 210] configured to generate a latch output signal [e.g., Fig. 1: CTRL2; Paragraph 161: horizontal synchronization signals and timing signals] at each horizontal time [e.g., Figs. 11-12: H],
wherein the digital signal is output from the latch circuit according to the latch output signal [Paragraph 92: The shift register 350b may store the image data DATA, for example, pixel data of one line, which is provided by the timing controller 300 (of FIG. 1) and may output the pixel data of one line in synchronization with the synchronization signal Hsync (of FIG. 5) or a timing signal generated based on the horizontal synchronization signal Hsync],
wherein the input switch is turned off for the first time period from the time when the digital signal is output (e.g., see Fig. 11; Paragraph 109-115).
Regarding claim 4, Kong discloses the timing control circuit is further configured to generate an output enable signal [e.g., Fig. 11: OC1, OC2, CON; see Paragraphs 65-70] that controls on/off of the output switch,
wherein the output switch is turned off [e.g., Fig. 7A: ISW1 off, ISW2 off, ICSW off, OSW1 off, OSW2 off, CSW off; Fig. 7B: ISW1 off, OSW2 off; Fig. 7C: ISW2 off, ICSW off, OSW2 off; Fig. 11: both EN1 & CON on/off, both EN2 & CON on/off, OC1 off, OC2 off, CON off] for the first time period from the time when the digital signal is output according to the output enable signal (e.g., see Paragraph 109-115).
Regarding claim 5, Kong discloses the input switch and the output switch operate in synchronization (e.g., see Figs. 7ABC, 11; Paragraph 90-115).
Regarding claim 8, Kong discloses a parasitic capacitor [e.g., Fig. 6: Cp] is formed on the data line,
wherein the output switch, when turned off [e.g., Fig. 7A: OSW1 off, OSW2 off, CSW off; Fig. 7B: OSW2 off; Fig. 7C: OSW2 off; Fig. 11: OC1 off, OC2 off, CON off], is configured to release a connection between the parasitic capacitor formed on the data line and the buffer circuit (e.g., see Figs. 7ABC, 11; Paragraph 90-115).
Regarding claim 9, Kong discloses the input switch is,
in a first mode [e.g., Fig. 7A: ISW2 on, ICSW on; Fig. 7B: ISW1 on; Fig. 11: only one of EN1 & CON on, only one of EN2 & CON on], continuously turned on during the horizontal time, and
in a second mode [e.g., Fig. 7A: ISW1 off, ISW2 off, ICSW off; Fig. 7B: ISW1 off; Fig. 7C: ISW2 off, ICSW off; Fig. 11: both EN1 & CON on/off, both EN2 & CON on/off], turned off during part of the horizontal time (e.g., see Figs. 7ABC, 11; Paragraph 90-115).
Claim Rejections - 35 USC § 103
The factual inquiries set forth in Graham v. John Deere Co., 383 U.S. 1, 148 USPQ 459 (1966), that are applied for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102 of this title, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
This application currently names joint inventors. In considering patentability of the claims the examiner presumes that the subject matter of the various claims was commonly owned as of the effective filing date of the claimed invention(s) absent any evidence to the contrary. Applicant is advised of the obligation under 37 CFR 1.56 to point out the inventor and effective filing dates of each claim that was not commonly owned as of the effective filing date of the later invention in order for the examiner to consider the applicability of 35 U.S.C. 102(b)(2)(C) for any potential 35 U.S.C. 102(a)(2) prior art against the later invention.
Claims 6-7 and 10 are rejected under 35 U.S.C. 103 as being unpatentable over Kong et al (US 2018/0315390 A1) in view of Hsueh et al (US 2011/0090198 A1).
Regarding claim 6, Kong doesn’t appear to expressly disclose the digital-to-analog converting circuit includes a plurality of switches, as instantly claimed.
However, Hsueh discloses the digital-to-analog converting circuit includes a plurality of switches [e.g., Fig. 2: illustrated switches; Fig. 6: 604] each connected to a plurality of gamma voltages [e.g., Paragraphs 2-6, 24-28: voltages], wherein on/off of the plurality of switches is determined according to the digital signal, wherein one of the plurality of gamma voltages is determined as the analog signal according to on/off state of the plurality of switches (e.g., see Paragraphs 2-6, 24-28).
Kong and Hsueh are analogous art, because they are from the shared inventive field of display driving devices.
Therefore, it would have been obvious to one having ordinary skill in the art at the time of filing to combine Hsueh’s circuitry with Kong’s DAC unit, so as to maintain full resolution and brightness of the display.
Moreover, it would have been obvious to one of ordinary skill in the art at the time of filing because all the claimed elements were known in the prior art and one skilled in the art could have combined Hsueh’s circuitry with Kong’s DAC unit as claimed by known methods with no change in their respective functions, and the combination would have yielded predictable results to one of ordinary skill in the art at the time of the filing. See KSR International Co. v. Teleflex Inc., et al., Docket No. 04-1350 (U.S. 30 April 2007).
Regarding claim 7, Hsueh discloses the latch circuit [e.g., Fig. 1: 106; Fig. 3: 306], the digital-to-analog converting circuit [e.g., Fig. 1: 110; Fig. 3: 400] and the buffer circuit [e.g., Fig. 1: 112; Figs. 4B, 5A: 406] share a ground [e.g., Figs. 4B, 5A: illustrated ground; Paragraphs 29, 33: ground] (e.g., see Paragraphs 2-6, 20-37).
Regarding claim 10, Hsueh disclose the buffer circuit further includes an output connection switch [e.g., Figs. 4B, 5A: 420] that operates on/off in a manner opposite to the on/off of the input switch [e.g., Figs. 4B, 5A: 414; Paragraph 34: switches 408, 416, and 420 are not open at the same time switches 410 and 414 are open, and vice versa], wherein the output connection switch is configured to maintain the input/output of the buffer circuit at the voltage of the data line [e.g., Figs. 4B, 5A: LCD Column] during the time when the input switch is turned off (e.g., see Paragraphs 29-35).
Claim 10 is additionally rejected under 35 U.S.C. 103 as being unpatentable over Kong et al (US 2018/0315390 A1) in view of the Applicant’s Admission of Obviousness.
Regarding claim 10, Kong doesn’t appear to expressly disclose the buffer circuit further includes an output connection switch that operates on/off in a manner opposite to the on/off of the input switch, wherein the output connection switch is configured to maintain the input/output of the buffer circuit at the voltage of the data line during the time when the input switch is turned off, as instantly claimed.
However, the above claimed subject matter encompasses elected Species 2 (i.e., the buffer circuit of Fig. 7).
The Applicant admits, “the embodiments represent obvious variations of a common buffer architecture and do not constitute independent and distinct inventions” (see page 7 of the 19 February 2026 Election).
Therefore, it would have been obvious to one having ordinary skill in the art at the time of filing to combine the Applicant’s admitted obvious output connection switch with Kong’s buffer circuit, so as to provide an “obvious variation of a common buffer architecture.”
Moreover, it would have been obvious to one of ordinary skill in the art at the time of filing because all the claimed elements were known in the prior art and one skilled in the art could have combined the Applicant’s admitted obvious output connection switch with Kong’s buffer circuit as claimed by known methods with no change in their respective functions, and the combination would have yielded predictable results to one of ordinary skill in the art at the time of the filing. See KSR International Co. v. Teleflex Inc., et al., Docket No. 04-1350 (U.S. 30 April 2007).
Election/Restrictions
Applicant's election with traverse of Group I in the reply filed on 19 February 2026 is acknowledged. The traversal is on the ground(s) that “The Claims Define a Single General Inventive Concept.” This is not found persuasive.
The groups of inventions listed in the 23 December 2025 Office Action do not relate to a single general inventive concept under PCT Rule 13.1 because, under PCT Rule 13.2, they lack the same or corresponding special technical features for the following reasons:
Any international application must relate to one invention only or to a group of inventions/species so linked as to form a single general inventive concept.
Where a group of inventions is claimed the requirement of unity of invention referred to in Rule 13.1 shall be fulfilled only when there is a technical relationship among those inventions involving one or more of the same or corresponding special technical features.
The expression “special technical features” means those technical features that define a contribution which each of the claimed inventions/species, considered as a whole, makes over the prior art. See MPEP 1850.
The inventions lack unity of invention because even though the inventions require the technical feature of a digital-to-analog converting circuit, this technical feature is not a special technical feature as it does not make a contribution over the prior art in view of the grounds of rejection in this Office Action.
As demonstrated by the grounds of rejection in this Office Action, at least one independent claim of the application does not avoid the prior art, therefore, the special technical feature of the application is anticipated by or obvious in view of the prior art.
Consequently, the inventions/species listed above do not relate to a single general inventive concept under PCT Rule 13.1.
The requirement is still deemed proper and is therefore made FINAL.
Applicant's election with traverse of Species 2 in the reply filed on 19 February 2026 is acknowledged. The traversal is on the ground(s) that “the embodiments represent obvious variations of a common buffer architecture and do not constitute independent and distinct inventions” (see page 7 of the 19 February 2026 Election). This is found persuasive.
The requirement to elect a Species is hereby withdrawn, because the Applicant admits the Species are obvious variants of each other.
Claims 11-20 are withdrawn from further consideration pursuant to 37 CFR 1.142(b), as being drawn to at least a nonelected invention, there being no allowable generic or linking claim. Applicant timely traversed the restriction (election) requirement in the reply filed on 19 February 2026.
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure. The documents listed on the attached 'Notice of References Cited' are cited to further evidence the state of the art pertaining to data driving devices.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to Jeff Piziali whose telephone number is (571)272-7678. The examiner can normally be reached on Monday - Friday (7:30AM - 4PM). The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/Jeff Piziali/
Primary Examiner, Art Unit 2628
6 March 2026