DETAILED ACTION
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA . In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
Drawings
The drawings are objected to because there are two figures labeled “Fig. 7C”. Corrected drawing sheets in compliance with 37 CFR 1.121(d) are required in reply to the Office action to avoid abandonment of the application. Any amended replacement drawing sheet should include all of the figures appearing on the immediate prior version of the sheet, even if only one figure is being amended. The figure or figure number of an amended drawing should not be labeled as “amended.” If a drawing figure is to be canceled, the appropriate figure must be removed from the replacement sheet, and where necessary, the remaining figures must be renumbered and appropriate changes made to the brief description of the several views of the drawings for consistency. Additional replacement sheets may be necessary to show the renumbering of the remaining figures. Each drawing sheet submitted after the filing date of an application must be labeled in the top margin as either “Replacement Sheet” or “New Sheet” pursuant to 37 CFR 1.121(d). If the changes are not accepted by the examiner, the applicant will be notified and informed of any required corrective action in the next Office action. The objection to the drawings will not be held in abeyance.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale or otherwise available to the public before the effective filing date of the claimed invention.
Claims 1-2, 4, 9, 11, 16-17, 19, 26, and 28 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Sharma et al. (US Pub. No. 2017/0270062), hereinafter referred toa s Sharma.
Referring to claims 1 and 16, Sharma discloses a Peripheral Component Interconnect express (PCIe) retimer (a PCIe-compliant link, can include one or more retimers, [0052]), comprising: one or more Physical Layer Circuits (PHYs) configured to receive a PCIe data stream (Physical Layer…transmitter…receiver…packets, [0045-0048]); a symbol detector configured to detect an in-band retimer message embedded in one or more control symbols within the PCIe data stream (in-band retimer register access can be facilitated by enhancing training sequences (TSes) generated by the physical layer to allow communications to be embedded within these TSes for processing by the retimer(s)…encoding information (e.g., addresses, commands, data, etc.) within the training sequence for consumption and use by the retimer, [0059]); and data package extraction logic configured to, responsive to the in-band retimer message, monitor the PCIe data stream subsequent to the in-band retimer message to detect a plurality of data package bits and write the data package bits to a memory of the retimer (encoding information (e.g., addresses, commands, data, etc.) within the training sequence for consumption and use by the retimer…messages that may read or write data from/to registers of one or more retimers of a link, [0059-0060]).
As to claims 2 and 17, Sharma discloses the one or more control symbols comprise control skip ordered sets (encoding data in an instance of an enhanced SKP OS, [0061]), and wherein the data package extraction logic comprises the symbol detector configured to monitor the PCIe data stream by detecting one or more additional control skip ordered sets and to obtain the plurality of data package bits from the one or more additional control skip ordered sets (may monitor this register and may wait for some number of additional Enhanced SKP OS with the same data in the data field across the multiple Enhanced SKP Oses, [0065]).
As to claims 4 and 19, Sharma discloses the one or more control symbols comprise training ordered sets (enhanced training sequence (e.g., an ordered set (OS)), [0060]), and wherein the data package extraction logic comprises the symbol detector configured to monitor the PCIe data stream by detecting one or more additional training ordered sets and to obtain the plurality of data package bits from the one or more additional training ordered sets (in-band retimer register access can be facilitated by enhancing training sequences (TSes) generated by the physical layer to allow communications to be embedded within these TSes for processing by the retimer(s)…encoding information (e.g., addresses, commands, data, etc.) within the training sequence for consumption and use by the retimer, [0059]).
As to claim 9, Sharma discloses the one or more control symbols comprise control skip ordered sets (encoding data in an instance of an enhanced SKP OS, [0061]) and the data package extraction logic comprises a transaction layer packet decoder (fig. 2, Transaction Layer 205) configured to decode one or more transaction layer packets received in the PCIe data stream (a PCIe protocol stack including transaction layer 205, [0031]; transaction layer 205 is to provide an interface between a device's processing core and the interconnect architecture…a primary responsibility of the transaction layer 205 is the assembly and disassembly of packets, [0034]) subsequent to the in-band retimer message to obtain the plurality of data package bits (may monitor this register and may wait for some number of additional Enhanced SKP OS with the same data in the data field across the multiple Enhanced SKP Oses, [0065]).
As to claims 11 and 26, Sharma discloses a physical coding sublayer (PCS) receiver configured to receive the PCIe data stream and to decode the PCIe data stream to generate a PCS-decoded data stream (physical layer 220 includes logical sub block 221…logical sub-block 221 is responsible for the “digital” functions of Physical Layer 221. In this regard, the logical sub-block includes a transmit section to prepare outgoing information for transmission by physical sub-block 222, and a receiver section to identify and prepare received information before passing it to the Link Layer, [0046]), and wherein the one or more control symbols comprise control skip ordered sets (encoding data in an instance of an enhanced SKP OS, [0061]) and the data package extraction logic comprises a transaction layer packet decoder (fig. 2, Transaction Layer 205) configured to decode one or more transaction layer packets received in the PCS-decoded data stream (a PCIe protocol stack including transaction layer 205, [0031]; transaction layer 205 is to provide an interface between a device's processing core and the interconnect architecture…a primary responsibility of the transaction layer 205 is the assembly and disassembly of packets, [0034]) subsequent to the in-band retimer message to obtain the plurality of data package bits (may monitor this register and may wait for some number of additional Enhanced SKP OS with the same data in the data field across the multiple Enhanced SKP Oses, [0065]).
As to claim 28, Sharma discloses the PCIe retimer is a multi-tile PCIe retimer (PCIe-compliant link, can include one or more retimers, [0052]), the method further comprising receiving the PCIe data stream over one or more lanes (a link may aggregate multiple lanes denoted by xN, where N is any supported Link width, such as 1, 2, 4, 8, 12, 16, 32, 64, or wider, [0050]) coupled to a leader tile of the multi-tile retimer (two or more retimers (e.g., 515, 520) can be provided in series to further extend a link connecting upstream component 505 and downstream component 510, [0053]).
Allowable Subject Matter
Claims 6, 8, 10, 12, 14, 21, 23-24, 27, and 29 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure. The US Patent No. 11,949,629 of Musoll et al., the US Pub. No. 2022/0318094 of Jeon et al., and the US Patent No. 11,258,696 of Morrison et al. are pertinent to symbol communication in link retimers.
The examiner has cited particular column, line, and/or paragraph numbers in the references as applied to the claims above for the convenience of the applicant. Although the specified citations are representative of the teachings of the art and are applied to the specific limitations within the individual claim, other passages and figures may apply as well. It is respectfully requested from the applicant in preparing responses, to fully consider the references in its entirety as potentially teaching of all or part of the claimed invention, as well as the context of the passage as taught by the prior art or disclosed by the examiner.
The examiner requests, in response to this office action, support be shown for language added to any original claims on amendment and any new claims. That is, indicate support for newly added claim language by specifically pointing to page(s) and line number(s) in the specification and/or drawing figure(s). This will assist the examiner in prosecuting the application. When responding to this office action, applicant is advised to clearly point out the patentable novelty which he or she thinks the claims present, in view of the state of art disclosed by the references cited or the objections made. He or she must also show how the amendments avoid such references or objections. See 37 C.F.R. 1.111(c).
Applicants seeking an interview with the examiner, including WebEx Video Conferencing, are encouraged to fill out the online Automated Interview Request (AIR) form (http://www.uspto.gov/patent/uspto-automated-interview-request-air-form.html). See MPEP §502.03, §713.01(11) and Interview Practice for additional details.
Contact Information
Any inquiry concerning this communication or earlier communications from the examiner should be directed to ERIC T OBERLY whose telephone number is (571)272-6991. The examiner can normally be reached on M-F 800am-430pm (MT).
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Dr. Henry Tsai can be reached on (571) 272-4176. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/ERIC T OBERLY/ Primary Examiner, Art Unit 2184
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