Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claims 14-27 are presented for examination.
Specification
The attempt to incorporate subject matter into this application by reference to PCT/US2023/012345 is ineffective because it does not match the submitted PCT application number. The submitted PCT application number is PCT/KR2024/005515 (dated 2024-04-24).
The incorporation by reference will not be effective until correction is made to comply with 37 CFR 1.57(c), (d), or (e). If the incorporated material is relied upon to meet any outstanding objection, rejection, or other requirement imposed by the Office, the correction must be made within any time period set by the Office for responding to the objection, rejection, or other requirement for the incorporation to be effective. Compliance will not be held in abeyance with respect to responding to the objection, rejection, or other requirement for the incorporation to be effective. In no case may the correction be made later than the close of prosecution as defined in 37 CFR 1.114(b), or abandonment of the application, whichever occurs earlier.
Any correction inserting material by amendment that was previously incorporated by reference must be accompanied by a statement that the material being inserted is the material incorporated by reference and the amendment contains no new matter. 37 CFR 1.57(g).
Claim Rejections - 35 USC § 112
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claims 15-24 are rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention.
Regarding claim 15, there is insufficient antecedent basis for “the instruction”. There are multiple instructions previously claimed.
Regarding claim 16, there is insufficient antecedent basis for “the memory bank”. There are multiple memory banks previously claimed.
Regarding claim 16, the scope of meaning of “configured to store a second weight required for a next operation cycle of the corresponding operation cycle” is unclear. It is unclear what is meant by “a next operation cycle of the corresponding operation cycle” regarding a cycle being of another cycle.
Claims 17-24 are rejected as being dependent from a rejected parent claim.
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claims 14-16, 24-25 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Bae, US Patent Application Publication 2022/0374691 (hereinafter Bae).
Regarding claim 14, Bae teaches:
An electronic device comprising: a system on chip (SoC) (see e.g. fig. 2, para. [0078]); and a NAND flash connected to the SoC and configured to store a weight of an artificial neural network model and instructions (see e.g. fig. 2, para. [0084], [0106], [0136-9], [0267-9], data including weights and instructions are exchanged between the different memory levels), wherein the SoC comprises: a memory configured to store input data of the artificial neural network model (see e.g. fig. 7, para. [0136], [0140], L0 memory and weight buffers); an interface configured to perform communication between the NAND flash and the SoC (see e.g. fig. 2, 3, para. [0078], [0089], non-volatile memory interface/controller); and an accelerator configured to perform an artificial neural network operation between the input data obtained from the memory and the weight obtained through the interface (see e.g. fig. 3, neural processor).
Regarding claim 15, Bae teaches:
The electronic device of claim 14, wherein the memory further comprises: buffers configured to store the input data (see e.g. fig. 7, para. [0140], [0260-1]); and memory banks configured to load and store a portion of the weight from the interface according to the instruction (see e.g. fig. 19, para. [0260-1]).
Regarding claim 16, Bae teaches:
The electronic device of claim 15, wherein the memory bank comprises: a first memory bank configured to store a first weight required for a corresponding operation cycle; and a second memory bank configured to store a second weight required for a next operation cycle of the corresponding operation cycle (see e.g. fig. 19, para. [0260]).
Regarding claim 24, Bae teaches:
The electronic device of claim 15, wherein a number of buffers is determined based on an algorithm corresponding to the artificial neural network operation (see e.g. Bae para. [0315]).
Regarding claim 25, Bae teaches:
The electronic device of claim 14, wherein the memory comprises a static random access memory (SRAM) (see e.g. Bae para. [0085]).
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 17-18 are rejected under 35 U.S.C. 103 as being unpatentable over Bae in view of Yang et al., US Patent Application Publication 2024/0160692 (hereinafter Yang).
Regarding claim 17, Bae teaches:
The electronic device of claim 16.
Bae fails to explicitly teach wherein the accelerator comprises a data selection unit configured to select first data and second data among outputs of the buffers and an output of the first memory bank.
Yang teaches selecting from among buffers or banks of input data for convolution operations (see e.g. fig. 2, para. [0193]).
Before the effective filing date of the claimed invention it would have been obvious to one of ordinary skill in the art to combine the teachings of Bae and Yang such that the accelerator comprises a data selection unit configured to select first data and second data among outputs of the buffers and an output of the first memory bank. This would have provided an advantage of using well-known and easy to implement multiplexers to select from stored data. This would also have provided performance improvements such as discussed by Yang of “one or more of increased computational performance, reduced latency, increased throughput, and/or reduced power consumption” (see para. [0280]).
Regarding claim 18, Bae in view of Yang teaches or suggests:
The electronic device of claim 17, wherein the data selection unit comprises: a first multiplexer configured to select the first data among the outputs of the buffers and the output of the first memory bank; and a second multiplexer configured to select the second data among the outputs of the buffers and the output of the first memory bank (see e.g. Yang fig. 2, para. [0193]).
Claims 19-23 are rejected under 35 U.S.C. 103 as being unpatentable over Bae in view of Yang, further in view of Smelyanskiy, US Patent Application Publication 2016/0179540 (hereinafter Smelyanskiy).
Regarding claim 19, Bae in view of Yang teaches or suggests:
The electronic device of claim 18.
Bae in view of Yang fails to explicitly teach wherein the instructions comprise a data alignment instruction, and the accelerator comprises a data alignment unit configured to align the first data and the second data according to the data alignment instruction.
Smelyanskiy teaches a data alignment unit that aligns data for convolution processing as specified by an instruction (see e.g. para. [0156], [0172]).
Before the effective filing date of the claimed invention it would have been obvious to one of ordinary skill in the art to combine the teachings of Bae, Yang, and Smelyanskiy such that the instructions comprise a data alignment instruction, and the accelerator comprises a data alignment unit configured to align the first data and the second data according to the data alignment instruction. This would have provided an advantage of ensuring that data were in the correct positions to improve the accuracy of processing.
Regarding claim 20, Bae in view of Yang and Smelyanskiy teaches or suggests:
The electronic device of claim 19, wherein the first data comprises consecutive data selected by the first multiplexer, the second data comprises consecutive data selected by the second multiplexer, and the data alignment unit comprises: a first shifter configured to align the consecutive data selected by the first multiplexer; and a second shifter configured to align the consecutive data selected by the second multiplexer (see e.g. Yang para. [0131], [0206], [0261], loaded data can be permuted to order the data).
Regarding claim 21, Bae in view of Yang and Smelyanskiy teaches or suggests:
The electronic device of claim 20, wherein the accelerator comprises an operation unit configured to perform the artificial neural network operation between the first data and the second data (see e.g. Bae fig. 6, para. [0112], [0146]).
Regarding claim 22, Bae in view of Yang and Smelyanskiy teaches or suggests:
The electronic device of claim 21, wherein the instructions comprise a convolution operation instruction, and the operation unit is configured to perform a convolution operation between an output of the first shifter and an output of the second shifter according to the convolution operation instruction (see e.g. Bae para. [0146]).
Regarding claim 23, Bae in view of Yang and Smelyanskiy teaches or suggests:
The electronic device of claim 22, wherein the operation unit comprises a multiply-accumulate (MAC) circuit configured to perform a MAC operation between the output of the first shifter and the output of the second shifter in one cycle according to the convolution operation instruction (see e.g. Bae para. [0161-2]).
Claim 26 is rejected under 35 U.S.C. 103 as being unpatentable over Bae in view of Wen et al., US Patent Application Publication 2020/0364544 (hereinafter Wen).
Regarding claim 26, Bae teaches:
The electronic device of claim 14.
Bae fails to explicitly teach wherein the interface comprises a quad serial peripheral interface (QSPI).
Wen teaches using a QSPI interface for an AI accelerator chip (see e.g. para. [0048], [0052]).
Before the effective filing date of the claimed invention it would have been obvious to one of ordinary skill in the art to combine the teachings of Bae and Wen such that the interface comprises a quad serial peripheral interface (QSPI). This would have been desirable to provide better performance for high-bandwidth applications.
Claim 27 is rejected under 35 U.S.C. 103 as being unpatentable over Bae in view of Smelyanskiy.
Regarding claim 27, Bae teaches:
A system on chip (SoC) comprising: a memory configured to store input data of an artificial neural network model (see e.g. fig. 7, para. [0136], [0140], L0 memory and weight buffers); an interface configured to perform communication with an external memory storing a weight of the artificial neural network model (see e.g. fig. 7, para. [0136], [0140], weight values read from external memory); and an accelerator configured to perform an artificial neural network operation between the input data obtained from the memory and the weight obtained through the interface according to instructions (see e.g. fig. 3, neural processor), wherein the instructions comprise an operation instruction, and the accelerator comprises an operation unit configured to perform an operation between the input data and the weight (see e.g. Bae fig. 6, para. [0112], [0146], [0161-2]).
Bae fails to explicitly teach wherein the instructions comprise a data alignment instruction, and the accelerator comprises a data alignment unit configured to align the input data and the weight according to the data alignment instruction.
Smelyanskiy teaches a data alignment unit that aligns data for convolution processing as specified by an instruction (see e.g. para. [0156], [0172]).
Before the effective filing date of the claimed invention it would have been obvious to one of ordinary skill in the art to combine the teachings of Bae, Yang, and Smelyanskiy such that the instructions comprise a data alignment instruction, and the accelerator comprises a data alignment unit configured to align the input data and the weight according to the data alignment instruction. This would have provided an advantage of ensuring that data were in the correct positions to improve the accuracy of processing.
Conclusion
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/JOHN M LINDLOF/Primary Examiner, Art Unit 2183
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