Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Allowable Subject Matter
Claims 15-18, and 20 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
Claim Objections
Claim 10 is objected to because of the following informalities: “That shift register according to claim 1” shall be “The shift register according to claim 1”. Appropriate correction is required.
Claim Rejections - 35 USC § 112
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claims 25 and 26 are rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention.
Claims 25 and 26 re-introduce claim terms “an input sub-circuit”, “a second control sub-circuit”, and “an output sub-circuit”, however, corresponding terms already contain antecedent basis as claimed in claims 1 and 19, in which claims 25 and 26 respectively depends on. Accordingly, corresponding terms shall be “the input sub-circuit”, “the second control sub-circuit” and “the output sub-circuit”).
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claims 1-4, 7, 10, 11, 13, 14, 21, 22, 24 and 25 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Feng et al., US 20220013060 A1 (hereinafter “Feng”).
Regarding claim 1, Feng discloses a shift register (see abstract, a shift register and driving method thereof), comprising an input sub-circuit, an output sub-circuit, and a first control sub-circuit (see annotated fig. 11);
wherein the input sub-circuit is electrically connected with a signal input terminal (fig. 11, signal input terminal PS) and a pull-up node (fig. 11, node PU), respectively, and is configured to provide a signal to the pull-up node under control of a signal of the signal input terminal (fig. 11, paragraphs 128, 139-141, 147, transistor M4 is configure to provide a signal CLKA to pull-up node PU under control of signal PS);
the output sub-circuit is electrically connected with a first output terminal (fig. 11, first output terminal OUT1), the pull-up node (fig. 11, node PU), and a clock signal terminal (fig. 11, clock signal CLKC), respectively, and is configured to provide a signal of the clock signal terminal to the first output terminal under control of a signal of the pull-up node (fig. 11, paragraphs 128, 139-141, 147-149, transistor M8 configured to provide a signal of the clock signal CLKC and/or CLKB to first output terminal OUT1 and/or OUT2 under control of signal at pull-up node PU); and
the first control sub-circuit is electrically connected with a control signal terminal (fig. 11, control signal terminal INPUT) and the signal input terminal (fig. 11, signal input terminal PS), respectively, and is configured to provide a signal of the control signal terminal to the signal input terminal under control of the signal of the control signal terminal (fig. 11, paragraphs 128, 139-141, transistor M1 configured to provide signal of the control signal terminal INPUT to the signal input terminal PS under control of the signal INPUT).
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Regarding claim 2, Feng discloses the shift register according to claim 1, further comprising a first reset sub-circuit (see annotated fig. 11 below); wherein
the first reset sub-circuit (fig. 11, M14) is electrically connected with a total reset signal terminal (fig. 11, reset signal terminal RST1), the pull-up node (fig. 11, node PU), and a first power supply terminal (fig. 11, power supply terminal VGL1), respectively, and is configured to provide a signal of the first power supply terminal to the pull-up node under control of the total reset signal terminal (fig. 11, paragraphs, 127, 128, 139-142, transistor M14 configured to provide signal of first power supply terminal VGL1 to pull-up node PU under control of total reset signal terminal RST1); and
the total reset signal terminal has an active level signal in part of time periods of a non-display phase and an inactive level signal in a display phase.
(fig. 12A, paragraphs 139-142, paragraph 140: “In a second stage D2, i.e., an output stage … The input signal of the first reset terminal RST1 is at a low level, and the third transistor M3 and the fourteenth transistor M14 are turned off, so the pull-up node PU maintains at a high level”, paragraph 142: “In a fourth stage D4, i.e., a reset stage … the input signal of the first reset terminal RST1 is at a high level, the third transistor M3 and the fourteenth transistor M14 are turned on to pull down the potentials of the pull-up node PU and the sensing node PS”, herein the output stage D2 constitute the claimed display phase wherein gate signal for display are output and reset stage D4 constitute the claimed non-display phase wherein shift register is reset).
Regarding claim 3, Feng discloses the shift register according to claim 1, wherein the control signal terminal comprises at least one of a first control signal terminal and a second control signal terminal; and the first control signal terminal is electrically connected with a total reset signal terminal, and the second control signal terminal is electrically connected with the first output terminal (see fig. 11 as annotated, the control signal terminal INPUT may be interpreted as both first control signal terminal or second control signal terminal, as it is electrically connected with total reset signal terminal via M6 and M16, and electrically connected with first output terminal via M6 and M8).
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Regarding claim 4, Feng discloses the shift register according to claim 3,
wherein in a state in which the control signal terminal comprises the first control signal terminal, the first control sub-circuit comprises a nineteenth transistor; and
a control electrode and a first electrode of the nineteenth transistor are respectively electrically connected with the first control signal terminal, and a second electrode of the nineteenth transistor is electrically connected with the signal input terminal;
or,
wherein in a state in which the control signal terminal comprises the second control signal terminal, the first control sub-circuit comprises a twentieth transistor; and
a control electrode and a first electrode of the twentieth transistor are respectively electrically connected with the second control signal terminal, and a second electrode of the twentieth transistor is electrically connected with the signal input terminal;
or,
wherein in a state in which the control signal terminal comprises the first control signal terminal and the second control signal terminal, the control sub-circuit comprises a nineteenth transistor and a twentieth transistor;
a control electrode and a first electrode of the nineteenth transistor are respectively electrically connected with the first control signal terminal, and a second electrode of the nineteenth transistor is electrically connected with the signal input terminal; and
a control electrode and a first electrode of the twentieth transistor are respectively electrically connected with the second control signal terminal, and a second electrode of the twentieth transistor is electrically connected with the signal input terminal.
(see annotated fig. 11, the transistor M1 may be interpreted as nineteenth or twentieth transistor, with control signal terminal INPUT as claimed first or second control signal, respectively, wherein the control electrode and first electrode of transistor M1 is connected with signal INPUT, and second electrode of the transistor M1 is connected with signal input terminal PS)
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Regarding claim 7, Feng discloses the shift register according to claim 1, wherein the input sub-circuit comprises a first transistor (fig. 11, transistor M4); and
a control electrode of the first transistor is electrically connected with the signal input terminal (fig. 11, control electrode of M4 connected with signal input terminal PS), a first electrode of the first transistor is electrically connected with the signal input terminal or a second power supply terminal (fig. 11, a first electrode of M4 connected with terminal CLKA), and a second electrode of the first transistor is electrically connected with the pull-up node (fig. 11, a second electrode of M4 connected with pull-up node PU);
or,
wherein the input sub-circuit comprises a first transistor and a twenty-first transistor;
a control electrode of the first transistor is electrically connected with the signal input terminal, a first electrode of the first transistor is electrically connected with the signal input terminal or a second power supply terminal, and a second electrode of the first transistor is electrically connected with a control node; and
a control electrode and a first electrode of the twenty-first transistor are respectively electrically connected with the control node, and a second electrode of the twenty-first transistor is electrically connected with the pull-up node;
or,
wherein the output sub-circuit comprises a second transistor (fig. 11, transistor M8) and a capacitor (fig. 11, capacitor C2);
a control electrode of the second transistor is electrically connected with the pull-up node (fig. 11, control electrode of M8 connected with pull-up node PU), a first electrode of the second transistor is electrically connected with the clock signal terminal (fig. 11, first electrode of transistor M8 connected with clock signal CLKC), and a second electrode of the second transistor is electrically connected with the first output terminal (fig. 11, second electrode of transistor M8 connected with first output terminal OUT1); and
a first terminal of the capacitor is electrically connected with the pull-up node, and a second terminal of the capacitor is electrically connected with the first output terminal (fig. 11, first terminal and second terminal of capacitor C2 connected with pull-up node PU and first output terminal OUT1 respectively).
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Regarding claim 10, Feng discloses the shift register according to claim 1, wherein the output sub-circuit is further electrically connected with a second output terminal (fig. 11, second output terminal OUT2) and is configured to provide a signal of the clock signal terminal to the second output terminal under control of the signal of the pull-up node (see annotated fig. 11 below, transistor M7 configured to provide clock signal CLKB to second output terminal OUT2 under control of signal from pull-up node PU).
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Regarding claim 11, Feng discloses the shift register according to claim 10, wherein the output sub-circuit comprises a second transistor (fig. 11, transistor M8) a third transistor (fig. 11, transistor M7), and a capacitor (fig. 11, capacitor C2);
a control electrode of the second transistor (fig. 11, transistor M8) is electrically connected with the pull-up node (fig. 11, pull-up node PU), a first electrode of the second transistor is electrically connected with the clock signal terminal (fig. 11, CLKC), and a second electrode of the second transistor is electrically connected with the first output terminal (fig. 11, OUT1);
a control electrode of the third transistor (fig. 11, transistor M7) is electrically connected with the pull-up node (fig. 11, pull-up node PU), a first electrode of the third transistor is electrically connected with the clock signal terminal (fig. 11, CLKB), and a second electrode of the third transistor is electrically connected with the second output terminal (fig. 11, OUT2); and
a first terminal of the capacitor (fig. 11, capacitor C2) is electrically connected with the pull-up node (fig. 11, pull-up node PU), and a second terminal of the capacitor is electrically connected with the first output terminal (fig. 11, terminal OUT1).
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Regarding claim 13, Feng discloses the shift register according to claim 1, further comprising a second reset sub-circuit (see annotated fig. 11 below); wherein
the second reset sub-circuit is electrically connected with a first reset signal terminal (fig. 11, terminal RST1), a second reset signal terminal (fig. 11, terminal PD), the pull-up node (fig. 11, node PU), the first output terminal (fig. 11, terminal OUT1), a first power supply terminal (fig. 11, power supply VGL1), and a third power supply terminal (fig. 11, power supply VGL2), respectively, and is configured to provide a signal of the first power supply terminal to the pull-up node and provide a signal of the third power supply terminal to the first output terminal under control of signals of the first reset signal terminal and the second reset signal terminal (fig. 11, M14 configured to provide VGL1 to node PU under control of signal RST1 and M13 configured to provide VLG2 to terminal OUT1 under control of signal PD);
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an absolute value of a voltage of the signal of the first power supply terminal is greater than an absolute value of a voltage of the signal of the third power supply terminal (paragraph 95, “the second power supply terminal VGL1 and the third power supply terminal VGL2 continuously provide low-level signals. The signal potentials of the second power supply terminal VGL1 and the third power supply terminal VGL2 may be the same or may be different. When the potentials of the second power supply terminal VGL1 and the third power supply terminal VGL2 are different, a signal potential of the third power supply terminal VGL2 is higher than that of the second power supply terminal VGL1”, that is, when both VGL1 and VGL2 are negative voltage, the absolute value of VGL1 is greater than absolute value of VGL2) ; and
the first reset signal terminal and the second reset signal terminal have inactive level signals in a non-display phase and an output phase, and have active level signals in part of time periods of a non-output phase.
(see timing diagram fig. 12A-12C, paragraphs 139-144, note that active level at node PD is inverse of lever of PU, as PD will be pulled down to inactive level by M10 whenever PU is in active level, in periods D1~D3, PU and RST1 have inactive level, and in period D4 PU and RST1 have active level, paragraph 142: “In a fourth stage D4, i.e., a reset stage … the input signal of the first reset terminal RST1 is at a high level, the third transistor M3 and the fourteenth transistor M14 are turned on to pull down the potentials of the pull-up node PU and the sensing node PS”).
Regarding claim 14, Feng discloses the shift register according to claim 13, wherein (see annotated fig. 11 below)
the second reset sub-circuit comprises a fifth transistor (fig. 11, transistor M14) and a sixth transistor (fig. 11, transistor M13);
a control electrode of the fifth transistor (fig. 11, M14) is electrically connected with the first reset signal terminal (fig. 11, terminal RST1), a first electrode of the fifth transistor is electrically connected with the pull-up node (fig. 11, node PU), and a second electrode of the fifth transistor is electrically connected with the first power supply terminal (fig. 11, supply VGL1); and
a control electrode of the sixth transistor (fig. 11, M13) is electrically connected with the second reset signal terminal (fig. 11, terminal PD), a first electrode of the sixth transistor is electrically connected with the first output terminal (fig. 11, terminal OUT1), and a second electrode of the sixth transistor is electrically connected with the third power supply terminal (fig. 11, supply VGL2).
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Regarding claim 21, Feng discloses a gate drive circuit, comprising a plurality of cascaded shift registers according to claim 1 (fig. 13, cascading of shifting registers to form gate driver, paragraphs 153-158, “An embodiment of the present disclosure also provides a gate driving circuit. FIG. 13 is a schematic structural diagram of a gate driving circuit according to an embodiment of the present disclosure. As shown in FIG. 13, the gate driving circuit provided by the embodiment of the present disclosure includes a plurality of shift registers”).
Regarding claim 22, Feng discloses the gate drive circuit according to claim 21, wherein the gate drive circuit is disposed in a display apparatus, the display apparatus is provided with a gate line, and a shift register comprises an output sub-circuit; and
in a state in which the output sub-circuit comprises a first output terminal, a first output terminal of any stage of shift register is electrically connected with the gate line, a first output terminal of a current-stage shift register is electrically connected with a signal input terminal of a next-stage shift register, and the first output terminal of the current-stage shift register is electrically connected with a first reset signal terminal or a second reset signal terminal of a previous-stage shift register;
or,
wherein the gate drive circuit is disposed in a display apparatus, the display apparatus is provided with a gate line, and a shift register comprises an output sub-circuit; and
in a state in which the output sub-circuit comprises a first output terminal and a second output terminal, a first output terminal of any stage of shift register is electrically connected with the gate line, a second output terminal of a current-stage shift register is electrically connected with a signal input terminal of a next-stage shift register, and the second output terminal of the current-stage shift register is electrically connected with a first reset signal terminal or a second reset signal terminal of a previous-stage shift register (see fig. 13, paragraphs 153-158, “An embodiment of the present disclosure also provides a gate driving circuit. FIG. 13 is a schematic structural diagram of a gate driving circuit according to an embodiment of the present disclosure. As shown in FIG. 13, the gate driving circuit provided by the embodiment of the present disclosure includes a plurality of shift registers.” See fig. 13 annotated as in below).
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Regarding claim 24, Feng discloses a display apparatus, comprising a gate drive circuit according to claim 21 (Feng, paragraph 3, 65, “A display panel includes a gate driving circuit and a pixel circuit arranged in an array. The gate driving circuit includes a plurality of shift registers. Different shift registers are connected with different rows of pixel circuits and are configured to provide scanning signals to the connected pixel circuits in a display stage”).
Regarding claim 25, Feng discloses a drive method of a shift register, configured to drive a shift register according to claim 21, wherein the method comprises (fig. 11, paragraphs128, 139-142):
providing, by an input sub-circuit (fig. 11, transistor M4), a signal (fig. 11, signal CLKA) to a pull-up node (fig. 11, node PU) under control of a signal of a signal input terminal (fig. 11, signal PS control transistor M4 to provide CLKA to node PU);
providing, by an output sub-circuit (fig. 11, transistor M8), a signal of a clock signal terminal (fig. 11, signal CLKC) to a first output terminal under (fig. 11, terminal OUT1) control of a signal of the pull-up node (fig. 11, signal at node PU control transistor M8 to provide CLKC to terminal OUT1) ; and
providing, by a control sub-circuit (fig. 11, transistor M1), a signal of a control signal terminal (fig. 11, terminal INPUT) to the signal input terminal (fig. 11, terminal PS) under control of the signal of the control signal terminal (fig. 11, signal INPUT control transistor M1 to provide signal INPUT to terminal PS).
Claims 19 and 26 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Kwon et al., US 20100007635 A1 (hereinafter “Kwon”).
Regarding claim 19. Kwon discloses a shift register (paragraph 7: “The gate driving circuit includes a shift register in which a plurality of driving stages are connected to each other one after another and sequentially outputs the gate signal”), comprising an input sub-circuit (fig. 2, circuit 215), an output sub-circuit (fig. 2, circuit 211), and a second control sub-circuit (fig. 2, circuit 214, see annotated fig 2 below); wherein
the input sub-circuit (fig. 2, circuit 215) is electrically connected with a signal input terminal (fig. 2, signal CK2) and a control node (fig. 2, node connected with terminal IN), respectively, and is configured to provide a signal to the control node under control of the signal input terminal (fig. 2, paragraphs 50-53, CK2 configured to connect signal at node QN with node at terminal IN in response to clock signal);
the second control sub-circuit (fig. 2, circuit 214) is electrically connected with the control node (fig. 2, node connected with terminal IN) and a pull-up node (fig. 2, node QN), respectively, and is configured to provide a signal of the control node to the pull-up node under control of the signal of the control node (fig. 2, paragraphs 47, 48, signal of the control node IN provided to pull-up node QN under control of the signal IN via transistor NT4); and
the output sub-circuit (fig. 2, circuit 211) is electrically connected with a first output terminal (fig. 2, terminal OUT), the pull-up node (fig. 2, node QN), and a clock signal terminal (fig. 2, clock signal CK1), respectively, and is configured to provide a signal of the clock signal terminal to the first output terminal under control of a signal of the pull-up node (fig. 2, paragraphs 44, 45, clock signal CK1 provided to output terminal OUT under control of signal at pull-up node QN via transistor NT1).
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Regarding claim 26, Kwon discloses a drive method of a shift register, configured to drive a shift register according to claim 19, wherein the method comprises:
providing, by an input sub-circuit (fig. 2, circuit 215), a signal to a control node under control of a signal input terminal (fig. 2, paragraphs 50-53, signal input terminal CK2 configured to connect signal at node QN with control node at terminal IN in response to clock signal);
providing, by a second control sub-circuit (fig. 2, circuit 214), a signal of the control node (fig. 2, signal at terminal IN) to a pull-up node (fig. 2, node QN) under control of the signal of the control node (fig. 2, paragraphs 47, 48, signal of the control node IN provided to pull-up node QN under control of the signal IN via transistor NT4); and
providing, by an output sub-circuit (fig. 2, circuit 211), a signal of a clock signal terminal (fig. 2, clock signal terminal CK1) to a first output terminal (fig. 2, output terminal OUT) under control of a signal of the pull-up node (fig. 2, paragraphs 44, 45, clock signal CK1 provided to output terminal OUT under control of signal at pull-up node QN via transistor NT1).
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to PEIJIE SHEN whose telephone number is (571)272-5522. The examiner can normally be reached Monday - Friday 10AM - 6PM.
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/PEIJIE SHEN/Examiner, Art Unit 2622
/PATRICK N EDOUARD/Supervisory Patent Examiner, Art Unit 2622
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