DETAILED ACTION
Claims 18 has been cancelled. Claims 1-17 and 19-21 have been examined and are pending.
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Rejections - 35 USC § 101
35 U.S.C. 101 reads as follows:
Whoever invents or discovers any new and useful process, machine, manufacture, or composition of matter, or any new and useful improvement thereof, may obtain a patent therefor, subject to the conditions and requirements of this title.
Claim 20 is rejected under 35 U.S.C. 101 because the claimed invention is directed to non-statutory subject matter. The claim(s) does/do not fall within at least one of the four categories of patent eligible subject matter because in its broadest reasonable interpretation it includes transitory signals. To avoid this interpretation is “non-transitory” may be used.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
This application currently names joint inventors. In considering patentability of the claims the examiner presumes that the subject matter of the various claims was commonly owned as of the effective filing date of the claimed invention(s) absent any evidence to the contrary. Applicant is advised of the obligation under 37 CFR 1.56 to point out the inventor and effective filing dates of each claim that was not commonly owned as of the effective filing date of the later invention in order for the examiner to consider the applicability of 35 U.S.C. 102(b)(2)(C) for any potential 35 U.S.C. 102(a)(2) prior art against the later invention.
Claims 1-7, 13-17, and 19-21 are rejected under 35 U.S.C. 103 as being unpatentable over US Pub. No. 2020/0106615 to Rule et al. (hereinafter “Rule”) and further in view of US Pub. No. 2025/0004649 to O’Doherty (hereinafter “O’Doherty”).
As to Claim 1, Rules discloses a communication method, comprising:
computing a key corresponding to current time according to initial keys, wherein the initial keys comprise at last one first initial key and a second initial key, the at least one first initial key is generated by a server, and the second initial key is generated by an encryption dedicated [field programmable gate array (FPGA) accelerator] (Paragraph [0120] of Rule discloses the session keys are independently derived at the one or more servers, resulting in a first session key (the ENC session key) and a second session key (the MAC session key). Paragraph [0073] of Rule discloses one or more HSMs 330 may be configured to perform at least one of key derivations, decryption, and MAC operations. The one or more HSMs 330 may be contained within, or may be in data communication with, servers 320 and 325);
generating a data message according to the key and to-be-transmitted data (Paragraph [0010] of Rule discloses generate an encrypted payload);
transmitting the data message to a message receiving end (Paragraph [0181] of Rule discloses a server may receive the payload and the server may be configured to utilize symmetric key decryption to decrypt the payload);
generating a verification data message according to verification keys, wherein the verification keys comprise at last one first verification key and a second verification key, the at last one first verification key is obtained by searching the server, and the second verification key is obtained by searching the encryption dedicated [FPGA accelerator] (Paragraph [0044] of Rule discloses sends the MAC cryptogram to the application. Paragraph [0120] of Rule discloses the session keys are independently derived at the one or more servers, resulting in a first session key (the ENC session key) and a second session key (the MAC session key). Paragraph [0073] of Rule discloses one or more HSMs 330 may be configured to perform at least one of key derivations, decryption, and MAC operations. The one or more HSMs 330 may be contained within, or may be in data communication with, servers 320 and 325); and
transmitting the verification data message to the message receiving end, and causing validity of the data message to be verified by the message receiving end according to the initial keys and the verification data message (Paragraph [0044] of Rule discloses sends the MAC cryptogram to the application. Paragraph [0046] of Rule discloses verifies the MAC cryptogram).
Rule does not explicitly disclose FPGA accelerator.
However, O’Doherty discloses this. Paragraph [0084] of O’Doherty discloses the HSM device may be implemented using an ASIC or a Field Programmable Gate Array (FPGA).
It would have been obvious to one of ordinary skill in the art before the effective filing of the invention to combine the cryptographic system as disclosed by Rule, with implementing an HSM using an FPGA as disclosed by O’Doherty. One of ordinary skill in the art would have been motivated to combine to apply a known technique to a known device ready for improvement to yield predictable results. Rule and O’Doherty are directed toward cryptographic systems and as such it would be obvious to use the techniques of one in the other. Paragraph [0084] of O’Doherty discloses the HSM device may be implemented using an ASIC or a Field Programmable Gate Array (FPGA). Paragraph [0073] of Rule discloses one or more HSMs 330 may be configured to perform at least one of key derivations, decryption, and MAC operations. Accordingly, it is known in the art for the HSMs disclosed in Rule to be implemented using FPGAs.
As to Claim 2, Rule-O’Doherty discloses the communication method according to claim 1, wherein the at least one first initial key comprise:
a first-level initial key and a second-level initial key (Paragraph [0120] of Rule discloses the session keys are independently derived at the one or more servers, resulting in a first session key (the ENC session key) and a second session key (the MAC session key));
the first-level initial key is generated by the server for the encryption dedicated FPGA accelerator and forwarded by the encryption dedicated FPGA accelerator to a computation dedicated FPGA accelerator in an interconnected FPGA accelerator cluster corresponding to the encryption dedicated FPGA accelerator (Paragraph [0120] of Rule discloses the session keys are independently derived at the one or more servers. Paragraph [0073] of Rule discloses one or more HSMs 330 may be configured to perform at least one of key derivations, decryption, and MAC operations. Paragraph [0084] of O’Doherty discloses the HSM device may be implemented using an ASIC or a Field Programmable Gate Array (FPGA)); and
the second-level initial key is generated by the server for the computation dedicated FPGA accelerator and broadcasted to the computation dedicated FPGA accelerator (Paragraph [0120] of Rule discloses the session keys are independently derived at the one or more servers. Paragraph [0073] of Rule discloses one or more HSMs 330 may be configured to perform at least one of key derivations, decryption, and MAC operations. Paragraph [0084] of O’Doherty discloses the HSM device may be implemented using an ASIC or a Field Programmable Gate Array (FPGA)).
Examiner recites the same rationale to combine used for claim 1.
As to Claim 3, Rule-O’Doherty discloses the communication method according to claim 2, wherein a method through which the first-level initial key generated by the server for the encryption dedicated FPGA accelerator is forwarded by the encryption dedicated FPGA accelerator comprises:
transmitting, by the encryption dedicated FPGA accelerator through an inter-core data transmission channel, the first-level initial key generated by the server for the encryption dedicated FPGA accelerator to the computation dedicated FPGA accelerator interconnected to the encryption dedicated FPGA accelerator, and forwarding, by the computation dedicated FPGA accelerator interconnected to the encryption dedicated FPGA accelerator, the first-level initial key which is received to other computation dedicated FPGA accelerators in a same router (Paragraph [0073] of Rule discloses one or more HSMs 330 may be configured to perform at least one of key derivations, decryption, and MAC operations. The one or more HSMs 330 may be contained within, or may be in data communication with, servers 320 and 325. Paragraph [0084] of O’Doherty discloses the HSM device may be implemented using an ASIC or a Field Programmable Gate Array (FPGA)).
Examiner recites the same rationale to combine used for claim 1.
As to Claim 4, Rule-O’Doherty discloses the communication method according to claim 2, wherein keys generated by the server for different encryption dedicated FPGA accelerators are different (Paragraph [0065] of Rule discloses a different counter value may be selected producing a different diversified symmetric key).
As to Claim 5, Rule-O’Doherty discloses the communication method according to claim 2, wherein the at last one first verification key comprise: a first-level verification key and a second-level verification key; a first-level verification key is computed by the server according to the first-level initial key; and a second-level verification key is computed by the server according to the second-level initial key (Paragraph [0120] of Rule discloses the session keys are independently derived at the one or more servers. The second derived key (i.e., the ENC session key) may be used to decrypt the data, and the first derived key (i.e., the MAC session key) may be used to verify the decrypted data. Paragraph [0073] of Rule discloses one or more HSMs 330 may be configured to perform at least one of key derivations, decryption, and MAC operations).
As to Claim 6, Rule-O’Doherty discloses the communication method according to claim 1, wherein the data message and the verification data message are transmitted to the message receiving end in parallel (Paragraph [0147] of Rule discloses The protected data, including plaintext and shared secret, may be used to produce a MAC. Paragraph [0148] of Rule discloses the data to be protected may be encrypted by the sender using the data encryption derived session key. Paragraph [0149] of Rule discloses the encrypted MAC is transmitted, from the sender to the recipient, with sufficient information to identify additional secret information (such as shared secret, master keys, etc.), for verification of the cryptogram).
As to Claim 7, Rule-O’Doherty discloses the communication method according to claim 1, wherein the validity of the data message is caused to be verified according to the initial keys and the verification data message as follows: parsing the verification data message, and obtaining the verification keys; computing to-be-verified keys according to the initial keys; comparing the verification keys with the to-be-verified keys; not receiving the data message in a case that the verification keys are different from the to-be-verified keys; verifying the validity of the data message according to the verification keys in a case that the verification keys are the same as the to-be-verified keys; receiving the data message in a case that the validity passes verification; and not receiving the data message in a case that the validity does not pass the verification (Paragraph [0153] of Rule discloses the ability to verify the MAC shows that the derived session key was proper. The successful decryption may show that the correctly derived encryption key was used to decrypt the encrypted MAC. Since the derived session keys are created using the master keys known only to the sender (e.g., the transmitting device) and recipient (e.g., the receiving device), it may be trusted that the contactless card which originally created the MAC and encrypted the MAC is indeed authentic).
As to Claim 13, Rule-O’Doherty discloses the communication method according to claim 1, applied to an FPGA accelerator cluster network based on a tree topology, wherein the FPGA accelerator cluster network based on a tree topology mainly comprises the server, the encryption dedicated FPGA accelerator, a computation dedicated FPGA accelerator, and a router (Paragraph [0073] of Rule discloses the one or more HSMs 330 may be contained within, or may be in data communication with, servers 320 and 325. Paragraph [0084] of O’Doherty discloses the HSM device may be implemented using an ASIC or a Field Programmable Gate Array (FPGA).
Examiner recites the same rationale to combine used for claim 1.
As to Claim 14, Rule-O’Doherty discloses the communication method according to claim 1, wherein a key chain is generated by the encryption dedicated FPGA accelerator by using a pseudorandom function, and the key chain is used for being updated to the server and a computation dedicated FPGA accelerator in an interconnected FPGA accelerator cluster corresponding to the encryption dedicated FPGA accelerator (Paragraph [0053] of Rule discloses independently generate keys from an initial shared master symmetric key in combination with a counter value, and thereby periodically replace the shared symmetric key being used).
As to Claim 15, Rule-O’Doherty discloses the communication method according to claim 14, wherein a function of the computation dedicated FPGA accelerator comprises: generating and transmitting a message to a message receiver (Paragraph [0054] of Rule discloses a sender and recipient may desire to exchange data (e.g., original sensitive data)).
As to Claim 16, Rule-O’Doherty discloses the communication method according to claim 15, wherein in an FPGA accelerator cluster network, a message transmitter is a server, and the message receiver is a computation dedicated FPGA accelerator; or in an FPGA accelerator cluster network, a message transmitter is a computation dedicated FPGA accelerator, and the message receiver is a computation dedicated FPGA accelerator or a server (Paragraph [0073] of Rule discloses one or more HSMs 330 may be configured to perform at least one of key derivations, decryption, and MAC operations. The one or more HSMs 330 may be contained within, or may be in data communication with, servers 320 and 325. Paragraph [0084] of O’Doherty discloses the HSM device may be implemented using an ASIC or a Field Programmable Gate Array (FPGA)).
Examiner recites the same rationale to combine used for claim 1.
As to Claim 17, Rule-O’Doherty discloses the communication method according to claim 16, wherein in a case that the message transmitter is the server, the first verification key is a key computed by the server according to the at least one first initial key, and the second verification key is a key acquired by the server from the encryption dedicated FPGA accelerator and is a key corresponding to the current time computed by the encryption dedicated FPGA accelerator according to the second initial key; and in a case that the message transmitter is the computation dedicated FPGA accelerator, the first verification key is a key acquired by the computation dedicated FPGA accelerator from the server and is a key corresponding to the current time computed by the server according to the at least one first initial key, and the second verification key is a key acquired by the computation dedicated FPGA accelerator from the encryption dedicated FPGA accelerator and is a key corresponding to the current time computed by the encryption dedicated FPGA accelerator according to the second initial key (Paragraph [0044] of Rule discloses sends the MAC cryptogram to the application. Paragraph [0120] of Rule discloses the session keys are independently derived at the one or more servers, resulting in a first session key (the ENC session key) and a second session key (the MAC session key). Paragraph [0073] of Rule discloses one or more HSMs 330 may be configured to perform at least one of key derivations, decryption, and MAC operations. The one or more HSMs 330 may be contained within, or may be in data communication with, servers 320 and 325).
As to Claim 19, Rule discloses a communication device, comprising: a memory configured to store a computer program; and a processor configured to implement to: compute a key corresponding to current time according to initial keys, wherein the initial keys comprise at last one first initial key and a second initial key, the at least one first initial key is generated by a server, and the second initial key is generated by an encryption dedicated [field programmable gate array (FPGA) accelerator] (Paragraph [0120] of Rule discloses the session keys are independently derived at the one or more servers, resulting in a first session key (the ENC session key) and a second session key (the MAC session key). Paragraph [0073] of Rule discloses one or more HSMs 330 may be configured to perform at least one of key derivations, decryption, and MAC operations. The one or more HSMs 330 may be contained within, or may be in data communication with, servers 320 and 325);
generate a data message according to the key and to-be-transmitted data (Paragraph [0010] of Rule discloses generate an encrypted payload);
transmit the data message to a message receiving end (Paragraph [0181] of Rule discloses a server may receive the payload and the server may be configured to utilize symmetric key decryption to decrypt the payload);
generate a verification data message according to verification keys, wherein the verification keys comprise at last one first verification key and a second verification key, the at last one first verification key is obtained by searching the server, and the second verification key is obtained by searching the encryption dedicated [FPGA accelerator] (Paragraph [0044] of Rule discloses sends the MAC cryptogram to the application. Paragraph [0120] of Rule discloses the session keys are independently derived at the one or more servers, resulting in a first session key (the ENC session key) and a second session key (the MAC session key). Paragraph [0073] of Rule discloses one or more HSMs 330 may be configured to perform at least one of key derivations, decryption, and MAC operations. The one or more HSMs 330 may be contained within, or may be in data communication with, servers 320 and 325); and
transmit the verification data message to the message receiving end, and cause validity of the data message to be verified by the message receiving end according to the initial keys and the verification data message (Paragraph [0044] of Rule discloses sends the MAC cryptogram to the application. Paragraph [0046] of Rule discloses verifies the MAC cryptogram).
Rule does not explicitly disclose FPGA accelerator.
However, O’Doherty discloses this. Paragraph [0084] of O’Doherty discloses the HSM device may be implemented using an ASIC or a Field Programmable Gate Array (FPGA).
Examiner recites the same rationale to combine used for claim 1.
As to Claim 20, Rule discloses a non-volatile readable storage medium, storing a computer program, wherein the computer program, when executing the computer program, is configured to implement to:
compute a key corresponding to current time according to initial keys, wherein the initial keys comprise at last one first initial key and a second initial key, the at least one first initial key is generated by a server, and the second initial key is generated by an encryption dedicated [field programmable gate array (FPGA) accelerator] (Paragraph [0120] of Rule discloses the session keys are independently derived at the one or more servers, resulting in a first session key (the ENC session key) and a second session key (the MAC session key). Paragraph [0073] of Rule discloses one or more HSMs 330 may be configured to perform at least one of key derivations, decryption, and MAC operations. The one or more HSMs 330 may be contained within, or may be in data communication with, servers 320 and 325);
generate a data message according to the key and to-be-transmitted data (Paragraph [0010] of Rule discloses generate an encrypted payload);
transmit the data message to a message receiving end (Paragraph [0181] of Rule discloses a server may receive the payload and the server may be configured to utilize symmetric key decryption to decrypt the payload);
generate a verification data message according to verification keys, wherein the verification keys comprise at last one first verification key and a second verification key, the at last one first verification key is obtained by searching the server, and the second verification key is obtained by searching the encryption dedicated [FPGA accelerator] (Paragraph [0044] of Rule discloses sends the MAC cryptogram to the application. Paragraph [0120] of Rule discloses the session keys are independently derived at the one or more servers, resulting in a first session key (the ENC session key) and a second session key (the MAC session key). Paragraph [0073] of Rule discloses one or more HSMs 330 may be configured to perform at least one of key derivations, decryption, and MAC operations. The one or more HSMs 330 may be contained within, or may be in data communication with, servers 320 and 325); and
transmit the verification data message to the message receiving end, and cause validity of the data message to be verified by the message receiving end according to the initial keys and the verification data message (Paragraph [0044] of Rule discloses sends the MAC cryptogram to the application. Paragraph [0046] of Rule discloses verifies the MAC cryptogram).
Rule does not explicitly disclose FPGA accelerator.
However, O’Doherty discloses this. Paragraph [0084] of O’Doherty discloses the HSM device may be implemented using an ASIC or a Field Programmable Gate Array (FPGA).
Examiner recites the same rationale to combine used for claim 1.
As to Claim 21, Rule-O’Doherty discloses the communication method according to claim 13, wherein in an initialization phase of the FPGA accelerator cluster network, each encryption dedicated FPGA accelerator is responsible for uploading information of the encryption dedicated FPGA accelerator and information of an interconnected FPGA accelerator cluster corresponding to the encryption dedicated FPGA accelerator to the server, the information uploaded by the encryption dedicated FPGA accelerator is received and stored by the server, a key chain is generated by using a pseudorandom function (Paragraph [0140] of Rule discloses a network profile record ID (pNPR) and derivation key index (pDKI) may be used to identify which Issuer Master Keys to use in the cryptographic processes for authentication. Paragraph [0053] of Rule discloses independently generate keys from an initial shared master symmetric key in combination with a counter value, and thereby periodically replace the shared symmetric key being used).
Claims 8-12 are rejected under 35 U.S.C. 103 as being unpatentable over Rule-O’Doherty and further in view of US Pub. No. 2012/0011566 to Youm et al. (hereinafter “Youm”).
As to Claim 8, Rule-O’Doherty discloses the communication method according to claim 1. Rule-O’Doherty does not explicitly disclose wherein a time interval for updating a second-level key chain by the server is greater than a time interval for updating a first-level key chain by the server and less than a time interval for updating a key chain by the encryption dedicated FPGA accelerator; and the first-level key chain is a key chain generated by the server for the encryption dedicated FPGA accelerator, and the second-level key chain is a key chain generated by the server for the computation dedicated FPGA accelerator.
However, Youm discloses this. Paragraph [0015] of Youm discloses Paragraph [0015] of Youm discloses a higher layer having a key chain with a long interval and a lower layer having a key chain with a short interval are hierarchically interconnected, so as to reduce the update period of the authentication key.
It would have been obvious to one of ordinary skill in the art before the effective filing of the invention to combine the cryptographic system as disclosed by Rule-O’Doherty, with using different interval keychains as disclosed by Youm. One of ordinary skill in the art would have been motivated to combine to apply a known technique to a known device ready for improvement to yield predictable results. Rule and Youm are directed toward cryptographic systems and as such it would be obvious to use the techniques of one in the other. Paragraph [0015] of Youm discloses such a technique reduces the update period of the authentication key.
As to Claim 9, Rule-O’Doherty-Youm discloses the communication method according to claim 8, wherein the time interval for updating the first-level key chain by the server, the time interval for updating the second-level key chain by the server, and the time interval for updating a key chain by the encryption dedicated FPGA accelerator satisfy: Δ2 = n1*Δ1;and Δ3 = n2*Δ2;
wherein Δ1 denotes the time interval for updating the first-level key chain by the server, n.sub.1 denotes a number of keys in the first-level key chain, Δ2 denotes the time interval for updating the second-level key chain by the server, n.sub.2 denotes a number of keys in the second-level key chain, and Δ3 denotes the time interval for updating the key chain by the encryption dedicated FPGA accelerator (Paragraph [0015] of Youm discloses Paragraph [0015] of Youm discloses a higher layer having a key chain with a long interval and a lower layer having a key chain with a short interval are hierarchically interconnected, so as to reduce the update period of the authentication key. The claimed timed interval relationship is the obvious one to make sure that all possible combinations of the plurality of key chains is used. Namely the 2nd key chain only rotates once the first key chain has completely rotated to ensure that each key combination will be used).
As to Claim 10, Rule-O’Doherty discloses the communication method according to claim 1. Rule-O’Doherty does not explicitly disclose wherein computing the key corresponding to the current time according to the initial keys comprises: computing a time serial number corresponding to the current time according to the current time, initial time, and a time interval for updating a key chain; and computing the key corresponding to the current time according to the time serial number and the initial keys.
However, Youm discloses this. Paragraph [0028] of Youm discloses values of generated keys and certificates should be different according to the intervals.
Examiner recites the same rationale to combine used for claim 8.
As to Claim 11, Rule-O’Doherty-Youm discloses the communication method according to claim 10, wherein computing the time serial number corresponding to the current time according to the current time, the initial time, and the time interval for updating the key chain comprises: computing the time serial number corresponding to the current time according to
j = Tnow - T0 / Δ mod n;
wherein j denotes the time serial number, T.sub.now denotes the current time, T.sub.0 denotes the initial time, Δ denotes the time interval for updating the key chain, and n denotes a number of keys in the key chain (Paragraph [0028] of Youm discloses values of generated keys and certificates should be different according to the intervals).
Examiner recites the same rationale to combine used for claim 8.
As to Claim 12, Rule-O’Doherty-Youm discloses the communication method according to claim 10, wherein the computing the key corresponding to the current time according to the time serial number and the initial keys comprises: computing the key corresponding to the current time according to S.sub.j=S.sup.j(S.sub.0); wherein S.sub.j denotes the key corresponding to the current time, j denotes the time serial number, and S.sub.0 denotes the initial keys (Paragraph [0028] of Youm discloses values of generated keys and certificates should be different according to the intervals).
Examiner recites the same rationale to combine used for claim 8.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to Kevin S Mai whose telephone number is (571)270-5001. The examiner can normally be reached Monday to Friday 9AM to 5PM.
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/KEVIN S MAI/Primary Examiner, Art Unit 2499