DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claim(s) 1-3, 8, and 9 is/are rejected under 35 U.S.C. 102(a)(1) as being anticipated by JP 2015-530820 (‘820).
Regarding claim 1, fig. 1 of ‘820 discloses a clock duty calibration device, comprising: a duty control module [102] configured to generate a first clock [112] by adjusting a duty cycle of a received reference clock [110]; a duty measurement module [104, 106] configured to measure a duty cycle of the first clock based on an average voltage level (with LPF 104) of the first clock; and a control module [108] configured to generate a duty control code [122] based on the measured duty cycle so that the duty cycle of the first clock becomes a target duty cycle; and wherein the duty control module adjusts the duty cycle of the reference clock based on the duty control code.
Regarding claim 2, fig. 1 of ‘820 discloses wherein: the duty measurement module includes a low-pass filter unit [104]; and the low-pass filter unit generates a first voltage signal corresponding to the average voltage level of the first clock.
Regarding claim 3, fig. 1 of ‘820 discloses wherein: the duty measurement module comprises a reference signal generation unit [that generating 116] (not shown); and the reference signal generation unit generates a reference voltage signal [116] corresponding to the target duty cycle.
Regarding claims 8 and 9, these claims are merely methods to operate the circuit having structure recited in claims 1-3. Since ‘820 above teaches the structure, the methods to operate such a circuit are similarly disclosed.
Allowable Subject Matter
Claims 4-7 and 10-14 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure. Fon describes a testing ADC. Hussain describes a clock signal conversion circuit for high-speed serial data control. Ke describes an apparatus for performing clock and data duty cycle. Addepalli describes a duty cycle and skew corrector.
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/SIBIN CHEN/Primary Examiner, Art Unit 2836
