DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Status of Claims
Claims 1-19, 21, and 22 are pending. Claims 14 have been amended as per Applicants' request. Claims 20 have been canceled as per Applicants' request.
Information Disclosure Statement
The information disclosure statement (IDS) submitted on May 30, 2025 is/are in compliance with the provisional of 37 CFR 1.97. Accordingly, the information disclosure statement is being considered by the examiner.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale or otherwise available to the public before the effective filing date of the claimed invention.
Claim(s) 1-13 and 21 is/are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Huott et al. (US 2006/0156130) (hereinafter Huott) (published July 13, 2006).
Regarding Claim 1, Huott discloses A method for controlling storage resources in a storage node, comprising:
“As shown in FIG. 1, cluster 104 includes a plurality of processor nodes 115, each of which can include one or more processors which cooperate together in executing computing tasks. Each processor node 115 also typically includes one or more local or main memory components, displays, printers, input output (I/O) devices or computer devices that are networked together. A communication network 130 provides communication between the processor nodes 115, as well as between the processor nodes and one or more storage units 120” (Huott [0014])
in a process of deleting a cache partition in a storage node,
“When it is determined that one of the subdivisions of the cache memory determined defective by the BIST is non-repairable, the SE logically deletes the defective subdivision from the system configuration, and the SE is operable to permit the processor to operate without the logically deleted subdivision” (Huott [0007])
“In a variation of this procedure, when it is determined that the number of failing elements within a particular set portion of the cache memory exceeds a threshold, the SE can temporarily take the affected processor core offline and invoke ABIST to test the cache memory of the affected processor core. If the ABIST determines that one of the set portions of the cache memory is failing, the SE can then delete the failing set portion from the configuration of the system” (Huott [0033])
detecting an operation state of a currently executed operation process,
“Another way in which the invention can be utilized is during recovery operations which occur during the normal (task-executing) operation of the computing system” (Huott [0033] the operational state is normal)
wherein the deletion of the cache partition comprises one or more operation processes, and the one or more operation processes comprise the currently executed operation process;
“At this step, the SE may perform other repairs to the processor core of the chip, including the replacement of defective wordlines or defective columns of the cache memory. After these repairs have been made, the ABIST preferably tests the condition of the entire cache memory of the chip again from block 410. Occasionally, the repair of defective wordlines or defective columns changes the status of the set portion of the cache memory from failing to good. In such case, upon retesting, the ABIST determines that there no longer is a failing set portion of the array” (Huott [0029] the operation processes includes at least initial testing, repair process, and retesting)
“Another way in which the invention can be utilized is during recovery operations which occur during the normal (task-executing) operation of the computing system” (Huott [0033] the recovery operations are the currently executed operation process)
The limitations of “in cases where it is detected that the operation state indicates that the currently executed operation process fails to be completed, detecting a target scenario which causes the currently executed operation process to fail to be completed; restoring the currently executed operation process to a target operation process according to the target scenario; and executing the target operation process, wherein the target operation process is used for continuing to realize the deletion of the cache partition starting from a target partition state of the cache partition which is indicated by the target scenario” are contingent upon when “it is detected that the operation state indicates that the currently executed operation process fails to be completed”, without a positive recitation of the results from the detection, the limitations are directed to steps not required to be perform by the claims since the condition is not present. “The broadest reasonable interpretation of a method (or process) claim having contingent limitations requires only those steps that must be performed and does not include steps that are not required to be performed because the condition(s) precedent are not met. For example, assume a method claim requires step A if a first condition happens and step B if a second condition happens. If the claimed invention may be practiced without either the first or second condition happening, then neither step A or B is required by the broadest reasonable interpretation of the claim. If the claimed invention requires the first condition to occur, then the broadest reasonable interpretation of the claim requires step A. If the claimed invention requires both the first and second conditions to occur, then the broadest reasonable interpretation of the claim requires both steps A and B” (MPEP 2111.04).
Regarding Claims 2-11, 13, and 21, these dependent claims are contingent upon the contingent limitation in claim 1 and therefore the limitations are directed to steps not required to be perform by the claims since the condition is not present. “The broadest reasonable interpretation of a method (or process) claim having contingent limitations requires only those steps that must be performed and does not include steps that are not required to be performed because the condition(s) precedent are not met. For example, assume a method claim requires step A if a first condition happens and step B if a second condition happens. If the claimed invention may be practiced without either the first or second condition happening, then neither step A or B is required by the broadest reasonable interpretation of the claim. If the claimed invention requires the first condition to occur, then the broadest reasonable interpretation of the claim requires step A. If the claimed invention requires both the first and second conditions to occur, then the broadest reasonable interpretation of the claim requires both steps A and B” (MPEP 2111.04).
Regarding Claim 12, Huott further discloses wherein detecting the operation state of a currently executed current operation process comprises: detecting whether the cache partition fails during execution of the currently executed operation process;
“As shown at 420, a result of the ABIST testing is a determination of a failure condition, or, alternatively, lack of a failure condition, i.e., a "pass" condition” (Huott [0026])
“Another way in which the invention can be utilized is during recovery operations which occur during the normal (task-executing) operation of the computing system. During such operation, a number of errors can occur which are determined to be due to failures in a certain region of the cache memory, such as failing wordlines located within a certain set portion of the cache memory” (Huott [0033])
in cases where it is detected that the cache partition has failed, determining that the operation state indicates that the currently executed operation process cannot be completed; and
“On the other hand, when two or more set portions of the cache are found to be failing, the ABIST reports the condition to the SE as unrepairable. In such case, the processor core which contains the two or more failing set portions is determined to be failing and not repairable” (Huott [0031])
“In a variation of this procedure, when it is determined that the number of failing elements within a particular set portion of the cache memory exceeds a threshold, the SE can temporarily take the affected processor core offline and invoke ABIST to test the cache memory of the affected processor core” (Huott [0033])
in cases where it is detected that the cache partition has not failed, determining that the operation state indicates that the currently executed operation process can be completed.
“When the ABIST determines the "pass" condition, that result is provided to the SE, which then continues powering on the computing system, as shown at step 490” (Huott [0026])
“when the ABIST determines that a set portion of the cache memory of the single processor system is failing at time of power-on, configuration logic circuitry of such processor can perform the deletion of the failing set portion to allow the processor to continue powering on and to operate” (Huott [0035])
Allowable Subject Matter
Claims 14-19 and 22 are allowed.
The following is an examiner’s statement of reasons for allowance:
Claim 14 recites the limitations “a cache partition configuration end and a cache partition service end, wherein the cache partition configuration end is configured to detect, in a process of deleting a cache partition in a storage node, an operation state of a currently executed current operation process, wherein the deletion of the cache partition comprises one or more operation processes, and the one or more operation processes comprise the currently executed operation process; in cases where it is detected that the operation state indicates that the currently executed operation process fails to be completed, detect a target scenario which causes the currently executed operation process to fail to be completed; restore the currently executed operation process to a target operation process according to the target scenario; and execute a target operation process, wherein the target operation process is used for continuing to realize the deletion of the cache partition starting from a target partition state of the cache partition which is indicated by the target scenario; and the cache partition service end is configured to execute, in respond to the cache partition configuration end executes the target operation process, an instruction delivered by the cache partition configuration end” in combination with the other elements recited, which is not found in the prior art of record.
The prior art of record does not teach or render obvious the limitation noted above, particularly in combination with the other limitations within the claims. The dependent claims are allowable for at least the same reasons as its respective independent claim.
Any comments considered necessary by applicant must be submitted no later than the payment of the issue fee and, to avoid processing delays, should preferably accompany the issue fee. Such submissions should be clearly labeled “Comments on Statement of Reasons for Allowance.”
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure.
KAWAMURA (US 2008/0177975) discloses an instruction to delete from the cache memory cache partition areas associated with a database buffer.
Novakovsky et al. (US 2014/0258618) discloses removable cache portions and by removing some or all of the cache portion, the integrated circuit can have different cache configurations for multiple platforms.
Won et al. (US 2023/021502) discloses cache portions with a predefined size and removing the cache portions with respect to the current plan cache size.
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/S.L./Examiner, Art Unit 2137
/Arpan P. Savla/Supervisory Patent Examiner, Art Unit 2137
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