Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Priority
Receipt is acknowledged of certified copies of papers required by 37 CFR 1.55.
Information Disclosure Statement
The information disclosure statement (lDS) submitted are in compliance with the provisions of 37 CFR 1.97 and have been considered by the Examiner.
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale or otherwise available to the public before the effective filing date of the claimed invention.
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
Claims 1-3, 8-10 and 24 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by WIPO Patent Publication No. WO 2021159231 A1 to TAKAO et al. (hereafter “TAKAO”).
Regarding claim 1, TAKAO teaches a solid-state imaging device (event based image sensors), comprising:
a pixel array unit that includes a plurality of pixels, wherein each pixel in the plurality of pixels is configured to generate charge by photoelectric conversion (Figs. 18-21, [0069]-[0073]: pixel units including photodiodes), wherein the plurality of pixels includes:
a plurality of event pixels, wherein each pixel of the plurality of event pixels is configured to generate an event signal on a basis of a luminance change of incident light (Figs. 18-21, [0069]-[0073]: photodiode denoted by “E” in each pixel unit 300 is used for event detection);
and a plurality of gradation pixels, wherein each pixel of the plurality of gradation pixels is configured to generate a luminance signal on a basis of an amount of incident light (Figs. 18-21, [0069]-[0073]: photodiodes used for obtaining frame based images);
and a plurality of color filters, wherein at least one color filter of the plurality of color filters is disposed over each pixel of the plurality of pixels (Figs. 18-21: a color filter array, bayer array, Quad bayer array, RGB, RYYB, RGBW and other arranged on the pixel units),
wherein the color filters disposed over the event pixels are at least one of white color filters or cyan color filters (Figs. 18-21, [0069]-[0073]: A clear or complementary color filter may be placed on the photodiode used for event detection to raise its sensitivity.),
and wherein the color filters disposed over the gradation pixels are at least one of red color filters, green color filters, or blue color filters (Figs. 18-21, [0069]-[0073]: “F/G” denotes a photodiode used for obtaining frame based images with a green filter (shown with a coarsely shaded rectangle) , “F/R” denotes a photodiode used for obtaining frame based images with a red filter (shown with a hatched rectangle) , “F/B” denotes a photodiode used for obtaining frame based images with a blue filter (shown with a densely shaded rectangle)).
Regarding claim 2, TAKAO teaches the solid-state imaging device according to claim 1, in addition TAKAO discloses wherein an arrangement of the event pixels and the gradation pixels does not have 180 degree rotational symmetry (as illustrated by Figs. 18-21, [0069]-[0073]: pixel units arrangement).
Regarding claim 3, TAKAO teaches the solid-state imaging device according to claim 1, in addition TAKAO discloses wherein the color filters disposed over the event pixels include either white color filters or cyan color filters (Figs. 18-21, [0069]-[0073]: A clear or complementary color filter (Examiner notes that it includes a cyan as a true complementary color) may be placed on the photodiode used for event detection to raise its sensitivity.),
and wherein the color filters disposed over the gradation pixels include red color filters, green color filters, and blue color filters (as illustrated by Figs. 18-21, [0069]-[0073]: “F/G” denotes a photodiode used for obtaining frame based images with a green filter (shown with a coarsely shaded rectangle) , “F/R” denotes a photodiode used for obtaining frame based images with a red filter (shown with a hatched rectangle) , “F/B” denotes a photodiode used for obtaining frame based images with a blue filter (shown with a densely shaded rectangle)).
Regarding claim 8, TAKAO teaches the solid-state imaging device according to claim 1, in addition TAKAO discloses wherein a ratio of a number of the event pixels to a total number of the event pixels and the gradation pixels included in the pixel array unit is 25% or smaller (as illustrated by Figs. 18-21, [0069]-[0073]: number of “E” event detection is smaller than 25%).
Regarding claim 9, TAKAO teaches the solid-state imaging device according to claim 8, in addition TAKAO discloses wherein the ration of the number of the event pixels to the total number of the event pixels and the gradation pixels included in the pixel array unit is 12.5% or smaller (as illustrated by Figs. 18-21, [0069]-[0073]: number of “E” event detection is smaller than 12.5%).
Regarding claim 10, TAKAO teaches the solid-state imaging device according to claim 1, in addition TAKAO discloses wherein each of the event pixels includes an event-based vision sensor (EVS) pixel (as illustrated by Figs. 18-21, [0069]-[0073]: event based image sensors).
Regarding claim 24, claim 24 has been analyzed and rejected with regard to claim 1 and in accordance with TAKAO's further teaching on: An electronic apparatus, comprising: an imaging apparatus ([0002]&[0053]: a Dynamic Vision Sensor (DVS) , is expected to be applied mainly as a component of a new camera system for mobile devices).
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 4-6 are rejected under 35 U.S.C. 103 as being unpatentable over WIPO Patent Publication No. WO 2021159231 A1 to TAKAO et al. (hereafter “TAKAO”), in view of LEE et al. (US 20170141149 A1 , hereinafter “LEE”).
Regarding claim 4, TAKAO teaches the solid-state imaging device according to claim 1, in addition TAKAO discloses wherein the color filters disposed over the event pixels include white color filters (as illustrated by Figs. 18-21, [0069]-[0073]: A clear or complementary color filter may be placed on the photodiode used for event detection to raise its sensitivity.),
and wherein the color filters disposed over the gradation pixels include red color filters, green color filters, and blue color filters (as illustrated by Figs. 18-21, [0069]-[0073]:: “F/G” denotes a photodiode used for obtaining frame based images with a green filter (shown with a coarsely shaded rectangle) , “F/R” denotes a photodiode used for obtaining frame based images with a red filter (shown with a hatched rectangle) , “F/B” denotes a photodiode used for obtaining frame based images with a blue filter (shown with a densely shaded rectangle)).
TAKAO does not teach wherein the color filters disposed over the event pixels include both white color filters and cyan color filters
However, LEE discloses wherein the color filters disposed over the both white color filters and cyan color filters (as illustrated by Figs. 25-26, [0147]-[0150]: an image sensor that includes cyan color filters 2520 and white color filters 2520).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to incorporate wherein the color filters disposed over the event pixels include both white color filters and cyan color filters as taught by LEE into TAKAO image device. The suggestion/ motivation for doing so would be to provide improved light absorption efficiency and sensitivity than other image sensors under various illumination environments (LEE: [0150]).
Regarding claim 5, TAKAO and LEE combination teaches the solid-state imaging device according to claim 4, in addition TAKAO discloses wherein an event pixel located adjacent to a gradation pixel having a blue color filter has a cyan color filter (as illustrated by Figs. 18-21: A clear or complementary color filter (Examiner notes that it includes a cyan as a true complementary color) placed on the “E” event detection adjacent to “F/B” photodiode with a blue filter).
Regarding claim 6, TAKAO and LEE combination teaches the solid-state imaging device according to claim 4, in addition TAKAO discloses wherein an event pixel located adjacent to a gradation pixel having a color filter in any color other than blue has a white color filter (as illustrated by Figs. 18-22: A clear or complementary color filter placed on the “E” event detection adjacent to “F/R”, “F/G” color filters).
Claim 7 is rejected under 35 U.S.C. 103 as being unpatentable over TAKAO and LEE combination as applied above, in view of the court case Law. In re Japikse, 86 USPQ 70.
Regarding claim 7, TAKAO and LEE combination teaches the solid-state imaging device according to claim 4, in addition TAKAO discloses wherein each of the event pixels located in a central portion of the pixel array unit has a white color filter (as illustrated by Fig. 21, [0074]: event detection photodiode “E” arranged in the central portion of the “F” photodiodes array), except wherein each of the event pixels located in a peripheral portion of the pixel array unit has a cyan color filter. However, It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to incorporate wherein each of the event pixels located in a peripheral portion of the pixel array unit has a cyan color filter, since it has been held that rearranging parts of an invention involves only routine skill in the art. In re Japikse, 86 USPQ 70.
Claims 11-12 and 16-18 are rejected under 35 U.S.C. 103 as being unpatentable over WIPO Patent Publication No. WO 2021159231 A1 to TAKAO et al. (hereafter “TAKAO”), in view of NAKAMOTO et al. (US 20180301491 A1, hereinafter “NAKAMOTO”).
Regarding claim 11, TAKAO teaches the solid-state imaging device according to claim 1, except wherein first light shielding walls are provided between the color filters of the plurality of pixels.
However, NAKAMOTO discloses wherein first light shielding walls are provided between the color filters of the plurality of pixels (as illustrated by Figs. 5-10, [0075]: wall 50 provided between color filters of any one of red (R), green (G), or blue (B)).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to incorporate wherein first light shielding walls are provided between the color filters of the plurality of pixels as taught by NAKAMOTO into TAKAO image device. The suggestion/ motivation for doing so would be to prevent color mixing between color filters of adjacent pixels (NAKAMOTO: [0002]).
Regarding claim 12, TAKAO and NAKAMOTO combination teaches the solid-state imaging device according to claim 11, in addition NAKAMOTO discloses wherein each of the first light shielding walls includes a low refractive index material structure or an air structure (as illustrated by Figs. 5-10, [0078]: the wall 50 provided with low refractive index films). The suggestion/ motivation for doing so would be to prevent color mixing between color filters of adjacent pixels (NAKAMOTO: [0002]).
Regarding claim 16, TAKAO teaches the solid-state imaging device according to claim 1, except further comprising: a plurality of on-chip lenses, wherein one on-chip lens of the plurality of on-chip lenses is disposed over the color filter of each pixel of the plurality of pixels, and wherein each on-chip lens collects incident light , and; a plurality of second light shielding walls, wherein one second light shielding wall of the plurality of light shielding walls is disposed between each adjacent pair of on- chip lenses of the plurality of pixels.
However, NAKAMOTO discloses a plurality of on-chip lenses, wherein one on-chip lens of the plurality of on-chip lenses is disposed over the color filter of each pixel of the plurality of pixels, and wherein each on-chip lens collects incident light (as illustrated by Figs. 5&9-10, [0075]-[0076]&[0097]: an on-chip lens 48 is formed for each pixel 2), and;
a plurality of second light shielding walls, wherein one second light shielding wall of the plurality of light shielding walls is disposed between each adjacent pair of on- chip lenses of the plurality of pixels (as illustrated by Figs. 5-10, [0075]-[0076]&[0097]: wall 50 and wall 100 provided between color filters and on-chip lens 48).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to incorporate a plurality of on-chip lenses, wherein one on-chip lens of the plurality of on-chip lenses is disposed over the color filter of each pixel of the plurality of pixels, and wherein each on-chip lens collects incident light , and; a plurality of second light shielding walls, wherein one second light shielding wall of the plurality of light shielding walls is disposed between each adjacent pair of on- chip lenses of the plurality of pixels as taught by NAKAMOTO into TAKAO image device. The suggestion/ motivation for doing so would be to prevent color mixing between color filters of adjacent pixels (NAKAMOTO: [0002]).
Regarding claim 17, TAKAO and NAKAMOTO combination teaches the solid-state imaging device according to claim 16, in addition NAKAMOTO discloses further comprising: a plurality of waveguides, wherein one waveguide in the plurality of waveguides is provided on each of at least some color filters of the plurality of color filters, and wherein each wave guide constitutes an optical path for incident light (as illustrated by Figs. 5-10, [0075]-[0076]&[0097]: walls 50 and 100 forming a shielding and have an optical path property as shown in Fig. 10).
Regarding claim 18, TAKAO and NAKAMOTO combination teaches the solid-state imaging device according to claim 17, in addition NAKAMOTO discloses wherein the waveguides are provided on the white color filters or the cyan color filters (as illustrated by Figs. 5-10, [0075]-[0076]&[0097]: wall 50 and wall 100 provided between each color filters and on-chip lens 48).
Claims 13-15 are rejected under 35 U.S.C. 103 as being unpatentable over TAKAO and NAKAMOTO combination as applied above, in view of Mehta et al. (US 20210074745 A1, hereinafter “Mehta”).
Regarding claim 13, TAKAO and NAKAMOTO combination teaches the solid-state imaging device according to claim 11, except wherein each of the first light shielding walls provided between the color filters of the gradation pixels and the color filters of adjacent event pixels has a thickness different from a thickness of each of the first light shielding walls provided between the color filters of the gradation pixels and the color filters of adjacent gradation pixels.
However, Mehta discloses wherein each of the first light shielding walls provided between the color filters of the gradation pixels and the color filters of adjacent event pixels has a thickness different from a thickness of each of the first light shielding walls provided between the color filters of the gradation pixels and the color filters of adjacent gradation pixels (Figs. 11-12, [0138]-[0139]: full thickness dielectric trench (RFTI) 1208 structures can be formed around each event detection pixel 503. Similarly, RFTI 1208 and/or rear deep trench isolation (RDTI) 1212 structures can be formed around individual image sensing pixels 502. Examiner further notes that specific design layout depend on fabrication techniques, application and/or allowable errors, dictated by fabrication process).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to incorporate wherein each of the first light shielding walls provided between the color filters of the gradation pixels and the color filters of adjacent event pixels has a thickness different from a thickness of each of the first light shielding walls provided between the color filters of the gradation pixels and the color filters of adjacent gradation pixels as taught by Mehta into TAKAO and NAKAMOTO combination. The suggestion/ motivation for doing so would be to reduce cross talk, improve light-reception efficiencies. More particularly, provide an imaging device with improved occupation ratios. (Mehta: [0007]).
Regarding claim 14, TAKAO, NAKAMOTO and Mehta combination teaches the solid-state imaging device according to claim 13, in addition Mehta discloses wherein each of the first light shielding walls provided between the color filters of the gradation pixels each having a blue color filter and the color filters of the adjacent event pixels has a thickness larger than the thickness of each of the first light shielding walls provided between the color filters of the gradation pixels and the color filters of the adjacent gradation pixels (Figs. 11-12, [0138]-[0139]: full thickness dielectric trench (RFTI) 1208 structures can be formed around each event detection pixel 503. Similarly, RFTI 1208 and/or rear deep trench isolation (RDTI) 1212 structures can be formed around individual image sensing pixels 502. Examiner further notes that specific design layout depend on fabrication techniques, application and/or allowable errors, dictated by fabrication process and specific applications).
Regarding claim 15, TAKAO, NAKAMOTO and Mehta combination teaches the solid-state imaging device according to claim 13, in addition Mehta discloses wherein each of the first light shielding walls provided between the color filters of the gradation pixels each having a color filter in any color other than blue and the color filters of the adjacent event pixels has a thickness smaller than the thickness of each of the first light shielding walls provided between the color filters of the gradation pixels and the color filters of the adjacent gradation pixels (Figs. 11-12, [0138]-[0139]: full thickness dielectric trench (RFTI) 1208 structures can be formed around each event detection pixel 503. Similarly, RFTI 1208 and/or rear deep trench isolation (RDTI) 1212 structures can be formed around individual image sensing pixels 502. Examiner further notes that specific design layout depend on fabrication techniques, application and/or allowable errors, dictated by fabrication process and specific applications).
Claim 19 is rejected under 35 U.S.C. 103 as being unpatentable over WIPO Patent Publication No. WO 2021159231 A1 to TAKAO et al. (hereafter “TAKAO”), in view of KIM; Sung-Man (US 20180158864 A1, hereinafter “KIM”).
Regarding claim 19, TAKAO teaches the solid-state imaging device according to claim 1, in addition TAKAO discloses wherein each pixel of the plurality of pixels further includes a photodiode that is located within a semiconductor substrate below the color filter and performs photoelectric conversion (Figs. 18-21: pixel units including photodiodes),
TAKAO does not teach the solid-state imaging device further comprising: third light shielding walls, wherein the third light shielding walls penetrate an interior of the semiconductor substrate and are provided between the photodiodes of the plurality of pixels.
However, KIM discloses the solid-state imaging device further comprising: third light shielding walls, wherein the third light shielding walls penetrate an interior of the semiconductor substrate and are provided between the photodiodes of the plurality of pixels (as illustrated by Figs. 4, [0069]: isolation regions 15 and 16 between photodiodes).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to incorporate the solid-state imaging device further comprising: third light shielding walls, wherein the third light shielding walls penetrate an interior of the semiconductor substrate and are provided between the photodiodes of the plurality of pixels as taught by KIM into TAKAO image device. The suggestion/ motivation for doing so would be to prevent color mixing and crosstalk between adjacent pixels.
Claim 20 is rejected under 35 U.S.C. 103 as being unpatentable over TAKAO and LEE combination as applied above, in view of LEE et al. (US 20210075985 A1, hereinafter “LEE”).
Regarding claim 20, TAKAO and KIM combination teaches the solid-state imaging device according to claim 19, except further comprising: fourth light shielding walls, wherein the fourth light shielding walls are provided between the plurality of pixels within an insulation film below the semiconductor substrate.
However, LEE discloses further comprising: fourth light shielding walls, wherein the fourth light shielding walls are provided between the plurality of pixels within an insulation film below the semiconductor substrate (as illustrated by Fig. 13, [0110]: contact hole H2 surrounded by an insulating film 242 extended below substrate 210).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to incorporate fourth light shielding walls, wherein the fourth light shielding walls are provided between the plurality of pixels within an insulation film below the semiconductor substrate as taught by LEE into TAKAO and KIM combination. The suggestion/ motivation for doing so would be to improve photoelectric conversion efficiency (LEE: [0119]).
Claim 23 is rejected under 35 U.S.C. 103 as being unpatentable over WIPO Patent Publication No. WO 2021159231 A1 to TAKAO et al. (hereafter “TAKAO”),, in view of Mehta et al. (US 20210074745 A1, hereinafter “Mehta”).
Regarding claim 23, TAKAO teaches the solid-state imaging device according to claim 1, except wherein, for each pixel in the plurality of pixels, each event pixel is adjacent one other event pixel, and wherein each pair of adjacent event pixels has a color filter of a same type.
However, Mehta discloses wherein, for each pixel in the plurality of pixels, each event pixel is adjacent one other event pixel, and wherein each pair of adjacent event pixels has a color filter of a same type (Figs. 11, [0138]-[0139]: Two event detection pixels 503 having same filters).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to incorporate wherein, for each pixel in the plurality of pixels, each event pixel is adjacent one other event pixel, and wherein each pair of adjacent event pixels has a color filter of a same type as taught by Mehta into TAKAO and NAKAMOTO combination. The suggestion/ motivation for doing so would be to improve light-reception efficiencies. More particularly, provide an imaging device with improved occupation ratios (Mehta: [0007]).
Contact
Any inquiry concerning this communication or earlier communications from the examiner should be directed to ABDELAAZIZ TISSIRE whose telephone number is (571)270-7204. The examiner can normally be reached on Monday through Friday from 8 AM to 5 PM.
Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Ye Lin can be reached on 571-272-7372. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
Information regarding the status of an application may be obtained from the Patent Application Information Retrieval (PAIR) system. Status information for published applications may be obtained from either Private PAIR or Public PAIR. Status information for unpublished applications is available through Private PAIR only. For more information about the PAIR system, see http://pair-direct.uspto.gov. Should you have questions on access to the Private PAIR system, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative or access to the automated information system, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000.
/ABDELAAZIZ TISSIRE/ Primary Examiner, Art Unit 2638
Prosecution Insights