Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claims 1-20 are presented for examination.
Claim Objections
Claim 3-4, 6-7, 9-10, 13-14, and 16-19 objected to because of the following informalities:
In claim 3, line 2, “configured to” should read “further configured to”
In claim 4, line 2, “configured to” should read “further configured to”
In claim 6, line 2, “configured to” should read “further configured to”
In claim 7, line 2, “configured to” should read “further configured to”
In claim 9, line 2, “configured to” should read “further configured to”
In claim 10, line 2, “configured to” should read “further configured to”
In claim 13, line 2, “configured to” should read “further configured to”
In claim 14, line 2, “configured to” should read “further configured to”
In claim 16, line 2, “configured to” should read “further configured to”
In claim 17, line 2, “configured to” should read “further configured to”
In claim 18, line 5, “configured to” should read “further configured to”
In claim 19, line 2, “configured to” should read “further configured to”
Appropriate correction is required.
Claim Rejections - 35 USC § 112
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claim 10 and 19 rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention.
Claim 10 recites the limitation "the second portion of the combined parity information" in line 6. There is insufficient antecedent basis for this limitation in the claim.
Claim 19 recites the limitation "the second portion of the combined parity information" in line 6. There is insufficient antecedent basis for this limitation in the claim.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
Claim(s) 1-20 is/are rejected under 35 U.S.C. 102(a)(1) and (a)(2) as being anticipated by Wu et al. (US 20180137005 A1), hereinafter Wu.
As per claim 1, Wu teaches a memory device comprising:
a first memory die (Memory Device 740 in Fig. 7; “Memory devices 740 represent memory resources for system 700. In one example, each memory device 740 is a separate memory die.” Wu Paragraph [0087]) comprising:
a first interface circuit (“Each memory device 740 includes I/O interface logic 742” Wu paragraph [0087]);
a first memory array (“Memory resources 760 represent individual arrays of memory locations or storage locations for data” Wu paragraph [0089]); and
a first error correction circuit coupled to the first interface circuit and to first memory array (“In one example, the error detection mechanism includes internal and external ECC logic. It will be understood that internal ECC logic refers to logic within the memory device itself,” Wu Paragraph [0063]); and
a second memory die vertically stacked (“The multiple memory dies can be a vertical stack” Wu Paragraph [0025]) with the first memory die, the second memory dies comprising:
a second interface circuit (“Each memory device 740 includes I/O interface logic 742” Wu paragraph [0087]);
a second memory array (“Memory resources 760 represent individual arrays of memory locations or storage locations for data.” Wu paragraph [0089]); and
a second error correction circuit coupled to the second interface circuit (“In one example, the error detection mechanism includes internal and external ECC logic. It will be understood that internal ECC logic refers to logic within the memory device itself,” Wu Paragraph [0063]) to generate parity information for data to be stored in the memory device, and wherein at least a portion of the parity information is stored in the first memory array of the first memory die and in the second memory array of the second memory die (“Redundancy logic 780 includes one or more memory resources that are spares or that provide parity services, or both” Wu Paragraph [0097]).
As per claim 2, Wu teaches the memory device of claim 1 as stated above (See 35 U.S.C. 102 rejection for claim 1 for further details). Wu further teaches the second interface circuit of the second memory die is configured to receive an entire data word to be stored at the memory device (“Redundancy logic 780 represents logic within memory device 740 to provide redundancy for memory device 740 to achieve error recovery for memory resources that store an entire cacheline of data.” Wu Paragraph [0097]).
As per claim 3, Wu teaches the memory device of claim 2 as stated above (See 35 U.S.C. 102 rejection for claim 2 for further details). Wu further teaches the second error correction circuit of the second memory die is further configured to: generate the parity information for the entire data word (“Redundancy logic 780 includes one or more memory resources that are spares or that provide parity services, or both” Wu Paragraph [0097]);
store a first portion of the data word and a first portion of the parity information in the second memory array of the second memory die (“For a Write operation, an individual memory device 740 can write a portion of the overall data word” Wu Paragraph [0087]); and
provide a second portion of the data word and a second portion of the parity information to the first memory die to be stored in the first memory array of the first memory die (“The remaining bits of the word will be provided or received by other memory devices in parallel.” Wu Paragraph [0087]).
As per claim 4, Wu teaches the memory device of claim 3 as stated above (See 35 U.S.C. 102 rejection for claim 3 for further details). Wu further teaches the second error correction circuit of the second memory die is further configured to:receive the first portion of the data word and the first portion of the parity information from the second memory array of the second memory die (“memory device responding to a command, and accessing memory resources 760 internal to each.” Wu Paragraph [0087]); receive the second portion of the data word and the second portion of the parity information from the first memory die (“each stack includes 5 receivers, and each receiver is connected to the lower stack” Wu Paragraph [0068]; Wu teaches data being transferred between memory dies.); and correct one or more errors in the first portion of the data and the second portion of the data using the first portion of the parity information and the second portion of the parity information (“Redundancy logic 780 represents logic within memory device 740 to provide redundancy for memory device 740 to achieve error recovery for memory resources” Wu Paragraph [0097]).
As per claim 5, Wu teaches the memory device of claim 1 as stated above (See 35 U.S.C. 102 rejection for claim 1 for further details). Wu further teaches first interface circuit of the first memory die is configured to receive at least a portion of an entire data word to be stored at the memory device (“For a Write operation, an individual memory device 740 can write a portion of the overall data word” Wu Paragraph [0087]), and wherein the second interface circuit of the second memory die is also configured to receive at least a portion of the entire data word (“The remaining bits of the word will be provided or received by other memory devices in parallel.” Wu Paragraph [0087]).
As per claim 6, Wu teaches the memory device of claim 5 as stated above (See 35 U.S.C. 102 rejection for claim 5 for further details). Wu further teaches the second error correction circuit of the second memory die is further configured to: generate the parity information for the entire data word (“Redundancy logic 780 represents logic within memory device 740 to provide redundancy for memory device 740 to achieve error recovery for memory resources that store an entire cache line of data. Redundancy logic 780 includes one or more memory resources that are spares or that provide parity services, or both.” Wu Paragraph [0097]); and store a first portion of the data word and a first portion of the parity information in the second memory array of the second memory die (“For a Write operation, an individual memory device 740 can write a portion of the overall data word” Wu Paragraph [0087]).
As per claim 7, Wu teaches the memory device of claim 6 as stated above (See 35 U.S.C. 102 rejection for claim 6 for further details). Wu further teaches the second error correction circuit of the second memory dies is further configured to: receive the first portion of the data word and the first portion of the parity information from the second memory array of the second memory die (“memory device responding to a command, and accessing memory resources 760 internal to each.” Wu Paragraph [0087]); receive a second portion of the data word and a second portion of the parity information from the first memory die (“each stack includes 5 receivers, and each receiver is connected to the lower stack” Wu Paragraph [0068]; Wu teaches data can be transferred between memory dies.); and correct one or more errors in the first portion of the data using the first portion of the parity information and the second portion of the parity information (“Redundancy logic 780 represents logic within memory device 740 to provide redundancy for memory device 740 to achieve error recovery for memory resources” Wu Paragraph [0097]).
As per claim 8, Wu teaches the memory device of claim 1 as stated above (See 35 U.S.C. 102 rejection for claim 1 for further details). Wu further teaches the first interface circuit of the first memory die is configured to receive a first portion of a data word to be stored at the memory device (“Write operation, an individual memory device 740 can write a portion of the overall data word” Wu Paragraph [0087]), and the second interface circuit of the second memory die is configured to receive a second portion of the data word (“The remaining bits of the word will be provided or received by other memory devices in parallel.” Wu Paragraph [0087]).
As per claim 9, Wu teaches the memory device of claim 8 as stated above (See 35 U.S.C. 102 rejection for claim 8 for further details). Wu further teaches the second error correction circuit of the second memory dies is further configured to:generate a first portion of the parity information for the second portion of the data word (“Redundancy logic 780 includes one or more memory resources that are spares or that provide parity services, or both.” Wu Paragraph [0097]); receive a second portion of the parity information for the first portion of the data word from the first memory die (“each stack includes 5 receivers, and each receiver is connected to the lower stack” Wu Paragraph [0068]; Wu teaches data being transferred between memory dies.); generate combined parity information based on the first portion and the second portion of the parity information (“In one example, the value of the parity information is an XOR of all the segments of data.” Wu Paragraph [0066]); and store the second portion of the data word and a first portion of the combined parity information in the second memory array of the second memory die (“Redundancy logic 780 represents logic within memory device 740 to provide redundancy for memory device 740 to achieve error recovery for memory resources that store an entire cacheline of data. Redundancy logic 780 includes one or more memory resources that are spares or that provide parity services, or both.” Wu paragraph [0097]).
As per claim 10, Wu teaches the memory device of claim 9 as stated above (See 35 U.S.C. 102 rejection for claim 9 for further details). Wu further teaches the second error correction circuit of the second memory die is further configured to: receive the second portion of the data word and the first portion of the combined parity information from the second memory array of the second memory dies (“each stack includes 5 receivers, and each receiver is connected to the lower stack” Wu Paragraph [0068]; Wu teaches data can be transferred between dies.); calculate a first sub-result based on the second portion of the data word (“In one example, the memory reads Data A[old], 604, and computes Delta=A[old] XOR A[new] locally at the memory stack, 606” Wu Paragraph [0074]; receive the second portion of the combined parity information and a second sub-result from the first memory die, wherein the second sub-result is calculated based on the first portion for the data word (“each stack includes 5 receivers, and each receiver is connected to the lower stack” Wu Paragraph [0068]; Wu teaches data being transferred between dies.); and correct one or more errors in the second portion of the data using the first portion and the second portion of the combined parity information and using the first sub-result and the second sub-result (“In one example, each die includes multiple separate XOR circuits to calculate: P_new=P_old̂ΔÂΔB̂ΔC.” Wu Paragraph [0053]).
As per claim 11, Wu teaches a memory device comprising; a plurality of memory die arranged in a vertical stack (“The multiple memory dies can be a vertical stack” Wu Paragraph [0025]), wherein each of the plurality of memory die comprises a memory array (“Memory resources 760 represent individual arrays of memory locations or storage locations for data.” Wu paragraph [0089]) and an error correction circuit, wherein the error correction circuit at least one of the plurality of memory dies is configured to generate parity information for data to be stored in the memory device (“Redundancy logic 780 includes one or more memory resources that are spares or that provide parity services, or both” Wu Paragraph [0097]), and wherein at least portion of the parity information is stored in the memory array of at least one other memory die of the plurality of the memory die (See Memory device 740 and memory resources 760 in Fig. 7).
As per claim 12, Wu teaches the memory device of claim 11 as stated above (See 35 U.S.C. 102 rejection for claim 11 for further details). Wu further teaches one memory die of the plurality of memory dies is configured to receive an entire data word to be stored at the memory device (“Redundancy logic 780 represents logic within memory device 740 to provide redundancy for memory device 740 to achieve error recovery for memory resources that store an entire cacheline of data.” Wu Paragraph [0097]).
As per claim 13, Wu teaches the memory device of claim 12 as stated above (See 35 U.S.C. 102 rejection for claim 12 for further details). Wu further teaches the error correction circuit of the one memory die is further configured to: generate the parity information for the entire data word (“Redundancy logic 780 includes one or more memory resources that are spares or that provide parity services, or both” Wu Paragraph [0097]); store a first portion of the data word and a first portion for the parity information in the memory array of the one memory die (“For a Write operation, an individual memory device 740 can write a portion of the overall data word” Wu Paragraph [0087]); and provide a second portion of the data word and a second portion of the parity information to the at least one other memory die of the plurality of the memory die to be stored in the memory array of the at least one other memory die (“The remaining bits of the word will be provided or received by other memory devices in parallel.” Wu Paragraph [0087]).
As per claim 14, Wu teaches the memory device of claim 13 as stated above (see 35 U.S.C. 102 rejection for claim 13 for further details). Wu further teaches the error correction circuit of the one memory die is further configured to: receive the first portion of the data word and the first portion of the parity information from the memory array of the one memory die (“memory device responding to a command and accessing memory resources 760 internal to each.” Wu Paragraph [0087]); receive the second portion of the data word and the second portion of the parity information from the at least one other memory die (“each stack includes 5 receivers, and each receiver is connected to the lower stack” Wu Paragraph [0068]; Wu teaches data can be transferred between dies.); and correct one or more errors in the first portion of the data and the second portion of the data using the first portion of the parity information and the second portion of the parity information (“Redundancy logic 780 represents logic within memory device 740 to provide redundancy for memory device 740 to achieve error recovery for memory resources” Wu Paragraph [0097]).
As per claim 15, Wu teaches the memory device of claim 11 as stated above (See 35 U.S.C. 102 rejection for claim 11 for further details). Wu further teaches a first memory die of the plurality of memory die is configured to receive at least a portion of an entire data word to be stored at the memory device (“For a Write operation, an individual memory device 740 can write a portion of the overall data word” Wu Paragraph [0087]), and a second memory die of the plurality of memory die is also configured to receive at least a portion of the entire data word (“The remaining bits of the word will be provided or received by other memory devices in parallel.” Wu Paragraph [0087]).
As per claim 16, Wu teaches the memory device of claim 15 as stated above (See 35 U.S.C. 102 rejection for claim 15 as stated above). Wu further teaches the error correction circuit of the second error correction circuit of the second memory die is further configured to:
generate the parity information for the entire data word (“Redundancy logic 780 represents logic within memory device 740 to provide redundancy for memory device 740 to achieve error recovery for memory resources that store an entire cacheline of data. Redundancy logic 780 includes one or more memory resources that are spares or that provide parity services, or both.” Wu Paragraph [0097]); and store a first portion of the data word and a first portion of the parity information in the memory array of the second memory die (“For a Write operation, an individual memory device 740 can write a portion of the overall data word” Wu Paragraph [0087]).
As per claim 17, Wu teaches the memory device of claim 16 as stated above (See 35 U.S.C. 102 rejection for further details). Wu further teaches the error correction circuit of the second memory die is further configured to: receive the first portion of the data word and the first portion of the parity information from the memory array of the second memory die (“memory device responding to a command, and accessing memory resources 760 internal to each.” Wu Paragraph [0087]); receive a second portion of the data word and a second portion of the parity information from the first memory die (“each stack includes 5 receivers, and each receiver is connected to the lower stack” Wu Paragraph [0068]; Wu teaches data can be transferred between dies.); and correct one or more errors in the first portion of the data using the first portion of the parity information and the second portion of the parity information (“Redundancy logic 780 represents logic within memory device 740 to provide redundancy for memory device 740 to achieve error recovery for memory resources” Wu Paragraph [0097]).
As per claim 18, Wu teaches the memory device of claim 11 as stated above (See 35 U.S.C. 102 rejection for claim 11 for further details). Wu further teaches a first memory dies of the plurality of memory die is configured to receive a first portion of a data word to be stored at the memory device (“Write operation, an individual memory device 740 can write a portion of the overall data word” Wu Paragraph [0087]), and a second memory die of the plurality of memory die is configured to receive a second portion of the data word (“The remaining bits of the word will be provided or received by other memory devices in parallel.” Wu Paragraph [0087]), and the error correction circuit of the second memory die is further configured to:
generate a first portion of the parity information for the second portion of the data word (“Redundancy logic 780 includes one or more memory resources that are spares or that provide parity services, or both.” Wu Paragraph [0097]); receive a second portion of the parity information for the first portion of the data word from the first memory die (“each stack includes 5 receivers, and each receiver is connected to the lower stack” Wu Paragraph [0068]; Wu teaches data can be transferred between memory dies.); generate combined parity information based on the first portion and the second portion of the parity information (“In one example, the value of the parity information is an XOR of all the segments of data.” Wu Paragraph [0066]); and store the second portion of the data word and a first portion of the combined parity information in the memory array of the second memory die (“Redundancy logic 780 represents logic within memory device 740 to provide redundancy for memory device 740 to achieve error recovery for memory resources that store an entire cacheline of data. Redundancy logic 780 includes one or more memory resources that are spares or that provide parity services, or both.” Wu paragraph [0097]).
As per claim 19, Wu teaches the memory device of claim 18 as stated above (See 35 U.S.C. 102 rejection for claim 18 for further details). Wu further teaches the error correction circuit of the second memory die further configured to: receive the second portion for the data word and the first portion of the combined parity information from the memory array of the second memory die (“each stack includes 5 receivers, and each receiver is connected to the lower stack” Wu Paragraph [0068]; Wu teaches data can be transferred between dies.); calculate a first sub-result based on the second portion of the data word (“In one example, the memory reads Data A[old], 604, and computes Delta=A[old] XOR A[new] locally at the memory stack, 606” Wu Paragraph [0074]; receive the second portion of the combined parity information and a second sub-result from the first memory die, wherein the second sub-result is calculated based on the first portion of the data word (“each stack includes 5 receivers, and each receiver is connected to the lower stack” Wu Paragraph [0068]; Wu teaches data being transferred between dies.); and correct one or more errors in the second portion of the data using the first portion and the second portion of the combined parity information and using the first sub-result and the second sub-result (“In one example, each die includes multiple separate XOR circuits to calculate: P_new=P_old̂ΔÂΔB̂ΔC.” Wu Paragraph [0053]).
As per claim 20, Wu teaches a method comprising: receiving, at a first memory die of a memory device, data to be stored at the memory device, the memory device comprising a plurality of memory die arranged in a vertical (“The multiple memory dies can be a vertical stack” Wu Paragraph [0025]), wherein each of plurality of memory die comprises a memory array (“Memory resources 760 represent individual arrays of memory locations or storage locations for data.” Wu paragraph [0089]) and an error correction circuit (“Redundancy logic 780 includes one or more memory resources that are spares or that provide parity services, or both” Wu Paragraph [0097]); and generating, by the error correction circuit of the first memory die, parity information for the data to be stored in the memory device (“Redundancy logic 780 includes one or more memory resources that are spares or that provide parity services, or both” Wu Paragraph [0097]), wherein at least a portion of the parity information is stored in the memory array of at least one other memory die of the plurality of the memory die (“The remaining bits of the word will be provided or received by other memory devices in parallel.” Wu Paragraph [0087]).
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure.
US 20130097471 A1 teaches a stack of memory dies with user data and/or first level error correction data stored in a stripe across the memory dies. One such stack can include a second level error correction vault, such as a parity vault, to store parity data corresponding to the user data and/or first level error correction data.
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/J.J./Examiner, Art Unit 2112
/ESAW T ABRAHAM/Primary Examiner, Art Unit 2112
